Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T119,T196,T104
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15658	0	0
DisabledNoTrigBkwd_A	2147483647	806304	0	0
DisabledNoTrigFwd_A	2147483647	1637837242	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15658	0	0
T21	40419	0	0	0
T26	765422	0	0	0
T52	600234	0	0	0
T53	26287	0	0	0
T54	646993	0	0	0
T55	248008	0	0	0
T71	139467	0	0	0
T104	1224	424	0	0
T119	2834	574	0	0
T196	0	421	0	0
T197	1317	557	0	0
T198	0	731	0	0
T199	0	1428	0	0
T200	0	958	0	0
T201	0	873	0	0
T202	0	640	0	0
T203	0	750	0	0
T204	0	481	0	0
T205	0	1260	0	0
T206	0	1158	0	0
T207	0	755	0	0
T208	0	331	0	0
T209	0	1043	0	0
T210	0	647	0	0
T211	0	864	0	0
T212	0	671	0	0
T213	0	1092	0	0
T214	39813	0	0	0
T215	24941	0	0	0
T216	100408	0	0	0
T217	679139	0	0	0
T218	3933	0	0	0
T219	11188	0	0	0
T220	7566	0	0	0
T221	292707	0	0	0
T222	18133	0	0	0
T223	14261	0	0	0
T224	234833	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	806304	0	0
T1	793776	1595	0	0
T2	2055060	6	0	0
T3	466828	7731	0	0
T4	465788	10	0	0
T5	0	25	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	2377	0	0
T12	0	1685	0	0
T14	121804	26	0	0
T15	152956	12	0	0
T16	3637288	3902	0	0
T17	352828	90	0	0
T18	0	3	0	0
T20	0	44	0	0
T42	0	287	0	0
T43	0	3	0	0
T44	0	280	0	0
T46	0	1373	0	0
T47	0	2441	0	0
T48	0	434	0	0
T49	0	28	0	0
T50	71405	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1637837242	0	0
T1	1058368	8389	0	0
T2	2055060	1033824	0	0
T3	466828	126768	0	0
T4	465788	661822	0	0
T10	877136	659843	0	0
T11	1714848	1331373	0	0
T14	121804	103177	0	0
T15	152956	121518	0	0
T16	3637288	2224428	0	0
T17	352828	267602	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T3,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T208,T210
1	1	Covered	T1,T3,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724532356	1535	0	0
DisabledNoTrigBkwd_A	724532356	297254	0	0
DisabledNoTrigFwd_A	724532356	356571526	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1535	0	0
T21	40419	0	0	0
T197	1317	557	0	0
T208	0	331	0	0
T210	0	647	0	0
T217	679139	0	0	0
T218	3933	0	0	0
T219	11188	0	0	0
T220	7566	0	0	0
T221	292707	0	0	0
T222	18133	0	0	0
T223	14261	0	0	0
T224	234833	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	297254	0	0
T1	264592	554	0	0
T2	513765	0	0	0
T3	116707	2214	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	2371	0	0
T12	0	880	0	0
T14	30451	26	0	0
T15	38239	2	0	0
T16	909322	1534	0	0
T17	88207	90	0	0
T20	0	44	0	0
T43	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	356571526	0	0
T1	264592	2069	0	0
T2	513765	511999	0	0
T3	116707	4867	0	0
T4	116447	2818	0	0
T10	219284	2021	0	0
T11	428712	47152	0	0
T14	30451	11974	0	0
T15	38239	33900	0	0
T16	909322	801745	0	0
T17	88207	3164	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T119,T196,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724532356	6116	0	0
DisabledNoTrigBkwd_A	724532356	167777	0	0
DisabledNoTrigFwd_A	724532356	409497255	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	6116	0	0
T26	765422	0	0	0
T52	600234	0	0	0
T53	26287	0	0	0
T54	646993	0	0	0
T55	248008	0	0	0
T71	139467	0	0	0
T119	2834	574	0	0
T196	0	421	0	0
T199	0	1428	0	0
T202	0	640	0	0
T203	0	750	0	0
T205	0	1260	0	0
T209	0	1043	0	0
T214	39813	0	0	0
T215	24941	0	0	0
T216	100408	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	167777	0	0
T2	513765	6	0	0
T3	116707	6	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	805	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	496	0	0
T17	88207	0	0	0
T42	0	108	0	0
T44	0	116	0	0
T46	0	1037	0	0
T49	0	28	0	0
T50	71405	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	409497255	0	0
T1	264592	2092	0	0
T2	513765	2766	0	0
T3	116707	116186	0	0
T4	116447	501515	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	29525	0	0
T16	909322	754813	0	0
T17	88207	88146	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T104,T200,T204
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724532356	5311	0	0
DisabledNoTrigBkwd_A	724532356	192207	0	0
DisabledNoTrigFwd_A	724532356	434747276	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	5311	0	0
T30	188436	0	0	0
T57	101456	0	0	0
T77	13105	0	0	0
T104	1224	424	0	0
T105	80219	0	0	0
T106	190177	0	0	0
T107	7828	0	0	0
T108	11188	0	0	0
T200	0	958	0	0
T204	0	481	0	0
T206	0	1158	0	0
T207	0	755	0	0
T211	0	864	0	0
T212	0	671	0	0
T225	142176	0	0	0
T226	36144	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	192207	0	0
T1	264592	742	0	0
T2	513765	0	0	0
T3	116707	2385	0	0
T4	116447	0	0	0
T5	0	24	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	179	0	0
T44	0	3	0	0
T46	0	229	0	0
T48	0	434	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	434747276	0	0
T1	264592	2110	0	0
T2	513765	511535	0	0
T3	116707	2155	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428169	0	0
T14	30451	30401	0	0
T15	38239	34583	0	0
T16	909322	458411	0	0
T17	88207	88146	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T14
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T201,T213
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724532356	2696	0	0
DisabledNoTrigBkwd_A	724532356	149066	0	0
DisabledNoTrigFwd_A	724532356	437021185	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	2696	0	0
T198	1432	731	0	0
T199	4611	0	0	0
T201	0	873	0	0
T213	0	1092	0	0
T227	9857	0	0	0
T228	285308	0	0	0
T229	454816	0	0	0
T230	31867	0	0	0
T231	492317	0	0	0
T232	130947	0	0	0
T233	20288	0	0	0
T234	35456	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	149066	0	0
T1	264592	299	0	0
T2	513765	0	0	0
T3	116707	3126	0	0
T4	116447	10	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	6	0	0
T14	30451	0	0	0
T15	38239	6	0	0
T16	909322	1869	0	0
T17	88207	0	0	0
T44	0	161	0	0
T46	0	107	0	0
T47	0	2441	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	437021185	0	0
T1	264592	2118	0	0
T2	513765	7524	0	0
T3	116707	3560	0	0
T4	116447	41047	0	0
T10	219284	219274	0	0
T11	428712	427347	0	0
T14	30451	30401	0	0
T15	38239	23510	0	0
T16	909322	209459	0	0
T17	88207	88146	0	0