Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T15,T16
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T11
1	1	1	Covered	T14,T16,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T11
0	1	Covered	T16,T18,T19
1	0	Covered	T14,T16,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T16,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T11
1	0	Covered	T21
1	1	Covered	T16,T18,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T17,T11

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T14,T16,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T14,T16,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T19,T22,T23
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T20,T19,T24
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T16,T25,T26
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T27,T28
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T16,T11,T29
TimeoutSt->Phase0St	172	Covered	T14,T16,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T11,T29
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T22,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T19,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T25,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T27,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1257	0	0
CheckAccumTrig0_A	2147483647	2381	0	0
CheckAccumTrig1_A	2147483647	83	0	0
CheckClr_A	2147483647	1137	0	0
CheckEn_A	2147483647	1282838103	0	0
CheckPhase0_A	2147483647	2666	0	0
CheckPhase1_A	2147483647	2626	0	0
CheckPhase2_A	2147483647	2570	0	0
CheckPhase3_A	2147483647	2511	0	0
CheckTimeout0_A	2147483647	5786	0	0
CheckTimeoutSt1_A	2147483647	532439	0	0
CheckTimeoutSt2_A	2147483647	5443	0	0
CheckTimeoutStTrig_A	2147483647	253	0	0
ErrorStAllEscAsserted_A	2147483647	6435	0	0
ErrorStIsTerminal_A	2147483647	5355	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1257	0	0
T7	152188	200	0	0
T8	0	291	0	0
T9	0	329	0	0
T31	0	167	0	0
T32	0	270	0	0
T33	1233536	0	0	0
T34	642152	0	0	0
T35	144596	0	0	0
T36	3815000	0	0	0
T37	1037124	0	0	0
T38	27448	0	0	0
T39	506316	0	0	0
T40	156508	0	0	0
T41	60812	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T1	793776	10	0	0
T2	2055060	2	0	0
T3	466828	5	0	0
T4	465788	1	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	4	0	0
T12	0	2	0	0
T14	121804	0	0	0
T15	152956	5	0	0
T16	3637288	14	0	0
T17	352828	4	0	0
T18	0	3	0	0
T20	0	3	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	71405	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	83	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T14	30451	1	0	0
T15	38239	0	0	0
T16	909322	2	0	0
T17	88207	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T26	765422	1	0	0
T28	267022	2	0	0
T41	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	646993	1	0	0
T55	248008	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	68246	0	0	0
T65	12094	0	0	0
T66	6986	0	0	0
T67	572918	0	0	0
T68	560930	0	0	0
T69	599043	0	0	0
T70	24298	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1137	0	0
T1	793776	6	0	0
T2	2055060	1	0	0
T3	466828	1	0	0
T4	465788	0	0	0
T10	877136	0	0	0
T11	1714848	2	0	0
T14	121804	0	0	0
T15	152956	0	0	0
T16	3637288	6	0	0
T17	352828	3	0	0
T18	0	4	0	0
T19	0	14	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	4	0	0
T25	0	9	0	0
T27	0	1	0	0
T28	0	5	0	0
T43	0	3	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	71405	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1282838103	0	0
T1	1058368	8389	0	0
T2	2055060	1033824	0	0
T3	466828	11250	0	0
T4	465788	661822	0	0
T10	877136	659843	0	0
T11	1714848	947324	0	0
T14	121804	91821	0	0
T15	152956	56549	0	0
T16	3637288	1748110	0	0
T17	352828	267599	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2666	0	0
T1	793776	10	0	0
T2	2055060	2	0	0
T3	466828	5	0	0
T4	465788	1	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	4	0	0
T12	0	2	0	0
T14	121804	1	0	0
T15	152956	5	0	0
T16	3637288	18	0	0
T17	352828	4	0	0
T18	0	5	0	0
T20	0	4	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	3	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	1	0	0
T50	71405	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2626	0	0
T1	793776	10	0	0
T2	2055060	2	0	0
T3	466828	5	0	0
T4	465788	1	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	4	0	0
T12	0	2	0	0
T14	121804	1	0	0
T15	152956	5	0	0
T16	3637288	18	0	0
T17	352828	4	0	0
T18	0	5	0	0
T20	0	3	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	3	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	1	0	0
T50	71405	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2570	0	0
T1	793776	10	0	0
T2	2055060	2	0	0
T3	466828	5	0	0
T4	465788	1	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	4	0	0
T12	0	2	0	0
T14	121804	1	0	0
T15	152956	5	0	0
T16	3637288	17	0	0
T17	352828	4	0	0
T18	0	5	0	0
T20	0	3	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	3	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	1	0	0
T50	71405	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2511	0	0
T1	793776	10	0	0
T2	2055060	2	0	0
T3	466828	5	0	0
T4	465788	1	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	877136	0	0	0
T11	1714848	4	0	0
T12	0	2	0	0
T14	121804	1	0	0
T15	152956	5	0	0
T16	3637288	16	0	0
T17	352828	4	0	0
T18	0	5	0	0
T20	0	3	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	3	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	1	0	0
T50	71405	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5786	0	0
T5	366213	0	0	0
T10	877136	0	0	0
T11	1714848	1	0	0
T12	2298988	0	0	0
T14	30451	1	0	0
T15	38239	0	0	0
T16	3637288	42	0	0
T17	352828	0	0	0
T18	0	4	0	0
T19	0	9	0	0
T20	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	5	0	0
T26	0	14	0	0
T28	0	706	0	0
T29	0	1	0	0
T42	509520	0	0	0
T43	232940	0	0	0
T46	0	2	0	0
T49	0	4	0	0
T50	285620	0	0	0
T51	0	1	0	0
T55	0	16	0	0
T65	0	3	0	0
T69	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	9450	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	532439	0	0
T5	366213	0	0	0
T10	877136	0	0	0
T11	1714848	30	0	0
T12	2298988	0	0	0
T14	30451	2	0	0
T15	38239	0	0	0
T16	3637288	4185	0	0
T17	352828	0	0	0
T18	0	879	0	0
T19	0	2225	0	0
T20	0	1	0	0
T22	0	297	0	0
T23	0	200	0	0
T24	0	367	0	0
T25	0	453	0	0
T26	0	2216	0	0
T28	0	53065	0	0
T29	0	32	0	0
T42	509520	0	0	0
T43	232940	0	0	0
T46	0	126	0	0
T49	0	1395	0	0
T50	285620	0	0	0
T51	0	8	0	0
T55	0	3314	0	0
T65	0	621	0	0
T69	0	102	0	0
T72	0	376	0	0
T73	0	282	0	0
T74	9450	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5443	0	0
T5	488284	0	0	0
T10	877136	0	0	0
T11	1714848	1	0	0
T12	2298988	0	0	0
T16	3637288	38	0	0
T17	352828	0	0	0
T18	0	2	0	0
T19	0	7	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	0	4	0	0
T26	0	23	0	0
T28	0	699	0	0
T29	0	1	0	0
T30	0	2	0	0
T42	509520	0	0	0
T43	232940	0	0	0
T46	0	2	0	0
T49	0	4	0	0
T50	285620	0	0	0
T54	0	3	0	0
T55	0	20	0	0
T65	0	1	0	0
T69	0	11	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	12600	0	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	1	0	0
T17	88207	0	0	0
T18	19869	2	0	0
T19	261562	1	0	0
T22	208310	0	0	0
T23	301836	0	0	0
T24	310856	1	0	0
T25	19099	0	0	0
T26	0	3	0	0
T28	534044	3	0	0
T30	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	21771	0	0	0
T50	71405	0	0	0
T51	204640	0	0	0
T55	0	1	0	0
T57	0	4	0	0
T65	0	2	0	0
T69	0	1	0	0
T72	32903	0	0	0
T73	295805	1	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	37380	0	0	0
T85	308590	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6435	0	0
T7	152188	1376	0	0
T8	0	1486	0	0
T9	0	1427	0	0
T31	0	732	0	0
T32	0	1414	0	0
T33	1233536	0	0	0
T34	642152	0	0	0
T35	144596	0	0	0
T36	3815000	0	0	0
T37	1037124	0	0	0
T38	27448	0	0	0
T39	506316	0	0	0
T40	156508	0	0	0
T41	60812	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5355	0	0
T7	152188	1136	0	0
T8	0	1246	0	0
T9	0	1187	0	0
T31	0	612	0	0
T32	0	1174	0	0
T33	1233536	0	0	0
T34	642152	0	0	0
T35	144596	0	0	0
T36	3815000	0	0	0
T37	1037124	0	0	0
T38	27448	0	0	0
T39	506316	0	0	0
T40	156508	0	0	0
T41	60812	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1058368	1058348	0	0
T2	2055060	2055024	0	0
T3	466828	466800	0	0
T4	465788	465768	0	0
T10	877136	877096	0	0
T11	1714848	1714820	0	0
T14	121804	121604	0	0
T15	152956	152740	0	0
T16	3637288	3637240	0	0
T17	352828	352584	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1058368	1058348	0	0
T2	2055060	2055024	0	0
T3	466828	466800	0	0
T4	465788	465768	0	0
T10	877136	877096	0	0
T11	1714848	1714820	0	0
T14	121804	121604	0	0
T15	152956	152740	0	0
T16	3637288	3637240	0	0
T17	352828	352584	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T16,T17
1	0	1	Covered	T16,T10,T17
1	1	0	Covered	T16,T11,T74
1	1	1	Covered	T14,T16,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T20
0	1	Covered	T19,T26,T65
1	0	Covered	T14,T16,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T20
1	0	Not Covered
1	1	Covered	T19,T26,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T14,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T17,T11,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T16,T17,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T14,T16
1	Covered	T3,T15,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T14,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T15,T16,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T14
Phase1St	198	Covered	T1,T3,T14
Phase2St	215	Covered	T1,T3,T14
Phase3St	233	Covered	T1,T3,T14
TerminalSt	249	Covered	T1,T3,T14
TimeoutSt	159	Covered	T14,T16,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T15
IdleSt->TimeoutSt	159	Covered	T14,T16,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T23,T28
Phase0St->Phase1St	198	Covered	T1,T3,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T55,T86
Phase1St->Phase2St	215	Covered	T1,T3,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T16,T26,T57
Phase2St->Phase3St	233	Covered	T1,T3,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T27,T79
Phase3St->TerminalSt	249	Covered	T1,T3,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T16,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T29,T22
TimeoutSt->Phase0St	172	Covered	T14,T16,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T29,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T37,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T55,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T26,T57
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T27,T79
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T14,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724532356	310	0	0
CheckAccumTrig0_A	724532356	897	0	0
CheckAccumTrig1_A	724532356	36	0	0
CheckClr_A	724532356	469	0	0
CheckEn_A	724220815	278322271	0	0
CheckPhase0_A	724532356	979	0	0
CheckPhase1_A	724532356	962	0	0
CheckPhase2_A	724532356	938	0	0
CheckPhase3_A	724532356	916	0	0
CheckTimeout0_A	724532356	992	0	0
CheckTimeoutSt1_A	724532356	102760	0	0
CheckTimeoutSt2_A	724532356	885	0	0
CheckTimeoutStTrig_A	724532356	68	0	0
ErrorStAllEscAsserted_A	724532356	1624	0	0
ErrorStIsTerminal_A	724532356	1354	0	0
EscStateOut_A	724219181	724146513	0	0
u_state_regs_A	724532356	724345464	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	310	0	0
T7	38047	46	0	0
T8	0	80	0	0
T9	0	91	0	0
T31	0	28	0	0
T32	0	65	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	897	0	0
T1	264592	6	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	3	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	7	0	0
T17	88207	4	0	0
T20	0	3	0	0
T43	0	3	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	36	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T14	30451	1	0	0
T15	38239	0	0	0
T16	909322	2	0	0
T17	88207	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	469	0	0
T1	264592	5	0	0
T2	513765	0	0	0
T3	116707	0	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	2	0	0
T14	30451	0	0	0
T15	38239	0	0	0
T16	909322	6	0	0
T17	88207	3	0	0
T19	0	5	0	0
T20	0	3	0	0
T23	0	2	0	0
T27	0	1	0	0
T43	0	3	0	0
T46	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724220815	278322271	0	0
T1	264592	2069	0	0
T2	513765	511999	0	0
T3	116707	3548	0	0
T4	116447	2818	0	0
T10	219284	2021	0	0
T11	428712	45250	0	0
T14	30451	621	0	0
T15	38239	2058	0	0
T16	909322	801745	0	0
T17	88207	3164	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	979	0	0
T1	264592	6	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	3	0	0
T12	0	1	0	0
T14	30451	1	0	0
T15	38239	1	0	0
T16	909322	9	0	0
T17	88207	4	0	0
T20	0	4	0	0
T43	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	962	0	0
T1	264592	6	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	3	0	0
T12	0	1	0	0
T14	30451	1	0	0
T15	38239	1	0	0
T16	909322	9	0	0
T17	88207	4	0	0
T20	0	3	0	0
T43	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	938	0	0
T1	264592	6	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	3	0	0
T12	0	1	0	0
T14	30451	1	0	0
T15	38239	1	0	0
T16	909322	8	0	0
T17	88207	4	0	0
T20	0	3	0	0
T43	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	916	0	0
T1	264592	6	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	3	0	0
T12	0	1	0	0
T14	30451	1	0	0
T15	38239	1	0	0
T16	909322	7	0	0
T17	88207	4	0	0
T20	0	3	0	0
T43	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	992	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T14	30451	1	0	0
T15	38239	0	0	0
T16	909322	21	0	0
T17	88207	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	0	5	0	0
T28	0	3	0	0
T29	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T51	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	102760	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T14	30451	2	0	0
T15	38239	0	0	0
T16	909322	1131	0	0
T17	88207	0	0	0
T19	0	28	0	0
T20	0	1	0	0
T22	0	297	0	0
T23	0	200	0	0
T25	0	453	0	0
T28	0	209	0	0
T29	0	32	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T51	0	8	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	885	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	19	0	0
T17	88207	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T25	0	4	0	0
T26	0	13	0	0
T28	0	3	0	0
T29	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T55	0	7	0	0
T69	0	9	0	0
T74	3150	0	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	68	0	0
T19	130781	1	0	0
T22	104155	0	0	0
T23	150918	0	0	0
T24	155428	0	0	0
T25	19099	0	0	0
T26	0	1	0	0
T28	267022	0	0	0
T51	102320	0	0	0
T57	0	2	0	0
T65	0	1	0	0
T73	295805	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T79	0	4	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	18690	0	0	0
T85	308590	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1624	0	0
T7	38047	328	0	0
T8	0	378	0	0
T9	0	375	0	0
T31	0	191	0	0
T32	0	352	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1354	0	0
T7	38047	268	0	0
T8	0	318	0	0
T9	0	315	0	0
T31	0	161	0	0
T32	0	292	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724219181	724146513	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	724345464	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T20,T46
1	0	1	Covered	T1,T16,T42
1	1	0	Covered	T16,T74,T46
1	1	1	Covered	T16,T18,T49

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T49
0	1	Covered	T18,T24,T73
1	0	Covered	T26,T56,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T18,T49
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T56,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T49
1	0	Not Covered
1	1	Covered	T18,T24,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T12,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T16,T42,T44

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T2,T3,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T15,T16,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T16,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T46,T49

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T15
Phase1St	198	Covered	T2,T3,T15
Phase2St	215	Covered	T2,T3,T15
Phase3St	233	Covered	T2,T3,T15
TerminalSt	249	Covered	T2,T3,T15
TimeoutSt	159	Covered	T16,T18,T49

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T15
IdleSt->TimeoutSt	159	Covered	T16,T18,T49
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T55,T88
Phase0St->Phase1St	198	Covered	T2,T3,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T25,T71
Phase1St->Phase2St	215	Covered	T2,T3,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T57,T89
Phase2St->Phase3St	233	Covered	T2,T3,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T59,T90
Phase3St->TerminalSt	249	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T16,T46
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T18,T49
TimeoutSt->Phase0St	172	Covered	T18,T24,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T49
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T49
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T88,T59
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T25,T71
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T57,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T59,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724532356	282	0	0
CheckAccumTrig0_A	724532356	491	0	0
CheckAccumTrig1_A	724532356	16	0	0
CheckClr_A	724532356	204	0	0
CheckEn_A	724220815	312177953	0	0
CheckPhase0_A	724532356	558	0	0
CheckPhase1_A	724532356	548	0	0
CheckPhase2_A	724532356	539	0	0
CheckPhase3_A	724532356	525	0	0
CheckTimeout0_A	724532356	1425	0	0
CheckTimeoutSt1_A	724532356	139846	0	0
CheckTimeoutSt2_A	724532356	1347	0	0
CheckTimeoutStTrig_A	724532356	61	0	0
ErrorStAllEscAsserted_A	724532356	1609	0	0
ErrorStIsTerminal_A	724532356	1339	0	0
EscStateOut_A	724219181	724146513	0	0
u_state_regs_A	724532356	724345464	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	282	0	0
T7	38047	46	0	0
T8	0	52	0	0
T9	0	73	0	0
T31	0	40	0	0
T32	0	71	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	491	0	0
T2	513765	2	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T49	0	1	0	0
T50	71405	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	16	0	0
T26	765422	1	0	0
T41	0	1	0	0
T54	646993	0	0	0
T55	248008	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	68246	0	0	0
T65	12094	0	0	0
T66	6986	0	0	0
T67	572918	0	0	0
T68	560930	0	0	0
T69	599043	0	0	0
T70	24298	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	204	0	0
T2	513765	1	0	0
T3	116707	0	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	0	0	0
T16	909322	0	0	0
T17	88207	0	0	0
T18	0	2	0	0
T19	0	6	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T28	0	1	0	0
T50	71405	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724220815	312177953	0	0
T1	264592	2092	0	0
T2	513765	2766	0	0
T3	116707	1987	0	0
T4	116447	501515	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30400	0	0
T15	38239	2080	0	0
T16	909322	528130	0	0
T17	88207	88145	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	558	0	0
T2	513765	2	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T50	71405	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	548	0	0
T2	513765	2	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T50	71405	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	539	0	0
T2	513765	2	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T50	71405	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	525	0	0
T2	513765	2	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T6	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	0	1	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T50	71405	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1425	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	6	0	0
T17	88207	0	0	0
T18	0	4	0	0
T19	0	2	0	0
T24	0	1	0	0
T26	0	6	0	0
T28	0	179	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	1	0	0
T50	71405	0	0	0
T55	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	3150	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	139846	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	1356	0	0
T17	88207	0	0	0
T18	0	879	0	0
T19	0	561	0	0
T24	0	152	0	0
T26	0	747	0	0
T28	0	13710	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	461	0	0
T50	71405	0	0	0
T55	0	158	0	0
T72	0	185	0	0
T73	0	33	0	0
T74	3150	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1347	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	6	0	0
T17	88207	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T26	0	4	0	0
T28	0	178	0	0
T30	0	2	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	1	0	0
T50	71405	0	0	0
T55	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T74	3150	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	61	0	0
T18	19869	2	0	0
T19	130781	0	0	0
T22	104155	0	0	0
T23	150918	0	0	0
T24	155428	1	0	0
T26	0	1	0	0
T28	267022	0	0	0
T30	0	1	0	0
T49	21771	0	0	0
T51	102320	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T72	32903	0	0	0
T73	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T84	18690	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1609	0	0
T7	38047	342	0	0
T8	0	380	0	0
T9	0	346	0	0
T31	0	178	0	0
T32	0	363	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1339	0	0
T7	38047	282	0	0
T8	0	320	0	0
T9	0	286	0	0
T31	0	148	0	0
T32	0	303	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724219181	724146513	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	724345464	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T11
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T16,T11,T74
1	1	1	Covered	T16,T11,T49

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T11,T49
0	1	Covered	T16,T19,T26
1	0	Covered	T76,T78,T91

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T11,T49
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T76,T78,T91

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T11,T49
1	0	Not Covered
1	1	Covered	T16,T19,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T1,T3,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T15,T16,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T16,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T16,T46

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T16,T11,T49

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T16,T11,T49
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T54,T60
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T57,T92,T93
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T69,T94
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T19,T55,T95
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T15,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T11,T49
TimeoutSt->Phase0St	172	Covered	T16,T19,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T11,T49
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T19,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T11,T49
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T11,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T54,T60
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T57,T92,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T69,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T55,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T15,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724532356	343	0	0
CheckAccumTrig0_A	724532356	504	0	0
CheckAccumTrig1_A	724532356	15	0	0
CheckClr_A	724532356	249	0	0
CheckEn_A	724220815	343609793	0	0
CheckPhase0_A	724532356	582	0	0
CheckPhase1_A	724532356	578	0	0
CheckPhase2_A	724532356	565	0	0
CheckPhase3_A	724532356	554	0	0
CheckTimeout0_A	724532356	1890	0	0
CheckTimeoutSt1_A	724532356	149208	0	0
CheckTimeoutSt2_A	724532356	1803	0	0
CheckTimeoutStTrig_A	724532356	69	0	0
ErrorStAllEscAsserted_A	724532356	1582	0	0
ErrorStIsTerminal_A	724532356	1312	0	0
EscStateOut_A	724219181	724146513	0	0
u_state_regs_A	724532356	724345464	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	343	0	0
T7	38047	57	0	0
T8	0	90	0	0
T9	0	68	0	0
T31	0	51	0	0
T32	0	77	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	504	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	1	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	2	0	0
T17	88207	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	15	0	0
T21	0	1	0	0
T30	188436	0	0	0
T76	56156	1	0	0
T78	0	1	0	0
T86	0	1	0	0
T91	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	133825	0	0	0
T102	716695	0	0	0
T103	114073	0	0	0
T104	1224	0	0	0
T105	80219	0	0	0
T106	190177	0	0	0
T107	7828	0	0	0
T108	11188	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	249	0	0
T1	264592	1	0	0
T2	513765	0	0	0
T3	116707	0	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	0	0	0
T17	88207	0	0	0
T19	0	5	0	0
T22	0	4	0	0
T23	0	3	0	0
T24	0	3	0	0
T28	0	7	0	0
T46	0	1	0	0
T47	0	2	0	0
T52	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724220815	343609793	0	0
T1	264592	2118	0	0
T2	513765	7524	0	0
T3	116707	3560	0	0
T4	116447	41047	0	0
T10	219284	219274	0	0
T11	428712	45200	0	0
T14	30451	30400	0	0
T15	38239	19396	0	0
T16	909322	209458	0	0
T17	88207	88145	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	582	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	1	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	578	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	1	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	565	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	1	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	554	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	1	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T14	30451	0	0	0
T15	38239	2	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1890	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T12	574747	0	0	0
T16	909322	8	0	0
T17	88207	0	0	0
T19	0	6	0	0
T24	0	1	0	0
T26	0	5	0	0
T28	0	260	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	1	0	0
T50	71405	0	0	0
T54	0	6	0	0
T55	0	9	0	0
T66	0	1	0	0
T74	3150	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	149208	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	30	0	0
T12	574747	0	0	0
T16	909322	622	0	0
T17	88207	0	0	0
T19	0	1636	0	0
T24	0	215	0	0
T26	0	830	0	0
T28	0	18142	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	471	0	0
T50	71405	0	0	0
T54	0	2053	0	0
T55	0	1031	0	0
T66	0	3	0	0
T74	3150	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1803	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	1	0	0
T12	574747	0	0	0
T16	909322	7	0	0
T17	88207	0	0	0
T19	0	5	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	0	259	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T49	0	1	0	0
T50	71405	0	0	0
T54	0	3	0	0
T55	0	7	0	0
T66	0	1	0	0
T74	3150	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	69	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	1	0	0
T17	88207	0	0	0
T19	0	1	0	0
T26	0	1	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T54	0	3	0	0
T55	0	2	0	0
T74	3150	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1582	0	0
T7	38047	355	0	0
T8	0	364	0	0
T9	0	338	0	0
T31	0	182	0	0
T32	0	343	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1312	0	0
T7	38047	295	0	0
T8	0	304	0	0
T9	0	278	0	0
T31	0	152	0	0
T32	0	283	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724219181	724146513	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	724345464	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T11
1	0	1	Covered	T1,T3,T16
1	1	0	Covered	T15,T16,T11
1	1	1	Covered	T16,T46,T49

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T46,T49
0	1	Covered	T16,T28,T26
1	0	Covered	T28,T65,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T46,T49
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T65,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T46,T49
1	0	Covered	T21
1	1	Covered	T16,T28,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T16,T19,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T16,T48,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T3,T15,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T3,T42

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T16,T42,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T15
Phase1St	198	Covered	T1,T3,T15
Phase2St	215	Covered	T1,T3,T15
Phase3St	233	Covered	T1,T3,T15
TerminalSt	249	Covered	T1,T3,T15
TimeoutSt	159	Covered	T16,T46,T49

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T15
IdleSt->TimeoutSt	159	Covered	T16,T46,T49
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T55,T30
Phase0St->Phase1St	198	Covered	T1,T3,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T109,T59
Phase1St->Phase2St	215	Covered	T1,T3,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T55,T109,T110
Phase2St->Phase3St	233	Covered	T1,T3,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T26,T111
Phase3St->TerminalSt	249	Covered	T1,T3,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T46,T49
TimeoutSt->Phase0St	172	Covered	T16,T28,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T46,T49
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T28,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T46,T49
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T46,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T88,T60
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T109,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T55,T109,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T26,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724532356	322	0	0
CheckAccumTrig0_A	724532356	489	0	0
CheckAccumTrig1_A	724532356	16	0	0
CheckClr_A	724532356	215	0	0
CheckEn_A	724220815	348728086	0	0
CheckPhase0_A	724532356	547	0	0
CheckPhase1_A	724532356	538	0	0
CheckPhase2_A	724532356	528	0	0
CheckPhase3_A	724532356	516	0	0
CheckTimeout0_A	724532356	1479	0	0
CheckTimeoutSt1_A	724532356	140625	0	0
CheckTimeoutSt2_A	724532356	1408	0	0
CheckTimeoutStTrig_A	724532356	55	0	0
ErrorStAllEscAsserted_A	724532356	1620	0	0
ErrorStIsTerminal_A	724532356	1350	0	0
EscStateOut_A	724219181	724146513	0	0
u_state_regs_A	724532356	724345464	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	322	0	0
T7	38047	51	0	0
T8	0	69	0	0
T9	0	97	0	0
T31	0	48	0	0
T32	0	57	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	489	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	2	0	0
T4	116447	0	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	2	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	16	0	0
T25	19099	0	0	0
T28	267022	2	0	0
T51	102320	0	0	0
T52	600234	0	0	0
T53	26287	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T73	295805	0	0	0
T84	18690	0	0	0
T85	308590	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	486514	0	0	0
T119	2834	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	215	0	0
T1	264592	1	0	0
T2	513765	0	0	0
T3	116707	1	0	0
T4	116447	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	0	0	0
T16	909322	0	0	0
T17	88207	0	0	0
T18	0	2	0	0
T19	0	3	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	2	0	0
T28	0	4	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724220815	348728086	0	0
T1	264592	2110	0	0
T2	513765	511535	0	0
T3	116707	2155	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428169	0	0
T14	30451	30400	0	0
T15	38239	33015	0	0
T16	909322	208777	0	0
T17	88207	88145	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	547	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	2	0	0
T4	116447	0	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	538	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	2	0	0
T4	116447	0	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	528	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	2	0	0
T4	116447	0	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	516	0	0
T1	264592	2	0	0
T2	513765	0	0	0
T3	116707	2	0	0
T4	116447	0	0	0
T5	0	1	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T14	30451	0	0	0
T15	38239	1	0	0
T16	909322	3	0	0
T17	88207	0	0	0
T18	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1479	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	7	0	0
T17	88207	0	0	0
T26	0	3	0	0
T28	0	264	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T46	0	2	0	0
T49	0	2	0	0
T50	71405	0	0	0
T55	0	5	0	0
T65	0	3	0	0
T69	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	3150	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	140625	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	1076	0	0
T17	88207	0	0	0
T26	0	639	0	0
T28	0	21004	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T46	0	126	0	0
T49	0	463	0	0
T50	71405	0	0	0
T55	0	2125	0	0
T65	0	621	0	0
T69	0	102	0	0
T72	0	191	0	0
T73	0	249	0	0
T74	3150	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1408	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	6	0	0
T17	88207	0	0	0
T26	0	2	0	0
T28	0	259	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T46	0	2	0	0
T49	0	2	0	0
T50	71405	0	0	0
T55	0	5	0	0
T65	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	3150	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	55	0	0
T5	122071	0	0	0
T10	219284	0	0	0
T11	428712	0	0	0
T12	574747	0	0	0
T16	909322	1	0	0
T17	88207	0	0	0
T26	0	1	0	0
T28	0	3	0	0
T42	127380	0	0	0
T43	58235	0	0	0
T50	71405	0	0	0
T57	0	1	0	0
T65	0	1	0	0
T74	3150	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1620	0	0
T7	38047	351	0	0
T8	0	364	0	0
T9	0	368	0	0
T31	0	181	0	0
T32	0	356	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	1350	0	0
T7	38047	291	0	0
T8	0	304	0	0
T9	0	308	0	0
T31	0	151	0	0
T32	0	296	0	0
T33	308384	0	0	0
T34	160538	0	0	0
T35	36149	0	0	0
T36	953750	0	0	0
T37	259281	0	0	0
T38	6862	0	0	0
T39	126579	0	0	0
T40	39127	0	0	0
T41	15203	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724219181	724146513	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724532356	724345464	0	0
T1	264592	264587	0	0
T2	513765	513756	0	0
T3	116707	116700	0	0
T4	116447	116442	0	0
T10	219284	219274	0	0
T11	428712	428705	0	0
T14	30451	30401	0	0
T15	38239	38185	0	0
T16	909322	909310	0	0
T17	88207	88146	0	0