Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T118,T83
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15564	0	0
DisabledNoTrigBkwd_A	2147483647	905831	0	0
DisabledNoTrigFwd_A	2147483647	1468267424	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15564	0	0
T3	4306	761	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T10	722228	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	52438	0	0	0
T21	17666	0	0	0
T22	73733	0	0	0
T23	41590	0	0	0
T29	136828	0	0	0
T45	34009	0	0	0
T46	974295	0	0	0
T71	44100	0	0	0
T81	2871	0	0	0
T82	11210	0	0	0
T83	8968	976	0	0
T118	3438	602	0	0
T198	0	707	0	0
T199	0	1090	0	0
T200	0	1320	0	0
T201	0	1052	0	0
T202	0	1159	0	0
T203	0	408	0	0
T204	0	668	0	0
T205	0	682	0	0
T206	0	306	0	0
T207	0	632	0	0
T208	0	449	0	0
T209	0	1014	0	0
T210	0	813	0	0
T211	0	726	0	0
T212	0	609	0	0
T213	0	717	0	0
T214	0	873	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	905831	0	0
T1	900540	1353	0	0
T2	1464980	216	0	0
T3	17224	5	0	0
T4	2675816	10432	0	0
T5	1219792	0	0	0
T6	3626256	3553	0	0
T8	0	2111	0	0
T9	984600	14778	0	0
T10	0	10	0	0
T15	0	4537	0	0
T16	103868	45	0	0
T17	232208	1	0	0
T18	140952	49	0	0
T22	0	11	0	0
T23	0	2	0	0
T28	0	16	0	0
T29	0	4	0	0
T43	0	84	0	0
T44	0	172	0	0
T45	0	2	0	0
T46	0	695	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1468267424	0	0
T1	900540	575873	0	0
T2	1464980	1045089	0	0
T3	17224	13091	0	0
T4	2675816	1333655	0	0
T5	1219792	379568	0	0
T6	3626256	924807	0	0
T9	984600	67370	0	0
T16	103868	78497	0	0
T17	232208	151441	0	0
T18	140952	86380	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T118,T201,T202
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	681991999	6660	0	0
DisabledNoTrigBkwd_A	681991999	231955	0	0
DisabledNoTrigFwd_A	681991999	373815120	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	6660	0	0
T21	17666	0	0	0
T22	73733	0	0	0
T23	41590	0	0	0
T29	68414	0	0	0
T45	34009	0	0	0
T71	22050	0	0	0
T81	2871	0	0	0
T82	11210	0	0	0
T83	4484	0	0	0
T118	3438	602	0	0
T201	0	1052	0	0
T202	0	1159	0	0
T203	0	408	0	0
T204	0	668	0	0
T207	0	632	0	0
T210	0	813	0	0
T212	0	609	0	0
T213	0	717	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	231955	0	0
T1	225135	736	0	0
T2	366245	4	0	0
T3	4306	0	0	0
T4	668954	1539	0	0
T5	304948	0	0	0
T6	906564	898	0	0
T9	246150	1117	0	0
T10	0	10	0	0
T15	0	2081	0	0
T16	25967	45	0	0
T17	58052	1	0	0
T18	35238	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	373815120	0	0
T1	225135	104793	0	0
T2	366245	334247	0	0
T3	4306	3238	0	0
T4	668954	1813	0	0
T5	304948	203061	0	0
T6	906564	4853	0	0
T9	246150	27396	0	0
T16	25967	815	0	0
T17	58052	32858	0	0
T18	35238	4722	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T205,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	681991999	2169	0	0
DisabledNoTrigBkwd_A	681991999	233154	0	0
DisabledNoTrigFwd_A	681991999	373075466	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	2169	0	0
T3	4306	761	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T10	722228	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	52438	0	0	0
T205	0	682	0	0
T211	0	726	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	233154	0	0
T1	225135	28	0	0
T2	366245	0	0	0
T3	4306	5	0	0
T4	668954	6	0	0
T5	304948	0	0	0
T6	906564	928	0	0
T9	246150	11269	0	0
T15	0	7	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T22	0	11	0	0
T28	0	13	0	0
T43	0	44	0	0
T45	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	373075466	0	0
T1	225135	214291	0	0
T2	366245	343137	0	0
T3	4306	3261	0	0
T4	668954	662332	0	0
T5	304948	175291	0	0
T6	906564	10758	0	0
T9	246150	6260	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T83,T199,T200
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	681991999	3835	0	0
DisabledNoTrigBkwd_A	681991999	253052	0	0
DisabledNoTrigFwd_A	681991999	343162511	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	3835	0	0
T7	848852	0	0	0
T8	186267	0	0	0
T29	68414	0	0	0
T46	974295	0	0	0
T71	22050	0	0	0
T72	81318	0	0	0
T83	4484	976	0	0
T94	527462	0	0	0
T95	118997	0	0	0
T96	34293	0	0	0
T199	0	1090	0	0
T200	0	1320	0	0
T208	0	449	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	253052	0	0
T1	225135	240	0	0
T2	366245	212	0	0
T3	4306	0	0	0
T4	668954	8887	0	0
T5	304948	0	0	0
T6	906564	3	0	0
T9	246150	1284	0	0
T15	0	2350	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	3	0	0
T28	0	3	0	0
T43	0	25	0	0
T44	0	172	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	343162511	0	0
T1	225135	153713	0	0
T2	366245	15075	0	0
T3	4306	3285	0	0
T4	668954	639	0	0
T5	304948	606	0	0
T6	906564	902421	0	0
T9	246150	6275	0	0
T16	25967	25894	0	0
T17	58052	2659	0	0
T18	35238	34046	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T206,T209
1	1	Covered	T1,T2,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	681991999	2900	0	0
DisabledNoTrigBkwd_A	681991999	187670	0	0
DisabledNoTrigFwd_A	681991999	378214327	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	2900	0	0
T26	159123	0	0	0
T30	490200	0	0	0
T31	35916	0	0	0
T62	110154	0	0	0
T63	48606	0	0	0
T64	11739	0	0	0
T65	102659	0	0	0
T198	1546	707	0	0
T199	3450	0	0	0
T206	0	306	0	0
T209	0	1014	0	0
T214	0	873	0	0
T215	107676	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	187670	0	0
T1	225135	349	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1724	0	0
T8	0	2111	0	0
T9	246150	1108	0	0
T15	0	99	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	12	0	0
T23	0	2	0	0
T29	0	4	0	0
T43	0	15	0	0
T46	0	695	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	378214327	0	0
T1	225135	103076	0	0
T2	366245	352630	0	0
T3	4306	3307	0	0
T4	668954	668871	0	0
T5	304948	610	0	0
T6	906564	6775	0	0
T9	246150	27439	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	12460	0	0