Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T5,T9,T6 Yes T5,T9,T6 INPUT
ping_ok_o Yes Yes T9,T6,T15 Yes T9,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T9,T6 Yes T1,T9,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T9,T6 Yes T5,T9,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T6,T15,T8 Yes T6,T15,T8 OUTPUT
integ_fail_o Yes Yes T1,T70,T72 Yes T1,T70,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T6,T15,T8 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T8 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T10,T15 Yes T9,T10,T15 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T10,T15 Yes T9,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T9,T15,T104 Yes T9,T10,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T47,T104 Yes T15,T47,T104 INPUT
ping_ok_o Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
integ_fail_o Yes Yes T44,T46,T74 Yes T44,T46,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T27 Yes T9,T15,T27 INPUT
ping_ok_o Yes Yes T9,T15,T27 Yes T9,T15,T27 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T27 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T9,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T11,T15,T47 Yes T11,T15,T47 INPUT
ping_ok_o Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
integ_fail_o Yes Yes T9,T70,T46 Yes T9,T70,T46 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T11,T15,T47 Yes T11,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T11,T15,T104 Yes T11,T15,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T4,T9 Yes T1,T4,T9 INPUT
ping_ok_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
integ_fail_o Yes Yes T44,T15,T72 Yes T44,T15,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T9 Yes T1,T15,T47 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T47 Yes T1,T4,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T11,T104 Yes T4,T11,T104 INPUT
ping_ok_o Yes Yes T4,T104,T30 Yes T4,T104,T30 OUTPUT
integ_fail_o Yes Yes T1,T4,T15 Yes T1,T4,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T11,T104 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T4,T11,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T15,T27 Yes T4,T15,T27 INPUT
ping_ok_o Yes Yes T4,T15,T27 Yes T4,T15,T27 OUTPUT
integ_fail_o Yes Yes T70,T72,T27 Yes T70,T72,T27 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T15,T27 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T4,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T9,T6 Yes T4,T9,T6 INPUT
ping_ok_o Yes Yes T4,T9,T6 Yes T4,T9,T6 OUTPUT
integ_fail_o Yes Yes T9,T46,T72 Yes T9,T46,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T9,T6 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T4,T9,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T8 Yes T9,T15,T8 INPUT
ping_ok_o Yes Yes T9,T15,T8 Yes T9,T15,T8 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T8 Yes T15,T8,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T8,T27 Yes T9,T15,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T4,T6 Yes T1,T4,T6 INPUT
ping_ok_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
integ_fail_o Yes Yes T9,T44,T70 Yes T9,T44,T70 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T6 Yes T1,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T104 Yes T1,T4,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T104,T215 Yes T9,T104,T215 INPUT
ping_ok_o Yes Yes T9,T104,T30 Yes T9,T104,T30 OUTPUT
integ_fail_o Yes Yes T44,T15,T48 Yes T44,T15,T48 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T104,T215 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T9,T104,T215 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T47,T104 Yes T15,T47,T104 INPUT
ping_ok_o Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
integ_fail_o Yes Yes T70,T15,T46 Yes T70,T15,T46 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T47,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T15,T47,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T8 Yes T9,T15,T8 INPUT
ping_ok_o Yes Yes T9,T15,T8 Yes T9,T15,T8 OUTPUT
integ_fail_o Yes Yes T4,T44,T74 Yes T4,T44,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T8 Yes T15,T104,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T116 Yes T9,T15,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T103 Yes T9,T15,T103 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T9,T70,T15 Yes T9,T70,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T103 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T15,T103 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T104 Yes T9,T15,T104 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T15,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T27,T104 Yes T15,T27,T104 INPUT
ping_ok_o Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
integ_fail_o Yes Yes T4,T9,T15 Yes T4,T9,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T10,T103 Yes T1,T10,T103 INPUT
ping_ok_o Yes Yes T1,T104,T30 Yes T1,T104,T30 OUTPUT
integ_fail_o Yes Yes T1,T4,T15 Yes T1,T4,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T10,T103 Yes T1,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T104,T30 Yes T1,T10,T103 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T10,T15 Yes T9,T10,T15 INPUT
ping_ok_o Yes Yes T9,T15,T47 Yes T9,T15,T47 OUTPUT
integ_fail_o Yes Yes T1,T46,T72 Yes T1,T46,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T10,T15 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T10,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T27,T104 Yes T1,T27,T104 INPUT
ping_ok_o Yes Yes T1,T27,T104 Yes T1,T27,T104 OUTPUT
integ_fail_o Yes Yes T4,T74,T30 Yes T4,T74,T30 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T27,T104 Yes T1,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T27,T104 Yes T1,T27,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T103,T47 Yes T15,T103,T47 INPUT
ping_ok_o Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
integ_fail_o Yes Yes T4,T74,T27 Yes T4,T74,T27 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T103,T47 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T15,T103,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T5,T9,T104 Yes T5,T9,T104 INPUT
ping_ok_o Yes Yes T9,T104,T30 Yes T9,T104,T30 OUTPUT
integ_fail_o Yes Yes T1,T4,T72 Yes T1,T4,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T9,T104 Yes T104,T30,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T216 Yes T5,T9,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T5,T9 Yes T4,T5,T9 INPUT
ping_ok_o Yes Yes T4,T9,T15 Yes T4,T9,T15 OUTPUT
integ_fail_o Yes Yes T1,T44,T15 Yes T1,T44,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T9 Yes T9,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T9,T15,T104 Yes T4,T5,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T11,T15 Yes T4,T11,T15 INPUT
ping_ok_o Yes Yes T4,T15,T104 Yes T4,T15,T104 OUTPUT
integ_fail_o Yes Yes T46,T72,T47 Yes T46,T72,T47 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T11,T15 Yes T15,T104,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T216 Yes T4,T11,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T103 Yes T9,T15,T103 INPUT
ping_ok_o Yes Yes T9,T15,T47 Yes T9,T15,T47 OUTPUT
integ_fail_o Yes Yes T1,T44,T15 Yes T1,T44,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T103 Yes T15,T104,T215 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T215 Yes T9,T15,T103 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T7 Yes T9,T15,T7 INPUT
ping_ok_o Yes Yes T9,T15,T7 Yes T9,T15,T7 OUTPUT
integ_fail_o Yes Yes T1,T4,T15 Yes T1,T4,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T27 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T9,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T27,T104 Yes T15,T27,T104 INPUT
ping_ok_o Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
integ_fail_o Yes Yes T27,T26,T116 Yes T27,T26,T116 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T15,T27,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T11,T15 Yes T9,T11,T15 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T15,T74,T27 Yes T15,T74,T27 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T11,T15 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T11,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T9,T11 Yes T1,T9,T11 INPUT
ping_ok_o Yes Yes T1,T9,T8 Yes T1,T9,T8 OUTPUT
integ_fail_o Yes Yes T4,T44,T15 Yes T4,T44,T15 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T9,T11 Yes T1,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T27,T104 Yes T1,T9,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T47,T104,T30 Yes T47,T104,T30 INPUT
ping_ok_o Yes Yes T47,T104,T30 Yes T47,T104,T30 OUTPUT
integ_fail_o Yes Yes T44,T46,T72 Yes T44,T46,T72 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T47,T104,T30 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T47,T104,T30 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T10,T103,T47 Yes T10,T103,T47 INPUT
ping_ok_o Yes Yes T47,T104,T116 Yes T47,T104,T116 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T103,T47 Yes T104,T116,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T116,T216 Yes T10,T103,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T10,T11,T15 Yes T10,T11,T15 INPUT
ping_ok_o Yes Yes T15,T27,T47 Yes T15,T27,T47 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T11,T15 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T10,T11,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T10,T15,T7 Yes T10,T15,T7 INPUT
ping_ok_o Yes Yes T15,T7,T47 Yes T15,T7,T47 OUTPUT
integ_fail_o Yes Yes T46,T74,T116 Yes T46,T74,T116 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T15,T103 Yes T15,T104,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T116 Yes T10,T15,T103 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T9,T11 Yes T1,T9,T11 INPUT
ping_ok_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
integ_fail_o Yes Yes T4,T44,T46 Yes T4,T44,T46 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T9,T11 Yes T1,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T104 Yes T1,T9,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T8,T27 Yes T15,T8,T27 INPUT
ping_ok_o Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
integ_fail_o Yes Yes T4,T9,T44 Yes T4,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T8,T27 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T15,T8,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T11,T15,T121 Yes T11,T15,T121 INPUT
ping_ok_o Yes Yes T15,T121,T27 Yes T15,T121,T27 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T11,T15,T99 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T11,T15,T99 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T8,T27 Yes T15,T8,T27 INPUT
ping_ok_o Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
integ_fail_o Yes Yes T44,T15,T72 Yes T44,T15,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T9,T10 Yes T4,T9,T10 INPUT
ping_ok_o Yes Yes T4,T9,T104 Yes T4,T9,T104 OUTPUT
integ_fail_o Yes Yes T1,T4,T46 Yes T1,T4,T46 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T9,T10 Yes T104,T30,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T216 Yes T4,T9,T10 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T104 Yes T9,T15,T104 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T1,T4,T44 Yes T1,T4,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T15,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T47,T104 Yes T9,T47,T104 INPUT
ping_ok_o Yes Yes T9,T47,T104 Yes T9,T47,T104 OUTPUT
integ_fail_o Yes Yes T1,T4,T44 Yes T1,T4,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T47,T104 Yes T104,T30,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T216 Yes T9,T47,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T5,T9 Yes T1,T5,T9 INPUT
ping_ok_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
integ_fail_o Yes Yes T1,T4,T44 Yes T1,T4,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T9 Yes T1,T15,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T104 Yes T1,T5,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T9,T6 Yes T4,T9,T6 INPUT
ping_ok_o Yes Yes T4,T9,T6 Yes T4,T9,T6 OUTPUT
integ_fail_o Yes Yes T1,T4,T44 Yes T1,T4,T44 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T9,T6 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T4,T9,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T103,T104 Yes T15,T103,T104 INPUT
ping_ok_o Yes Yes T15,T104,T62 Yes T15,T104,T62 OUTPUT
integ_fail_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T103,T104 Yes T15,T104,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T216 Yes T15,T103,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T47,T104 Yes T15,T47,T104 INPUT
ping_ok_o Yes Yes T15,T47,T104 Yes T15,T47,T104 OUTPUT
integ_fail_o Yes Yes T44,T15,T47 Yes T44,T15,T47 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T47,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T15,T47,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T11,T99 Yes T9,T11,T99 INPUT
ping_ok_o Yes Yes T9,T104,T30 Yes T9,T104,T30 OUTPUT
integ_fail_o Yes Yes T46,T48,T76 Yes T46,T48,T76 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T11,T99 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T9,T11,T99 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T8,T27 Yes T15,T8,T27 INPUT
ping_ok_o Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
integ_fail_o Yes Yes T4,T70,T72 Yes T4,T70,T72 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T8,T27 Yes T15,T8,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T15,T8 Yes T1,T15,T8 INPUT
ping_ok_o Yes Yes T1,T15,T8 Yes T1,T15,T8 OUTPUT
integ_fail_o Yes Yes T9,T44,T74 Yes T9,T44,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T15,T8 Yes T1,T15,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T27 Yes T1,T15,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T27 Yes T9,T15,T27 INPUT
ping_ok_o Yes Yes T9,T15,T27 Yes T9,T15,T27 OUTPUT
integ_fail_o Yes Yes T4,T15,T74 Yes T4,T15,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T27 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T9,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T99,T103,T47 Yes T99,T103,T47 INPUT
ping_ok_o Yes Yes T47,T104,T116 Yes T47,T104,T116 OUTPUT
integ_fail_o Yes Yes T4,T9,T44 Yes T4,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T99,T103,T47 Yes T47,T104,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T47,T104,T116 Yes T99,T103,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T104,T30,T62 Yes T104,T30,T62 INPUT
ping_ok_o Yes Yes T104,T30,T62 Yes T104,T30,T62 OUTPUT
integ_fail_o Yes Yes T4,T9,T44 Yes T4,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T104,T30,T67 Yes T104,T30,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T216 Yes T104,T30,T67 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T6,T15 Yes T9,T6,T15 INPUT
ping_ok_o Yes Yes T9,T6,T15 Yes T9,T6,T15 OUTPUT
integ_fail_o Yes Yes T15,T46,T74 Yes T15,T46,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T6,T15 Yes T15,T27,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T104 Yes T9,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T5,T10,T104 Yes T5,T10,T104 INPUT
ping_ok_o Yes Yes T104,T116,T216 Yes T104,T116,T216 OUTPUT
integ_fail_o Yes Yes T1,T4,T44 Yes T1,T4,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T10,T104 Yes T104,T116,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T116,T216 Yes T5,T10,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T104,T215 Yes T9,T104,T215 INPUT
ping_ok_o Yes Yes T9,T104,T216 Yes T9,T104,T216 OUTPUT
integ_fail_o Yes Yes T4,T9,T44 Yes T4,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T104,T215 Yes T104,T216,T217 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T216,T217 Yes T9,T104,T215 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T11,T15 Yes T4,T11,T15 INPUT
ping_ok_o Yes Yes T4,T15,T8 Yes T4,T15,T8 OUTPUT
integ_fail_o Yes Yes T1,T46,T30 Yes T1,T46,T30 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T11,T15 Yes T15,T104,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T216 Yes T4,T11,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T15,T103,T104 Yes T15,T103,T104 INPUT
ping_ok_o Yes Yes T15,T104,T30 Yes T15,T104,T30 OUTPUT
integ_fail_o Yes Yes T4,T72,T74 Yes T4,T72,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T103,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T15,T103,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T10,T11,T104 Yes T10,T11,T104 INPUT
ping_ok_o Yes Yes T104,T30,T67 Yes T104,T30,T67 OUTPUT
integ_fail_o Yes Yes T4,T15,T46 Yes T4,T15,T46 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T11,T104 Yes T104,T30,T216 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T216 Yes T10,T11,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T11,T104 Yes T9,T11,T104 INPUT
ping_ok_o Yes Yes T9,T104,T30 Yes T9,T104,T30 OUTPUT
integ_fail_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T11,T104 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T9,T11,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T4,T8,T104 Yes T4,T8,T104 INPUT
ping_ok_o Yes Yes T4,T8,T104 Yes T4,T8,T104 OUTPUT
integ_fail_o Yes Yes T1,T9,T44 Yes T1,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T8,T104 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T4,T8,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T1,T9,T15 Yes T1,T9,T15 INPUT
ping_ok_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
integ_fail_o Yes Yes T15,T72,T74 Yes T15,T72,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T9,T15 Yes T1,T15,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T15,T27 Yes T1,T9,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T10,T11 Yes T9,T10,T11 INPUT
ping_ok_o Yes Yes T9,T104,T116 Yes T9,T104,T116 OUTPUT
integ_fail_o Yes Yes T1,T9,T44 Yes T1,T9,T44 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T10,T11 Yes T9,T104,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T9,T104,T116 Yes T9,T10,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T104,T216 Yes T9,T104,T216 INPUT
ping_ok_o Yes Yes T9,T104,T216 Yes T9,T104,T216 OUTPUT
integ_fail_o Yes Yes T9,T44,T46 Yes T9,T44,T46 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T104,T216 Yes T104,T216,T217 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T216,T217 Yes T9,T104,T216 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T11,T7,T103 Yes T11,T7,T103 INPUT
ping_ok_o Yes Yes T7,T47,T104 Yes T7,T47,T104 OUTPUT
integ_fail_o Yes Yes T9,T44,T46 Yes T9,T44,T46 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T11,T103,T47 Yes T104,T30,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T30,T116 Yes T11,T103,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T7,T8 Yes T9,T7,T8 INPUT
ping_ok_o Yes Yes T9,T7,T8 Yes T9,T7,T8 OUTPUT
integ_fail_o Yes Yes T44,T15,T47 Yes T44,T15,T47 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T8,T104 Yes T9,T8,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T9,T8,T104 Yes T9,T8,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T121,T104,T216 Yes T121,T104,T216 INPUT
ping_ok_o Yes Yes T121,T104,T216 Yes T121,T104,T216 OUTPUT
integ_fail_o Yes Yes T74,T47,T26 Yes T74,T47,T26 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T104,T216,T217 Yes T104,T216,T217 OUTPUT
alert_rx_o.ping_p Yes Yes T104,T216,T217 Yes T104,T216,T217 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T44,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T44,T15 Yes T1,T3,T4 INPUT
ping_req_i Yes Yes T9,T15,T104 Yes T9,T15,T104 INPUT
ping_ok_o Yes Yes T9,T15,T104 Yes T9,T15,T104 OUTPUT
integ_fail_o Yes Yes T4,T44,T74 Yes T4,T44,T74 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T9,T15,T104 Yes T15,T104,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T104,T30 Yes T9,T15,T104 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

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