Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T9
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T9,T18
1	1	1	Covered	T1,T9,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T16
0	1	Covered	T1,T20,T21
1	0	Covered	T1,T16,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T16
1	0	Covered	T23,T24,T25
1	1	Covered	T1,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T9,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T9,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T15,T26
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T16,T27,T26
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T28,T29,T30
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T9,T28
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T9,T16
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T20,T28
TimeoutSt->Phase0St	172	Covered	T1,T16,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T15,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T27,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T9,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	982	0	0
CheckAccumTrig0_A	2147483647	2389	0	0
CheckAccumTrig1_A	2147483647	124	0	0
CheckClr_A	2147483647	1143	0	0
CheckEn_A	2147483647	1124807411	0	0
CheckPhase0_A	2147483647	2733	0	0
CheckPhase1_A	2147483647	2687	0	0
CheckPhase2_A	2147483647	2641	0	0
CheckPhase3_A	2147483647	2579	0	0
CheckTimeout0_A	2147483647	8945	0	0
CheckTimeoutSt1_A	2147483647	804953	0	0
CheckTimeoutSt2_A	2147483647	8541	0	0
CheckTimeoutStTrig_A	2147483647	269	0	0
ErrorStAllEscAsserted_A	2147483647	5202	0	0
ErrorStIsTerminal_A	2147483647	4362	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	982	0	0
T12	68216	192	0	0
T13	0	238	0	0
T14	0	144	0	0
T32	0	152	0	0
T33	0	256	0	0
T34	2298552	0	0	0
T35	837508	0	0	0
T36	1184388	0	0	0
T37	510456	0	0	0
T38	42980	0	0	0
T39	85520	0	0	0
T40	1007388	0	0	0
T41	142876	0	0	0
T42	1450832	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T1	900540	9	0	0
T2	1464980	2	0	0
T3	17224	1	0	0
T4	2675816	3	0	0
T5	1219792	0	0	0
T6	3626256	6	0	0
T8	0	1	0	0
T9	984600	7	0	0
T10	0	1	0	0
T15	0	19	0	0
T16	103868	3	0	0
T17	232208	1	0	0
T18	140952	7	0	0
T23	0	3	0	0
T28	0	3	0	0
T29	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	124	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	6	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T29	68414	1	0	0
T30	490200	1	0	0
T31	35916	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	4	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	110154	0	0	0
T63	48606	0	0	0
T64	11739	0	0	0
T65	102659	0	0	0
T66	23993	0	0	0
T67	694425	0	0	0
T68	17588	0	0	0
T69	15201	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1143	0	0
T1	675405	3	0	0
T2	1098735	0	0	0
T3	12918	0	0	0
T4	2006862	0	0	0
T5	914844	0	0	0
T6	3626256	3	0	0
T8	0	2	0	0
T9	984600	3	0	0
T10	722228	0	0	0
T11	108131	0	0	0
T15	0	12	0	0
T16	103868	9	0	0
T17	232208	0	0	0
T18	140952	5	0	0
T20	52438	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	0	16	0	0
T28	13448	2	0	0
T29	0	3	0	0
T30	0	6	0	0
T43	193343	0	0	0
T46	0	2	0	0
T47	0	5	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	15	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1124807411	0	0
T1	900540	977359	0	0
T2	1464980	719858	0	0
T3	17224	13091	0	0
T4	2675816	673139	0	0
T5	1219792	379566	0	0
T6	3626256	924806	0	0
T9	984600	67370	0	0
T16	103868	78494	0	0
T17	232208	125752	0	0
T18	140952	50757	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2733	0	0
T1	900540	11	0	0
T2	1464980	2	0	0
T3	17224	1	0	0
T4	2675816	3	0	0
T5	1219792	0	0	0
T6	3626256	5	0	0
T9	984600	7	0	0
T10	0	1	0	0
T15	0	16	0	0
T16	103868	9	0	0
T17	232208	1	0	0
T18	140952	8	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T28	0	3	0	0
T29	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2687	0	0
T1	900540	11	0	0
T2	1464980	2	0	0
T3	17224	1	0	0
T4	2675816	3	0	0
T5	1219792	0	0	0
T6	3626256	4	0	0
T9	984600	7	0	0
T10	0	1	0	0
T15	0	15	0	0
T16	103868	8	0	0
T17	232208	1	0	0
T18	140952	8	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T28	0	3	0	0
T29	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T1	900540	11	0	0
T2	1464980	2	0	0
T3	17224	1	0	0
T4	2675816	3	0	0
T5	1219792	0	0	0
T6	3626256	4	0	0
T9	984600	7	0	0
T10	0	1	0	0
T15	0	15	0	0
T16	103868	8	0	0
T17	232208	1	0	0
T18	140952	8	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T28	0	2	0	0
T29	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T1	900540	10	0	0
T2	1464980	2	0	0
T3	17224	1	0	0
T4	2675816	3	0	0
T5	1219792	0	0	0
T6	3626256	4	0	0
T9	984600	6	0	0
T10	0	1	0	0
T15	0	15	0	0
T16	103868	8	0	0
T17	232208	1	0	0
T18	140952	8	0	0
T20	0	2	0	0
T22	0	3	0	0
T23	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8945	0	0
T1	900540	13	0	0
T2	1464980	0	0	0
T3	17224	0	0	0
T4	2675816	0	0	0
T5	1219792	0	0	0
T6	3626256	0	0	0
T9	984600	2	0	0
T15	0	4	0	0
T16	103868	6	0	0
T17	232208	0	0	0
T18	140952	0	0	0
T20	0	11	0	0
T21	0	14	0	0
T22	0	2	0	0
T23	0	3	0	0
T26	0	3	0	0
T27	0	16	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	0	8	0	0
T31	0	6	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T67	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T74	0	42	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	804953	0	0
T1	900540	2187	0	0
T2	1464980	0	0	0
T3	17224	0	0	0
T4	2675816	0	0	0
T5	1219792	0	0	0
T6	3626256	0	0	0
T9	984600	132	0	0
T15	0	416	0	0
T16	103868	13	0	0
T17	232208	0	0	0
T18	140952	0	0	0
T20	0	1409	0	0
T21	0	1009	0	0
T22	0	38	0	0
T23	0	274	0	0
T26	0	238	0	0
T27	0	3752	0	0
T28	0	27	0	0
T29	0	116	0	0
T30	0	1838	0	0
T31	0	2010	0	0
T46	0	49	0	0
T47	0	2	0	0
T48	0	146	0	0
T67	0	51	0	0
T69	0	104	0	0
T71	0	127	0	0
T74	0	8717	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8541	0	0
T1	900540	7	0	0
T2	1464980	0	0	0
T3	17224	0	0	0
T4	2675816	0	0	0
T5	1219792	0	0	0
T6	3626256	0	0	0
T9	984600	0	0	0
T15	0	3	0	0
T16	103868	0	0	0
T17	232208	0	0	0
T18	140952	0	0	0
T20	0	9	0	0
T21	0	12	0	0
T23	0	1	0	0
T26	0	3	0	0
T27	0	4	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T35	0	2	0	0
T41	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	0	32	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	269	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T21	17666	1	0	0
T22	73733	1	0	0
T23	41590	1	0	0
T24	0	2	0	0
T26	0	1	0	0
T27	0	3	0	0
T29	68414	0	0	0
T30	0	6	0	0
T31	0	4	0	0
T41	0	1	0	0
T45	34009	0	0	0
T46	974295	0	0	0
T48	0	2	0	0
T52	0	3	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	22050	0	0	0
T74	650204	7	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	2871	0	0	0
T82	11210	0	0	0
T83	4484	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5202	0	0
T12	68216	744	0	0
T13	0	1482	0	0
T14	0	730	0	0
T32	0	757	0	0
T33	0	1489	0	0
T34	2298552	0	0	0
T35	837508	0	0	0
T36	1184388	0	0	0
T37	510456	0	0	0
T38	42980	0	0	0
T39	85520	0	0	0
T40	1007388	0	0	0
T41	142876	0	0	0
T42	1450832	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4362	0	0
T12	68216	624	0	0
T13	0	1242	0	0
T14	0	610	0	0
T32	0	637	0	0
T33	0	1249	0	0
T34	2298552	0	0	0
T35	837508	0	0	0
T36	1184388	0	0	0
T37	510456	0	0	0
T38	42980	0	0	0
T39	85520	0	0	0
T40	1007388	0	0	0
T41	142876	0	0	0
T42	1450832	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	900540	900508	0	0
T2	1464980	1464748	0	0
T3	17224	16868	0	0
T4	2675816	2675484	0	0
T5	1219792	1219488	0	0
T6	3626256	3625952	0	0
T9	984600	984576	0	0
T16	103868	103576	0	0
T17	232208	231848	0	0
T18	140952	140608	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	900540	900508	0	0
T2	1464980	1464748	0	0
T3	17224	16868	0	0
T4	2675816	2675484	0	0
T5	1219792	1219488	0	0
T6	3626256	3625952	0	0
T9	984600	984576	0	0
T16	103868	103576	0	0
T17	232208	231848	0	0
T18	140952	140608	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T28
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T20,T28
1	1	1	Covered	T1,T28,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T29
0	1	Covered	T74,T27,T30
1	0	Covered	T29,T47,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T28,T29
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T47,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T29
1	0	Not Covered
1	1	Covered	T74,T27,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T43,T28

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T2,T6,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T44,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T9,T6
1	Covered	T1,T4,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T28,T29

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T28,T29
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T26,T31
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T54,T84,T85
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T52,T19
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T27,T86
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T9,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T28,T74
TimeoutSt->Phase0St	172	Covered	T29,T74,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T28,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T74,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T28,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T28,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T31,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T54,T84,T85
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T52,T19
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T27,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T6,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	681991999	272	0	0
CheckAccumTrig0_A	681991999	494	0	0
CheckAccumTrig1_A	681991999	24	0	0
CheckClr_A	681991999	236	0	0
CheckEn_A	681625816	276618677	0	0
CheckPhase0_A	681991999	577	0	0
CheckPhase1_A	681991999	561	0	0
CheckPhase2_A	681991999	554	0	0
CheckPhase3_A	681991999	538	0	0
CheckTimeout0_A	681991999	2073	0	0
CheckTimeoutSt1_A	681991999	172444	0	0
CheckTimeoutSt2_A	681991999	1978	0	0
CheckTimeoutStTrig_A	681991999	70	0	0
ErrorStAllEscAsserted_A	681991999	1326	0	0
ErrorStIsTerminal_A	681991999	1116	0	0
EscStateOut_A	681624179	681555560	0	0
u_state_regs_A	681991999	681833798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	272	0	0
T12	17054	59	0	0
T13	0	56	0	0
T14	0	30	0	0
T32	0	47	0	0
T33	0	80	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	494	0	0
T1	225135	1	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	5	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	1	0	0
T28	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	24	0	0
T7	848852	0	0	0
T8	186267	0	0	0
T29	68414	1	0	0
T46	974295	0	0	0
T47	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T72	81318	0	0	0
T73	155781	0	0	0
T75	33969	0	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	527462	0	0	0
T95	118997	0	0	0
T96	34293	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	236	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	722228	0	0	0
T11	108131	0	0	0
T15	0	3	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	52438	0	0	0
T22	0	2	0	0
T27	0	7	0	0
T28	13448	1	0	0
T29	0	3	0	0
T43	193343	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681625816	276618677	0	0
T1	225135	153713	0	0
T2	366245	15075	0	0
T3	4306	3285	0	0
T4	668954	639	0	0
T5	304948	606	0	0
T6	906564	902420	0	0
T9	246150	6275	0	0
T16	25967	25893	0	0
T17	58052	2659	0	0
T18	35238	1577	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	577	0	0
T1	225135	1	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	4	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	1	0	0
T28	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	561	0	0
T1	225135	1	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	4	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	1	0	0
T28	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	554	0	0
T1	225135	1	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	4	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	1	0	0
T28	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	538	0	0
T1	225135	1	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	4	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	1	0	0
T22	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	2073	0	0
T1	225135	2	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T27	0	4	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	6	0	0
T47	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T74	0	26	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	172444	0	0
T1	225135	326	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T27	0	589	0	0
T28	0	27	0	0
T29	0	2	0	0
T30	0	1067	0	0
T31	0	2010	0	0
T47	0	2	0	0
T67	0	51	0	0
T69	0	104	0	0
T74	0	4703	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1978	0	0
T1	225135	2	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T31	0	2	0	0
T35	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T74	0	24	0	0
T78	0	9	0	0
T86	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	70	0	0
T24	0	1	0	0
T27	173756	2	0	0
T30	0	2	0	0
T31	0	4	0	0
T47	166778	0	0	0
T48	0	1	0	0
T52	0	3	0	0
T54	0	2	0	0
T74	650204	2	0	0
T79	0	1	0	0
T97	0	1	0	0
T98	75153	0	0	0
T99	526534	0	0	0
T100	75672	0	0	0
T101	16914	0	0	0
T102	83669	0	0	0
T103	122723	0	0	0
T104	35875	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1326	0	0
T12	17054	187	0	0
T13	0	363	0	0
T14	0	183	0	0
T32	0	200	0	0
T33	0	393	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1116	0	0
T12	17054	157	0	0
T13	0	303	0	0
T14	0	153	0	0
T32	0	170	0	0
T33	0	333	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681624179	681555560	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	681833798	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T9
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T9,T28
1	1	1	Covered	T1,T16,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T20
0	1	Covered	T21,T23,T74
1	0	Covered	T1,T16,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T20
1	0	Covered	T23
1	1	Covered	T21,T23,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T6,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T16,T10,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T16,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T16
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T9,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T16,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T16,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T26,T105
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T16,T26,T106
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T87,T107
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T108,T53,T54
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T16,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T20,T15
TimeoutSt->Phase0St	172	Covered	T1,T16,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T105,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T26,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T87,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T108,T53,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	681991999	225	0	0
CheckAccumTrig0_A	681991999	869	0	0
CheckAccumTrig1_A	681991999	53	0	0
CheckClr_A	681991999	439	0	0
CheckEn_A	681625816	279437149	0	0
CheckPhase0_A	681991999	973	0	0
CheckPhase1_A	681991999	956	0	0
CheckPhase2_A	681991999	937	0	0
CheckPhase3_A	681991999	917	0	0
CheckTimeout0_A	681991999	3271	0	0
CheckTimeoutSt1_A	681991999	288108	0	0
CheckTimeoutSt2_A	681991999	3140	0	0
CheckTimeoutStTrig_A	681991999	75	0	0
ErrorStAllEscAsserted_A	681991999	1223	0	0
ErrorStIsTerminal_A	681991999	1013	0	0
EscStateOut_A	681624179	681555560	0	0
u_state_regs_A	681991999	681833798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	225	0	0
T12	17054	50	0	0
T13	0	50	0	0
T14	0	26	0	0
T32	0	47	0	0
T33	0	52	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	869	0	0
T1	225135	3	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	0	1	0	0
T15	0	9	0	0
T16	25967	3	0	0
T17	58052	1	0	0
T18	35238	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	53	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	6	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T22	0	1	0	0
T49	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	439	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T8	0	2	0	0
T9	246150	0	0	0
T15	0	6	0	0
T16	25967	9	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T21	0	1	0	0
T27	0	1	0	0
T46	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	0	11	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681625816	279437149	0	0
T1	225135	103161	0	0
T2	366245	9018	0	0
T3	4306	3238	0	0
T4	668954	1813	0	0
T5	304948	203060	0	0
T6	906564	4853	0	0
T9	246150	27396	0	0
T16	25967	815	0	0
T17	58052	7171	0	0
T18	35238	1569	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	973	0	0
T1	225135	4	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	0	1	0	0
T15	0	8	0	0
T16	25967	9	0	0
T17	58052	1	0	0
T18	35238	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	956	0	0
T1	225135	4	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	0	1	0	0
T15	0	8	0	0
T16	25967	8	0	0
T17	58052	1	0	0
T18	35238	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	937	0	0
T1	225135	4	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	0	1	0	0
T15	0	8	0	0
T16	25967	8	0	0
T17	58052	1	0	0
T18	35238	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	917	0	0
T1	225135	4	0	0
T2	366245	1	0	0
T3	4306	0	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T10	0	1	0	0
T15	0	8	0	0
T16	25967	8	0	0
T17	58052	1	0	0
T18	35238	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	3271	0	0
T1	225135	4	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	2	0	0
T16	25967	6	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	9	0	0
T21	0	7	0	0
T22	0	1	0	0
T23	0	2	0	0
T29	0	1	0	0
T46	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	288108	0	0
T1	225135	580	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	117	0	0
T16	25967	13	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	1231	0	0
T21	0	488	0	0
T22	0	3	0	0
T23	0	122	0	0
T29	0	114	0	0
T46	0	49	0	0
T71	0	127	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	3140	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	9	0	0
T21	0	6	0	0
T23	0	1	0	0
T29	0	1	0	0
T46	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	75	0	0
T21	17666	1	0	0
T22	73733	0	0	0
T23	41590	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	68414	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T45	34009	0	0	0
T46	974295	0	0	0
T48	0	1	0	0
T64	0	1	0	0
T71	22050	0	0	0
T74	0	2	0	0
T77	0	1	0	0
T81	2871	0	0	0
T82	11210	0	0	0
T83	4484	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1223	0	0
T12	17054	166	0	0
T13	0	349	0	0
T14	0	179	0	0
T32	0	176	0	0
T33	0	353	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1013	0	0
T12	17054	136	0	0
T13	0	289	0	0
T14	0	149	0	0
T32	0	146	0	0
T33	0	293	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681624179	681555560	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	681833798	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T9,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T18
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T9,T18
1	1	1	Covered	T1,T9,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T18
0	1	Covered	T70,T74,T27
1	0	Covered	T18,T102,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T9,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T102,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T18
1	0	Covered	T24
1	1	Covered	T70,T74,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T18
1	Covered	T9,T6,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T6
1	Covered	T18,T27,T86

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T6
1	Covered	T43,T70,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T6,T18
1	Covered	T1,T18,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T18,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T18,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T6,T18,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T9,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T9,T6
Phase1St	198	Covered	T1,T9,T6
Phase2St	215	Covered	T1,T9,T6
Phase3St	233	Covered	T1,T9,T6
TerminalSt	249	Covered	T1,T9,T6
TimeoutSt	159	Covered	T1,T9,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T9,T6
IdleSt->TimeoutSt	159	Covered	T1,T9,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T110,T111,T112
Phase0St->Phase1St	198	Covered	T1,T9,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T15,T113
Phase1St->Phase2St	215	Covered	T1,T9,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T51,T84,T114
Phase2St->Phase3St	233	Covered	T1,T9,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T86,T110,T115
Phase3St->TerminalSt	249	Covered	T1,T9,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T18,T70
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T9,T18
TimeoutSt->Phase0St	172	Covered	T18,T70,T74

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T70,T74
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T9,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T9,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T15,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T9,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T9,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T51,T84,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T9,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T9,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T86,T110,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T9,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T9,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T18,T70
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	681991999	268	0	0
CheckAccumTrig0_A	681991999	522	0	0
CheckAccumTrig1_A	681991999	27	0	0
CheckClr_A	681991999	252	0	0
CheckEn_A	681625816	277416951	0	0
CheckPhase0_A	681991999	600	0	0
CheckPhase1_A	681991999	591	0	0
CheckPhase2_A	681991999	581	0	0
CheckPhase3_A	681991999	570	0	0
CheckTimeout0_A	681991999	2024	0	0
CheckTimeoutSt1_A	681991999	162581	0	0
CheckTimeoutSt2_A	681991999	1939	0	0
CheckTimeoutStTrig_A	681991999	55	0	0
ErrorStAllEscAsserted_A	681991999	1304	0	0
ErrorStIsTerminal_A	681991999	1094	0	0
EscStateOut_A	681624179	681555560	0	0
u_state_regs_A	681991999	681833798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	268	0	0
T12	17054	54	0	0
T13	0	58	0	0
T14	0	43	0	0
T32	0	36	0	0
T33	0	77	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	522	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	2	0	0
T8	0	1	0	0
T9	246150	1	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	5	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	27	0	0
T10	722228	0	0	0
T11	108131	0	0	0
T15	490733	0	0	0
T18	35238	1	0	0
T20	52438	0	0	0
T28	13448	0	0	0
T30	0	2	0	0
T43	193343	0	0	0
T44	107058	0	0	0
T70	43747	0	0	0
T84	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T102	0	1	0	0
T110	0	2	0	0
T114	0	2	0	0
T116	0	1	0	0
T117	0	2	0	0
T118	3438	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	252	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	0	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	5	0	0
T23	0	1	0	0
T27	0	5	0	0
T30	0	5	0	0
T64	0	3	0	0
T70	0	3	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681625816	277416951	0	0
T1	225135	103075	0	0
T2	366245	352629	0	0
T3	4306	3307	0	0
T4	668954	668870	0	0
T5	304948	610	0	0
T6	906564	6775	0	0
T9	246150	27439	0	0
T16	25967	25893	0	0
T17	58052	57961	0	0
T18	35238	12460	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	600	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	2	0	0
T9	246150	1	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	6	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	591	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	6	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	581	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	6	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	570	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	1	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	6	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T70	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	2024	0	0
T1	225135	4	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	2	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	3	0	0
T21	0	1	0	0
T23	0	1	0	0
T27	0	9	0	0
T70	0	5	0	0
T74	0	5	0	0
T102	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	162581	0	0
T1	225135	672	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	132	0	0
T15	0	132	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	183	0	0
T21	0	113	0	0
T23	0	152	0	0
T27	0	1938	0	0
T70	0	318	0	0
T74	0	1093	0	0
T102	0	1	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1939	0	0
T1	225135	4	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	2	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	2	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	0	2	0	0
T27	0	7	0	0
T70	0	2	0	0
T74	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	55	0	0
T15	490733	0	0	0
T21	17666	0	0	0
T22	73733	0	0	0
T23	41590	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T30	0	1	0	0
T45	34009	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T70	43747	3	0	0
T74	0	1	0	0
T81	2871	0	0	0
T82	11210	0	0	0
T83	4484	0	0	0
T97	0	1	0	0
T118	3438	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1304	0	0
T12	17054	200	0	0
T13	0	373	0	0
T14	0	159	0	0
T32	0	186	0	0
T33	0	386	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1094	0	0
T12	17054	170	0	0
T13	0	313	0	0
T14	0	129	0	0
T32	0	156	0	0
T33	0	326	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681624179	681555560	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	681833798	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T9
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T1,T9,T44
1	1	1	Covered	T1,T20,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T15
0	1	Covered	T1,T20,T22
1	0	Covered	T30,T48,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T20,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T48,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T15
1	0	Covered	T25
1	1	Covered	T1,T20,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T3,T7,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T4,T20,T43

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T45,T74

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T9,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T1,T20,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T1,T20,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T15,T119
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T61,T120
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T119,T110
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T9,T47
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T9,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T15,T21
TimeoutSt->Phase0St	172	Covered	T1,T20,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T15,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T61,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T119,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T9,T47
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	681991999	217	0	0
CheckAccumTrig0_A	681991999	504	0	0
CheckAccumTrig1_A	681991999	20	0	0
CheckClr_A	681991999	216	0	0
CheckEn_A	681625816	291334634	0	0
CheckPhase0_A	681991999	583	0	0
CheckPhase1_A	681991999	579	0	0
CheckPhase2_A	681991999	569	0	0
CheckPhase3_A	681991999	554	0	0
CheckTimeout0_A	681991999	1577	0	0
CheckTimeoutSt1_A	681991999	181820	0	0
CheckTimeoutSt2_A	681991999	1484	0	0
CheckTimeoutStTrig_A	681991999	69	0	0
ErrorStAllEscAsserted_A	681991999	1349	0	0
ErrorStIsTerminal_A	681991999	1139	0	0
EscStateOut_A	681624179	681555560	0	0
u_state_regs_A	681991999	681833798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	217	0	0
T12	17054	29	0	0
T13	0	74	0	0
T14	0	45	0	0
T32	0	22	0	0
T33	0	47	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	504	0	0
T1	225135	2	0	0
T2	366245	0	0	0
T3	4306	1	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	2	0	0
T9	246150	3	0	0
T15	0	3	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	20	0	0
T19	0	1	0	0
T30	490200	1	0	0
T31	35916	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	110154	0	0	0
T63	48606	0	0	0
T64	11739	0	0	0
T65	102659	0	0	0
T66	23993	0	0	0
T67	694425	0	0	0
T68	17588	0	0	0
T69	15201	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	216	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	1	0	0
T27	0	3	0	0
T28	0	1	0	0
T30	0	1	0	0
T47	0	4	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681625816	291334634	0	0
T1	225135	617410	0	0
T2	366245	343136	0	0
T3	4306	3261	0	0
T4	668954	1817	0	0
T5	304948	175290	0	0
T6	906564	10758	0	0
T9	246150	6260	0	0
T16	25967	25893	0	0
T17	58052	57961	0	0
T18	35238	35151	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	583	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	1	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	3	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	579	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	1	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	3	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	569	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	1	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	3	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T28	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	554	0	0
T1	225135	2	0	0
T2	366245	0	0	0
T3	4306	1	0	0
T4	668954	1	0	0
T5	304948	0	0	0
T6	906564	1	0	0
T9	246150	2	0	0
T15	0	2	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T28	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1577	0	0
T1	225135	3	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	0	3	0	0
T27	0	3	0	0
T30	0	6	0	0
T48	0	3	0	0
T74	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	181820	0	0
T1	225135	609	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	167	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	178	0	0
T21	0	408	0	0
T22	0	35	0	0
T26	0	238	0	0
T27	0	1225	0	0
T30	0	771	0	0
T48	0	146	0	0
T74	0	2921	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1484	0	0
T1	225135	2	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T15	0	1	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T21	0	6	0	0
T26	0	3	0	0
T27	0	2	0	0
T30	0	2	0	0
T35	0	1	0	0
T41	0	3	0	0
T48	0	2	0	0
T74	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	69	0	0
T1	225135	1	0	0
T2	366245	0	0	0
T3	4306	0	0	0
T4	668954	0	0	0
T5	304948	0	0	0
T6	906564	0	0	0
T9	246150	0	0	0
T16	25967	0	0	0
T17	58052	0	0	0
T18	35238	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T27	0	1	0	0
T30	0	3	0	0
T55	0	1	0	0
T74	0	3	0	0
T76	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1349	0	0
T12	17054	191	0	0
T13	0	397	0	0
T14	0	209	0	0
T32	0	195	0	0
T33	0	357	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	1139	0	0
T12	17054	161	0	0
T13	0	337	0	0
T14	0	179	0	0
T32	0	165	0	0
T33	0	297	0	0
T34	574638	0	0	0
T35	209377	0	0	0
T36	296097	0	0	0
T37	127614	0	0	0
T38	10745	0	0	0
T39	21380	0	0	0
T40	251847	0	0	0
T41	35719	0	0	0
T42	362708	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681624179	681555560	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681991999	681833798	0	0
T1	225135	225127	0	0
T2	366245	366187	0	0
T3	4306	4217	0	0
T4	668954	668871	0	0
T5	304948	304872	0	0
T6	906564	906488	0	0
T9	246150	246144	0	0
T16	25967	25894	0	0
T17	58052	57962	0	0
T18	35238	35152	0	0