Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61455742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29644153

1

T1

2007

T2

2403

T3

2542

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13854194	1			T1	772		T2	984		T3	1440
values[0x0]	37839892	1			T1	2778		T2	3206		T3	3222
values[0x1]	39405809	1			T1	2758		T2	3260		T3	3194

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52690541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38409354

1

T1

2519

T2

2981

T3

3209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	282640	1			T1	24		T3	24		T10	3
valid_sources[0x01]	283574	1			T1	16		T3	31		T10	5
valid_sources[0x02]	280037	1			T1	30		T3	67		T5	4
valid_sources[0x03]	285687	1			T1	38		T3	23		T10	4
valid_sources[0x04]	275967	1			T1	20		T10	1		T4	5
valid_sources[0x05]	1186864	1			T1	30		T5	3		T12	50
valid_sources[0x06]	745279	1			T1	30		T10	1		T5	2
valid_sources[0x07]	297120	1			T1	23		T10	7		T12	19
valid_sources[0x08]	543354	1			T1	26		T3	38		T10	2
valid_sources[0x09]	290659	1			T1	15		T3	68		T10	1
valid_sources[0x0a]	282722	1			T1	40		T3	42		T10	1
valid_sources[0x0b]	285556	1			T1	36		T5	1		T12	53
valid_sources[0x0c]	556281	1			T1	22		T3	42		T10	3
valid_sources[0x0d]	277327	1			T1	28		T5	2		T12	9
valid_sources[0x0e]	278564	1			T1	23		T3	26		T10	3
valid_sources[0x0f]	276276	1			T1	19		T5	1		T12	29
valid_sources[0x10]	276579	1			T1	22		T3	115		T10	1
valid_sources[0x11]	281083	1			T1	27		T3	11		T12	38
valid_sources[0x12]	274851	1			T1	19		T3	82		T10	2
valid_sources[0x13]	287240	1			T1	34		T3	41		T5	4
valid_sources[0x14]	664225	1			T1	32		T3	36		T10	2
valid_sources[0x15]	284172	1			T1	14		T3	3		T10	1
valid_sources[0x16]	281397	1			T1	24		T4	4		T5	2
valid_sources[0x17]	284217	1			T1	28		T3	56		T4	2
valid_sources[0x18]	281652	1			T1	6		T10	6		T5	1
valid_sources[0x19]	1049736	1			T1	28		T3	19		T5	1
valid_sources[0x1a]	278848	1			T1	33		T10	2		T4	7
valid_sources[0x1b]	273662	1			T1	24		T3	100		T10	3
valid_sources[0x1c]	287747	1			T1	21		T3	29		T10	5
valid_sources[0x1d]	273001	1			T1	17		T3	17		T10	3
valid_sources[0x1e]	306241	1			T1	28		T10	5		T5	3
valid_sources[0x1f]	1042438	1			T1	11		T3	74		T10	1
valid_sources[0x20]	275993	1			T1	19		T3	26		T5	1
valid_sources[0x21]	282567	1			T1	38		T3	30		T10	4
valid_sources[0x22]	276857	1			T1	33		T10	6		T4	17
valid_sources[0x23]	275002	1			T1	28		T3	21		T5	1
valid_sources[0x24]	291489	1			T1	23		T3	25		T5	1
valid_sources[0x25]	276880	1			T1	34		T3	26		T10	1
valid_sources[0x26]	279668	1			T1	16		T4	1		T5	1
valid_sources[0x27]	276901	1			T1	16		T3	103		T10	1
valid_sources[0x28]	279263	1			T1	34		T3	30		T10	1
valid_sources[0x29]	1089530	1			T1	28		T3	30		T4	7
valid_sources[0x2a]	280686	1			T1	12		T3	47		T10	3
valid_sources[0x2b]	278771	1			T1	22		T3	5		T10	4
valid_sources[0x2c]	278066	1			T1	29		T3	28		T10	2
valid_sources[0x2d]	274181	1			T1	24		T3	33		T10	1
valid_sources[0x2e]	283049	1			T1	21		T3	60		T5	3
valid_sources[0x2f]	283389	1			T1	19		T3	46		T5	1
valid_sources[0x30]	271784	1			T1	27		T3	26		T10	1
valid_sources[0x31]	277193	1			T1	33		T10	1		T4	1
valid_sources[0x32]	858974	1			T1	23		T3	38		T10	10
valid_sources[0x33]	277677	1			T1	19		T3	2		T10	4
valid_sources[0x34]	277424	1			T1	18		T3	1		T10	2
valid_sources[0x35]	278488	1			T1	20		T3	12		T10	1
valid_sources[0x36]	277154	1			T1	22		T3	3		T5	6
valid_sources[0x37]	283724	1			T1	18		T3	25		T12	1
valid_sources[0x38]	708533	1			T1	22		T3	82		T5	4
valid_sources[0x39]	525629	1			T1	24		T3	62		T10	3
valid_sources[0x3a]	280582	1			T1	21		T3	45		T10	3
valid_sources[0x3b]	271413	1			T1	26		T10	4		T5	4
valid_sources[0x3c]	278097	1			T1	36		T3	8		T10	3
valid_sources[0x3d]	288093	1			T1	30		T3	60		T12	49
valid_sources[0x3e]	275902	1			T1	40		T3	2		T10	1
valid_sources[0x3f]	272678	1			T1	50		T10	4		T12	21
valid_sources[0x40]	274960	1			T1	30		T3	55		T5	1
valid_sources[0x41]	295586	1			T1	38		T5	5		T12	14
valid_sources[0x42]	297785	1			T1	34		T3	6		T4	7
valid_sources[0x43]	286177	1			T1	16		T3	29		T10	2
valid_sources[0x44]	289208	1			T1	27		T3	38		T10	1
valid_sources[0x45]	785550	1			T1	29		T3	18		T5	4
valid_sources[0x46]	274169	1			T1	23		T3	2		T10	2
valid_sources[0x47]	286516	1			T1	20		T3	50		T10	1
valid_sources[0x48]	274534	1			T1	24		T3	17		T10	2
valid_sources[0x49]	293836	1			T1	16		T3	46		T10	15
valid_sources[0x4a]	280656	1			T1	19		T10	2		T5	2
valid_sources[0x4b]	283646	1			T1	27		T3	45		T12	36
valid_sources[0x4c]	401650	1			T1	26		T3	20		T10	1
valid_sources[0x4d]	682303	1			T1	35		T3	10		T10	5
valid_sources[0x4e]	277001	1			T1	20		T3	66		T10	3
valid_sources[0x4f]	326697	1			T1	21		T3	59		T10	2
valid_sources[0x50]	281516	1			T1	18		T3	1		T10	7
valid_sources[0x51]	276104	1			T1	20		T3	4		T10	6
valid_sources[0x52]	277768	1			T1	18		T3	170		T10	3
valid_sources[0x53]	282442	1			T1	16		T3	20		T4	2
valid_sources[0x54]	278353	1			T1	28		T3	8		T10	2
valid_sources[0x55]	284389	1			T1	36		T10	1		T5	2
valid_sources[0x56]	275023	1			T1	22		T3	26		T12	17
valid_sources[0x57]	545757	1			T1	17		T3	86		T10	4
valid_sources[0x58]	1179254	1			T1	20		T10	1		T4	1
valid_sources[0x59]	275977	1			T1	15		T3	31		T5	4
valid_sources[0x5a]	283714	1			T1	20		T3	71		T10	4
valid_sources[0x5b]	277233	1			T1	34		T3	35		T10	1
valid_sources[0x5c]	738510	1			T1	36		T3	65		T5	1
valid_sources[0x5d]	280929	1			T1	21		T5	2		T12	43
valid_sources[0x5e]	289766	1			T1	24		T3	69		T5	2
valid_sources[0x5f]	763762	1			T1	19		T3	79		T10	6
valid_sources[0x60]	277415	1			T1	18		T3	128		T10	1
valid_sources[0x61]	275025	1			T1	22		T3	38		T10	1
valid_sources[0x62]	278074	1			T1	29		T3	31		T4	8
valid_sources[0x63]	280077	1			T1	27		T3	19		T5	2
valid_sources[0x64]	284579	1			T1	28		T3	101		T10	7
valid_sources[0x65]	277062	1			T1	23		T10	1		T4	1
valid_sources[0x66]	276988	1			T1	21		T3	26		T6	1017
valid_sources[0x67]	281268	1			T1	23		T3	29		T5	2
valid_sources[0x68]	277777	1			T1	21		T5	2		T12	23
valid_sources[0x69]	277462	1			T1	19		T10	5		T4	1
valid_sources[0x6a]	568107	1			T1	26		T3	29		T5	1
valid_sources[0x6b]	275432	1			T1	20		T3	40		T10	2
valid_sources[0x6c]	284151	1			T1	26		T3	15		T10	1
valid_sources[0x6d]	276069	1			T1	18		T5	2		T12	26
valid_sources[0x6e]	317500	1			T1	21		T3	11		T10	2
valid_sources[0x6f]	281406	1			T1	30		T3	51		T10	1
valid_sources[0x70]	283928	1			T1	15		T3	4		T10	6
valid_sources[0x71]	686028	1			T1	15		T3	70		T10	1
valid_sources[0x72]	278258	1			T1	28		T3	56		T5	2
valid_sources[0x73]	275994	1			T1	22		T3	61		T10	2
valid_sources[0x74]	276947	1			T1	43		T4	9		T5	1
valid_sources[0x75]	279925	1			T1	32		T3	51		T4	4
valid_sources[0x76]	529900	1			T1	33		T3	3		T10	3
valid_sources[0x77]	279227	1			T1	34		T3	19		T5	4
valid_sources[0x78]	272532	1			T1	23		T5	1		T12	65
valid_sources[0x79]	700400	1			T1	41		T3	65		T10	3
valid_sources[0x7a]	306284	1			T1	27		T3	69		T4	1
valid_sources[0x7b]	284963	1			T1	17		T5	2		T12	8
valid_sources[0x7c]	276767	1			T1	26		T3	31		T10	2
valid_sources[0x7d]	277991	1			T1	32		T3	21		T5	1
valid_sources[0x7e]	277790	1			T1	31		T3	8		T10	1
valid_sources[0x7f]	279438	1			T1	37		T5	1		T12	12
valid_sources[0x80]	280030	1			T1	21		T3	3		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6842791

1

T1

388

T2

461

T3

712

values[0x0]

all_enables

biggest_size

14420653

1

T1

1047

T2

1212

T3

1193

values[0x1]

all_enables

biggest_size

8380709

1

T1

572

T2

730

T3

637