Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90,T202,T64
1	1	Covered	T2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16023	0	0
DisabledNoTrigBkwd_A	2147483647	685837	0	0
DisabledNoTrigFwd_A	2147483647	1507394900	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16023	0	0
T21	541039	0	0	0
T25	829570	0	0	0
T27	36864	0	0	0
T47	576175	0	0	0
T48	1425314	0	0	0
T63	48838	0	0	0
T64	6772	1041	0	0
T65	41744	0	0	0
T66	33878	0	0	0
T67	4533	785	0	0
T68	166086	0	0	0
T90	4075	696	0	0
T104	57672	0	0	0
T108	522117	0	0	0
T116	180740	0	0	0
T190	3672	0	0	0
T191	115623	0	0	0
T192	157958	0	0	0
T202	4081	992	0	0
T203	0	774	0	0
T204	0	1167	0	0
T205	0	369	0	0
T206	3885	362	0	0
T207	0	779	0	0
T208	0	464	0	0
T209	0	845	0	0
T210	0	704	0	0
T211	0	798	0	0
T212	0	1178	0	0
T213	0	686	0	0
T214	0	719	0	0
T215	0	567	0	0
T216	0	1107	0	0
T217	0	1334	0	0
T218	0	656	0	0
T219	86570	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	685837	0	0
T2	94553	92	0	0
T3	1432238	4	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	209	0	0
T10	4636	2	0	0
T11	118515	19	0	0
T12	187888	176	0	0
T13	491140	2194	0	0
T14	0	6	0	0
T16	2261916	3137	0	0
T17	310156	6003	0	0
T18	230152	3356	0	0
T19	0	4411	0	0
T20	1475763	601	0	0
T38	121822	24	0	0
T39	41772	18	0	0
T40	10231	19	0	0
T41	0	5	0	0
T42	0	5	0	0
T43	0	111	0	0
T44	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1507394900	0	0
T1	282524	210098	0	0
T2	378212	286395	0	0
T3	2864476	1279087	0	0
T4	91956	13382	0	0
T5	83204	2840	0	0
T10	9272	8019	0	0
T11	158020	108973	0	0
T12	187888	93017	0	0
T13	491140	377078	0	0
T16	2261916	1704757	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13
1	1	Covered	T2,T10,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T204,T207
1	1	Covered	T2,T10,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634186842	5535	0	0
DisabledNoTrigBkwd_A	634186842	164425	0	0
DisabledNoTrigFwd_A	634186842	369198359	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	5535	0	0
T27	18432	0	0	0
T48	712657	0	0	0
T64	3386	1041	0	0
T65	20872	0	0	0
T66	16939	0	0	0
T67	1511	0	0	0
T68	55362	0	0	0
T104	28836	0	0	0
T116	90370	0	0	0
T190	1836	0	0	0
T204	0	1167	0	0
T207	0	779	0	0
T208	0	464	0	0
T211	0	798	0	0
T214	0	719	0	0
T215	0	567	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	164425	0	0
T2	94553	92	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	87	0	0
T10	2318	2	0	0
T11	39505	7	0	0
T12	46972	0	0	0
T13	122785	11	0	0
T16	565479	3137	0	0
T18	0	3	0	0
T20	0	223	0	0
T41	0	5	0	0
T42	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	369198359	0	0
T1	70631	2576	0	0
T2	94553	3030	0	0
T3	716119	68493	0	0
T4	22989	3300	0	0
T5	20801	704	0	0
T10	2318	1263	0	0
T11	39505	23108	0	0
T12	46972	9825	0	0
T13	122785	121478	0	0
T16	565479	9655	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90,T202,T203
1	1	Covered	T3,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634186842	5141	0	0
DisabledNoTrigBkwd_A	634186842	154865	0	0
DisabledNoTrigFwd_A	634186842	384911737	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	5141	0	0
T21	541039	0	0	0
T47	576175	0	0	0
T63	48838	0	0	0
T64	3386	0	0	0
T65	20872	0	0	0
T66	16939	0	0	0
T67	1511	0	0	0
T68	55362	0	0	0
T90	4075	696	0	0
T202	4081	992	0	0
T203	0	774	0	0
T209	0	845	0	0
T212	0	1178	0	0
T218	0	656	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	154865	0	0
T3	716119	4	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	70	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	5	0	0
T13	122785	0	0	0
T14	0	6	0	0
T16	565479	0	0	0
T17	0	2294	0	0
T18	0	3	0	0
T19	0	1987	0	0
T20	491921	141	0	0
T38	0	19	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	384911737	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	360918	0	0
T4	22989	3332	0	0
T5	20801	708	0	0
T10	2318	2252	0	0
T11	39505	28222	0	0
T12	46972	34178	0	0
T13	122785	122315	0	0
T16	565479	564816	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T11,T12
1	1	Covered	T12,T13,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T205,T217
1	1	Covered	T12,T13,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T6,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634186842	2488	0	0
DisabledNoTrigBkwd_A	634186842	140990	0	0
DisabledNoTrigFwd_A	634186842	380027792	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	2488	0	0
T25	829570	0	0	0
T27	18432	0	0	0
T48	712657	0	0	0
T67	1511	785	0	0
T68	55362	0	0	0
T104	28836	0	0	0
T116	90370	0	0	0
T190	1836	0	0	0
T191	115623	0	0	0
T192	157958	0	0	0
T205	0	369	0	0
T217	0	1334	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	140990	0	0
T6	393524	10	0	0
T12	46972	162	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	1385	0	0
T18	115076	1848	0	0
T19	0	2424	0	0
T20	491921	127	0	0
T38	60911	0	0	0
T39	20886	2	0	0
T40	10231	6	0	0
T43	0	111	0	0
T44	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	380027792	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	181765	0	0
T4	22989	3362	0	0
T5	20801	712	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	42964	0	0
T13	122785	122523	0	0
T16	565479	564816	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T210,T213
1	1	Covered	T11,T12,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634186842	2859	0	0
DisabledNoTrigBkwd_A	634186842	225557	0	0
DisabledNoTrigFwd_A	634186842	373257012	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	2859	0	0
T61	429700	0	0	0
T94	43407	0	0	0
T108	522117	0	0	0
T188	135840	0	0	0
T206	3885	362	0	0
T210	0	704	0	0
T213	0	686	0	0
T216	0	1107	0	0
T219	86570	0	0	0
T220	32170	0	0	0
T221	150494	0	0	0
T222	287182	0	0	0
T223	366382	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	225557	0	0
T6	393524	42	0	0
T11	39505	12	0	0
T12	46972	9	0	0
T13	122785	2183	0	0
T16	565479	0	0	0
T17	155078	2324	0	0
T18	115076	1502	0	0
T20	491921	110	0	0
T38	60911	5	0	0
T39	20886	16	0	0
T40	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	373257012	0	0
T1	70631	66372	0	0
T2	94553	94455	0	0
T3	716119	667911	0	0
T4	22989	3388	0	0
T5	20801	716	0	0
T10	2318	2252	0	0
T11	39505	18211	0	0
T12	46972	6050	0	0
T13	122785	10762	0	0
T16	565479	565470	0	0