Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.81	100.00		96.44			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T3,T6,T20
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T12,T6,T20
1	0	Covered	T11,T13,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T11,T13,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Covered	T12,T6,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T10,T11,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T12,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T13,T6,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T2,T3,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T6,T20

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T10
Phase1St	198	Covered	T2,T3,T10
Phase2St	215	Covered	T2,T3,T10
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T11,T12,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T10
IdleSt->TimeoutSt	159	Covered	T11,T12,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T21,T22,T23
Phase0St->Phase1St	198	Covered	T2,T3,T10
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T20,T24
Phase1St->Phase2St	215	Covered	T2,T3,T10
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T10,T6,T21
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T19,T25
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T13,T6,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T11,T13,T16
TimeoutSt->Phase0St	172	Covered	T11,T12,T13

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T23,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T24,T21
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T21,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T19,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T6,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1183	0	0
CheckAccumTrig0_A	2147483647	2275	0	0
CheckAccumTrig1_A	2147483647	100	0	0
CheckClr_A	2147483647	1065	0	0
CheckEn_A	2147483647	1203745459	0	0
CheckPhase0_A	2147483647	2591	0	0
CheckPhase1_A	2147483647	2548	0	0
CheckPhase2_A	2147483647	2504	0	0
CheckPhase3_A	2147483647	2463	0	0
CheckTimeout0_A	2147483647	2974	0	0
CheckTimeoutSt1_A	2147483647	353188	0	0
CheckTimeoutSt2_A	2147483647	2602	0	0
CheckTimeoutStTrig_A	2147483647	262	0	0
ErrorStAllEscAsserted_A	2147483647	5727	0	0
ErrorStIsTerminal_A	2147483647	4767	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1183	0	0
T7	151720	276	0	0
T8	0	187	0	0
T9	0	270	0	0
T26	1903080	0	0	0
T28	0	147	0	0
T29	0	303	0	0
T30	181008	0	0	0
T31	86816	0	0	0
T32	3860272	0	0	0
T33	367740	0	0	0
T34	310408	0	0	0
T35	1181376	0	0	0
T36	281336	0	0	0
T37	1673592	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2275	0	0
T2	94553	1	0	0
T3	1432238	1	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	12	0	0
T10	4636	1	0	0
T11	118515	1	0	0
T12	140916	2	0	0
T13	368355	3	0	0
T14	0	2	0	0
T16	1696437	0	0	0
T17	310156	4	0	0
T18	230152	7	0	0
T19	0	4	0	0
T20	1475763	19	0	0
T38	121822	2	0	0
T39	41772	2	0	0
T40	10231	2	0	0
T41	18572	1	0	0
T42	50368	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	10201	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	100	0	0
T6	787048	1	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	1	0	0
T16	565479	1	0	0
T17	310156	0	0	0
T18	230152	0	0	0
T20	983842	3	0	0
T38	121822	0	0	0
T39	41772	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T47	576175	4	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	48838	0	0	0
T64	3386	0	0	0
T65	20872	0	0	0
T66	16939	0	0	0
T67	1511	0	0	0
T68	55362	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	1180572	2	0	0
T10	2318	1	0	0
T11	39505	0	0	0
T12	46972	0	0	0
T13	245570	2	0	0
T16	1130958	0	0	0
T17	620312	1	0	0
T18	345228	4	0	0
T19	0	1	0	0
T20	1967684	15	0	0
T21	0	20	0	0
T24	0	5	0	0
T25	0	9	0	0
T27	0	2	0	0
T38	182733	1	0	0
T39	62658	0	0	0
T40	30693	0	0	0
T41	55716	0	0	0
T42	100736	1	0	0
T46	20402	0	0	0
T47	0	22	0	0
T48	0	12	0	0
T63	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	17857	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1203745459	0	0
T1	282524	210095	0	0
T2	378212	286392	0	0
T3	2864476	1198501	0	0
T4	91956	13378	0	0
T5	83204	2836	0	0
T10	9272	8016	0	0
T11	158020	78537	0	0
T12	187888	31551	0	0
T13	491140	259393	0	0
T16	2261916	1704757	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2591	0	0
T2	94553	1	0	0
T3	1432238	1	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	16	0	0
T10	4636	1	0	0
T11	118515	2	0	0
T12	187888	4	0	0
T13	491140	4	0	0
T14	0	1	0	0
T16	2261916	1	0	0
T17	310156	4	0	0
T18	230152	7	0	0
T19	0	3	0	0
T20	1475763	23	0	0
T38	121822	2	0	0
T39	41772	2	0	0
T40	10231	4	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2548	0	0
T2	94553	1	0	0
T3	1432238	1	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	15	0	0
T10	4636	1	0	0
T11	118515	2	0	0
T12	187888	4	0	0
T13	491140	4	0	0
T14	0	1	0	0
T16	2261916	1	0	0
T17	310156	4	0	0
T18	230152	7	0	0
T19	0	3	0	0
T20	1475763	22	0	0
T38	121822	2	0	0
T39	41772	2	0	0
T40	10231	4	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2504	0	0
T2	94553	1	0	0
T3	1432238	1	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	14	0	0
T10	4636	0	0	0
T11	118515	2	0	0
T12	187888	4	0	0
T13	491140	4	0	0
T14	0	1	0	0
T16	2261916	1	0	0
T17	310156	3	0	0
T18	230152	7	0	0
T19	0	3	0	0
T20	1475763	22	0	0
T38	121822	2	0	0
T39	41772	2	0	0
T40	10231	4	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2463	0	0
T2	94553	1	0	0
T3	1432238	1	0	0
T4	45978	0	0	0
T5	41602	0	0	0
T6	1574096	13	0	0
T10	4636	0	0	0
T11	118515	2	0	0
T12	187888	4	0	0
T13	491140	4	0	0
T14	0	1	0	0
T16	2261916	1	0	0
T17	310156	3	0	0
T18	230152	7	0	0
T19	0	2	0	0
T20	1475763	22	0	0
T38	121822	2	0	0
T39	41772	2	0	0
T40	10231	4	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2974	0	0
T6	1574096	101	0	0
T11	118515	3	0	0
T12	187888	2	0	0
T13	491140	4	0	0
T16	2261916	5	0	0
T17	620312	0	0	0
T18	460304	0	0	0
T20	1967684	6	0	0
T21	0	6	0	0
T38	243644	0	0	0
T39	83544	0	0	0
T40	10231	2	0	0
T44	0	4	0	0
T46	0	7	0	0
T47	0	18	0	0
T48	0	8	0	0
T70	0	8	0	0
T75	0	12	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353188	0	0
T6	1574096	18719	0	0
T11	118515	258	0	0
T12	187888	1173	0	0
T13	491140	162	0	0
T16	2261916	410	0	0
T17	620312	0	0	0
T18	460304	0	0	0
T20	1967684	1213	0	0
T21	0	753	0	0
T38	243644	0	0	0
T39	83544	0	0	0
T40	10231	999	0	0
T44	0	481	0	0
T46	0	1008	0	0
T47	0	2839	0	0
T48	0	566	0	0
T70	0	600	0	0
T75	0	840	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2602	0	0
T6	1574096	95	0	0
T11	79010	2	0	0
T12	93944	0	0	0
T13	368355	3	0	0
T16	2261916	4	0	0
T17	620312	0	0	0
T18	460304	0	0	0
T20	1967684	2	0	0
T21	0	8	0	0
T22	0	7	0	0
T38	243644	0	0	0
T39	83544	0	0	0
T40	20462	0	0	0
T41	37144	0	0	0
T44	0	4	0	0
T46	10201	7	0	0
T47	0	17	0	0
T48	0	7	0	0
T50	0	8	0	0
T70	0	7	0	0
T73	0	1	0	0
T75	0	12	0	0
T76	0	1	0	0
T77	0	14	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262	0	0
T6	1574096	2	0	0
T12	93944	2	0	0
T13	245570	0	0	0
T16	1130958	0	0	0
T17	620312	0	0	0
T18	460304	0	0	0
T20	1967684	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T38	243644	0	0	0
T39	83544	0	0	0
T40	40924	1	0	0
T41	37144	0	0	0
T42	100736	0	0	0
T46	20402	0	0	0
T47	0	4	0	0
T50	0	1	0	0
T53	0	1	0	0
T55	0	4	0	0
T57	0	4	0	0
T70	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5727	0	0
T7	151720	1434	0	0
T8	0	746	0	0
T9	0	1427	0	0
T26	1903080	0	0	0
T28	0	687	0	0
T29	0	1433	0	0
T30	181008	0	0	0
T31	86816	0	0	0
T32	3860272	0	0	0
T33	367740	0	0	0
T34	310408	0	0	0
T35	1181376	0	0	0
T36	281336	0	0	0
T37	1673592	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4767	0	0
T7	151720	1194	0	0
T8	0	626	0	0
T9	0	1187	0	0
T26	1903080	0	0	0
T28	0	567	0	0
T29	0	1193	0	0
T30	181008	0	0	0
T31	86816	0	0	0
T32	3860272	0	0	0
T33	367740	0	0	0
T34	310408	0	0	0
T35	1181376	0	0	0
T36	281336	0	0	0
T37	1673592	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	282524	282300	0	0
T2	378212	377820	0	0
T3	2864476	2864188	0	0
T4	91956	91460	0	0
T5	83204	82528	0	0
T10	9272	9008	0	0
T11	158020	157728	0	0
T12	187888	187508	0	0
T13	491140	491108	0	0
T16	2261916	2261880	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	282524	282300	0	0
T2	378212	377820	0	0
T3	2864476	2864188	0	0
T4	91956	91460	0	0
T5	83204	82528	0	0
T10	9272	9008	0	0
T11	158020	157728	0	0
T12	187888	187508	0	0
T13	491140	491108	0	0
T16	2261916	2261880	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T18,T14,T43
1	1	0	Covered	T12,T13,T6
1	1	1	Covered	T11,T12,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T12,T40,T22
1	0	Covered	T11,T13,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T12,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T13,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Covered	T12,T40,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T6
1	Covered	T10,T11,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T6,T20,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T20,T18,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T2,T13,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T11,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T6,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T10,T11
Phase1St	198	Covered	T2,T10,T11
Phase2St	215	Covered	T2,T10,T11
Phase3St	233	Covered	T2,T11,T12
TerminalSt	249	Covered	T2,T11,T12
TimeoutSt	159	Covered	T11,T12,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T10,T13
IdleSt->TimeoutSt	159	Covered	T11,T12,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T53,T83
Phase0St->Phase1St	198	Covered	T2,T10,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T20,T21
Phase1St->Phase2St	215	Covered	T2,T10,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T10,T21,T27
Phase2St->Phase3St	233	Covered	T2,T11,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T86,T87,T80
Phase3St->TerminalSt	249	Covered	T2,T11,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T6,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T6,T44
TimeoutSt->Phase0St	172	Covered	T11,T12,T13

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T6,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T53,T88,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T21,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T10,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T10,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T21,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T86,T87,T80
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T20,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634186842	305	0	0
CheckAccumTrig0_A	634186842	856	0	0
CheckAccumTrig1_A	634186842	46	0	0
CheckClr_A	634186842	448	0	0
CheckEn_A	633990674	285151086	0	0
CheckPhase0_A	634186842	946	0	0
CheckPhase1_A	634186842	929	0	0
CheckPhase2_A	634186842	911	0	0
CheckPhase3_A	634186842	892	0	0
CheckTimeout0_A	634186842	786	0	0
CheckTimeoutSt1_A	634186842	89854	0	0
CheckTimeoutSt2_A	634186842	679	0	0
CheckTimeoutStTrig_A	634186842	59	0	0
ErrorStAllEscAsserted_A	634186842	1429	0	0
ErrorStIsTerminal_A	634186842	1189	0	0
EscStateOut_A	633988528	633915282	0	0
u_state_regs_A	634186842	634012009	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	305	0	0
T7	37930	61	0	0
T8	0	63	0	0
T9	0	59	0	0
T26	475770	0	0	0
T28	0	54	0	0
T29	0	68	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	856	0	0
T2	94553	1	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	5	0	0
T10	2318	1	0	0
T11	39505	0	0	0
T12	46972	0	0	0
T13	122785	1	0	0
T14	0	1	0	0
T16	565479	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	10	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	46	0	0
T6	393524	0	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	1	0	0
T16	565479	1	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	2	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	448	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	0	0	0
T10	2318	1	0	0
T11	39505	0	0	0
T12	46972	0	0	0
T13	122785	1	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	0	2	0	0
T20	491921	10	0	0
T21	0	9	0	0
T27	0	2	0	0
T42	0	1	0	0
T47	0	8	0	0
T48	0	7	0	0
T63	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633990674	285151086	0	0
T1	70631	2576	0	0
T2	94553	3030	0	0
T3	716119	68493	0	0
T4	22989	3299	0	0
T5	20801	703	0	0
T10	2318	1263	0	0
T11	39505	2055	0	0
T12	46972	6062	0	0
T13	122785	7497	0	0
T16	565479	9655	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	946	0	0
T2	94553	1	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	5	0	0
T10	2318	1	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	1	0	0
T18	0	2	0	0
T20	0	12	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	929	0	0
T2	94553	1	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	4	0	0
T10	2318	1	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	1	0	0
T18	0	2	0	0
T20	0	11	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	911	0	0
T2	94553	1	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	4	0	0
T10	2318	0	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	1	0	0
T18	0	2	0	0
T20	0	11	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	892	0	0
T2	94553	1	0	0
T3	716119	0	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	4	0	0
T10	2318	0	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	1	0	0
T18	0	2	0	0
T20	0	11	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	786	0	0
T6	393524	69	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	1	0	0
T16	565479	5	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	2	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T70	0	2	0	0
T75	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	89854	0	0
T6	393524	12341	0	0
T11	39505	30	0	0
T12	46972	594	0	0
T13	122785	3	0	0
T16	565479	410	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	6	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	0	998	0	0
T44	0	93	0	0
T70	0	165	0	0
T75	0	222	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	679	0	0
T6	393524	69	0	0
T16	565479	4	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	5	0	0
T22	0	2	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T44	0	1	0	0
T46	10201	0	0	0
T47	0	6	0	0
T70	0	2	0	0
T73	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	59	0	0
T6	393524	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T22	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	1	0	0
T50	0	1	0	0
T55	0	2	0	0
T57	0	4	0	0
T77	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1429	0	0
T7	37930	366	0	0
T8	0	188	0	0
T9	0	344	0	0
T26	475770	0	0	0
T28	0	174	0	0
T29	0	357	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1189	0	0
T7	37930	306	0	0
T8	0	158	0	0
T9	0	284	0	0
T26	475770	0	0	0
T28	0	144	0	0
T29	0	297	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633988528	633915282	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	634012009	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T3,T6,T20
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T13,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T6
0	1	Covered	T6,T20,T21
1	0	Covered	T6,T20,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T13,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T20,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T6
1	0	Not Covered
1	1	Covered	T6,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T6
1	Covered	T20,T69,T90

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T20
1	Covered	T12,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T6
1	Covered	T20,T18,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T6,T20
1	Covered	T3,T6,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T12,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T6,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T12,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T20,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T6
Phase1St	198	Covered	T3,T12,T6
Phase2St	215	Covered	T3,T12,T6
Phase3St	233	Covered	T3,T12,T6
TerminalSt	249	Covered	T3,T12,T6
TimeoutSt	159	Covered	T11,T13,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T3,T12,T6
IdleSt->TimeoutSt	159	Covered	T11,T13,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T91,T92
Phase0St->Phase1St	198	Covered	T3,T12,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T21,T48
Phase1St->Phase2St	215	Covered	T3,T12,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T21,T80,T93
Phase2St->Phase3St	233	Covered	T3,T12,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T94,T95,T96
Phase3St->TerminalSt	249	Covered	T3,T12,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T20,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T13,T6
TimeoutSt->Phase0St	172	Covered	T6,T20,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T91,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T21,T48
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T80,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T94,T95,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T18,T69
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634186842	292	0	0
CheckAccumTrig0_A	634186842	468	0	0
CheckAccumTrig1_A	634186842	22	0	0
CheckClr_A	634186842	193	0	0
CheckEn_A	633990674	305181094	0	0
CheckPhase0_A	634186842	535	0	0
CheckPhase1_A	634186842	528	0	0
CheckPhase2_A	634186842	516	0	0
CheckPhase3_A	634186842	509	0	0
CheckTimeout0_A	634186842	582	0	0
CheckTimeoutSt1_A	634186842	79236	0	0
CheckTimeoutSt2_A	634186842	499	0	0
CheckTimeoutStTrig_A	634186842	58	0	0
ErrorStAllEscAsserted_A	634186842	1417	0	0
ErrorStIsTerminal_A	634186842	1177	0	0
EscStateOut_A	633988528	633915282	0	0
u_state_regs_A	634186842	634012009	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	292	0	0
T7	37930	75	0	0
T8	0	35	0	0
T9	0	72	0	0
T26	475770	0	0	0
T28	0	37	0	0
T29	0	73	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	468	0	0
T3	716119	1	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	1	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T14	0	1	0	0
T16	565479	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	491921	2	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	22	0	0
T6	393524	1	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	193	0	0
T17	155078	0	0	0
T18	115076	1	0	0
T20	491921	1	0	0
T21	0	6	0	0
T24	0	2	0	0
T25	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T47	0	7	0	0
T48	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	17857	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633990674	305181094	0	0
T1	70631	70574	0	0
T2	94553	94454	0	0
T3	716119	280333	0	0
T4	22989	3331	0	0
T5	20801	707	0	0
T10	2318	2251	0	0
T11	39505	28221	0	0
T12	46972	17261	0	0
T13	122785	122314	0	0
T16	565479	564816	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	535	0	0
T3	716119	1	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	3	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T14	0	1	0	0
T16	565479	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	491921	4	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	528	0	0
T3	716119	1	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	3	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T14	0	1	0	0
T16	565479	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	491921	4	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	516	0	0
T3	716119	1	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	3	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T14	0	1	0	0
T16	565479	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	491921	4	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	509	0	0
T3	716119	1	0	0
T4	22989	0	0	0
T5	20801	0	0	0
T6	393524	3	0	0
T10	2318	0	0	0
T11	39505	0	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T14	0	1	0	0
T16	565479	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	491921	4	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	582	0	0
T6	393524	28	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	3	0	0
T21	0	3	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T46	0	5	0	0
T47	0	3	0	0
T48	0	3	0	0
T70	0	1	0	0
T75	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	79236	0	0
T6	393524	5951	0	0
T11	39505	111	0	0
T12	46972	0	0	0
T13	122785	107	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	391	0	0
T21	0	187	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T46	0	727	0	0
T47	0	986	0	0
T48	0	252	0	0
T70	0	63	0	0
T75	0	214	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	499	0	0
T6	393524	25	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	1	0	0
T21	0	2	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T46	0	5	0	0
T47	0	2	0	0
T48	0	3	0	0
T70	0	1	0	0
T75	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	58	0	0
T6	393524	1	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	1	0	0
T21	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1417	0	0
T7	37930	338	0	0
T8	0	179	0	0
T9	0	373	0	0
T26	475770	0	0	0
T28	0	181	0	0
T29	0	346	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1177	0	0
T7	37930	278	0	0
T8	0	149	0	0
T9	0	313	0	0
T26	475770	0	0	0
T28	0	151	0	0
T29	0	286	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633988528	633915282	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	634012009	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T13,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T20,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T6
1	0	1	Covered	T20,T17,T43
1	1	0	Covered	T11,T13,T16
1	1	1	Covered	T12,T13,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T6
0	1	Covered	T12,T6,T70
1	0	Covered	T47,T48,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T13,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T48,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T6
1	0	Not Covered
1	1	Covered	T12,T6,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T6,T20
1	Covered	T6,T20,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T6,T20
1	Covered	T6,T20,T39

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T6,T20
1	Covered	T6,T20,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T20,T17
1	Covered	T12,T40,T44

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T20,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T20,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T18,T39,T40

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T6,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T12,T6,T20
Phase1St	198	Covered	T12,T6,T20
Phase2St	215	Covered	T12,T6,T20
Phase3St	233	Covered	T12,T6,T20
TerminalSt	249	Covered	T12,T6,T20
TimeoutSt	159	Covered	T12,T13,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T6,T20,T17
IdleSt->TimeoutSt	159	Covered	T12,T13,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T23,T26
Phase0St->Phase1St	198	Covered	T12,T6,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T97,T98
Phase1St->Phase2St	215	Covered	T12,T6,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T94,T99
Phase2St->Phase3St	233	Covered	T12,T6,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T19,T25
Phase3St->TerminalSt	249	Covered	T12,T6,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T20,T70
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T46,T44
TimeoutSt->Phase0St	172	Covered	T12,T6,T70

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T6,T70
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T46,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T23,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T12,T6,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T12,T6,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T12,T6,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T12,T6,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T94,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T12,T6,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T12,T6,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T19,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T6,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T12,T6,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T20,T70
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T6,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634186842	288	0	0
CheckAccumTrig0_A	634186842	486	0	0
CheckAccumTrig1_A	634186842	8	0	0
CheckClr_A	634186842	222	0	0
CheckEn_A	633990674	311306984	0	0
CheckPhase0_A	634186842	557	0	0
CheckPhase1_A	634186842	547	0	0
CheckPhase2_A	634186842	540	0	0
CheckPhase3_A	634186842	533	0	0
CheckTimeout0_A	634186842	448	0	0
CheckTimeoutSt1_A	634186842	59726	0	0
CheckTimeoutSt2_A	634186842	365	0	0
CheckTimeoutStTrig_A	634186842	72	0	0
ErrorStAllEscAsserted_A	634186842	1399	0	0
ErrorStIsTerminal_A	634186842	1159	0	0
EscStateOut_A	633988528	633915282	0	0
u_state_regs_A	634186842	634012009	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	288	0	0
T7	37930	63	0	0
T8	0	52	0	0
T9	0	79	0	0
T26	475770	0	0	0
T28	0	26	0	0
T29	0	68	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	486	0	0
T6	393524	3	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T19	0	2	0	0
T20	491921	3	0	0
T38	60911	0	0	0
T39	20886	1	0	0
T40	10231	1	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	10201	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	8	0	0
T27	18432	0	0	0
T47	576175	3	0	0
T48	712657	1	0	0
T62	0	1	0	0
T63	48838	0	0	0
T64	3386	0	0	0
T65	20872	0	0	0
T66	16939	0	0	0
T67	1511	0	0	0
T68	55362	0	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	28836	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	222	0	0
T6	393524	2	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T19	0	1	0	0
T20	491921	2	0	0
T21	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T47	0	7	0	0
T48	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633990674	311306984	0	0
T1	70631	70574	0	0
T2	94553	94454	0	0
T3	716119	181765	0	0
T4	22989	3361	0	0
T5	20801	711	0	0
T10	2318	2251	0	0
T11	39505	39431	0	0
T12	46972	6088	0	0
T13	122785	122523	0	0
T16	565479	564816	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	557	0	0
T6	393524	4	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T19	0	2	0	0
T20	491921	3	0	0
T38	60911	0	0	0
T39	20886	1	0	0
T40	10231	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	547	0	0
T6	393524	4	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T19	0	2	0	0
T20	491921	3	0	0
T38	60911	0	0	0
T39	20886	1	0	0
T40	10231	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	540	0	0
T6	393524	3	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T19	0	2	0	0
T20	491921	3	0	0
T38	60911	0	0	0
T39	20886	1	0	0
T40	10231	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	533	0	0
T6	393524	2	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T19	0	1	0	0
T20	491921	3	0	0
T38	60911	0	0	0
T39	20886	1	0	0
T40	10231	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	448	0	0
T6	393524	1	0	0
T12	46972	1	0	0
T13	122785	1	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	2	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	11	0	0
T48	0	4	0	0
T70	0	1	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	59726	0	0
T6	393524	37	0	0
T12	46972	579	0	0
T13	122785	52	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	428	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T44	0	161	0	0
T46	0	281	0	0
T47	0	1149	0	0
T48	0	176	0	0
T70	0	16	0	0
T75	0	140	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	365	0	0
T6	393524	0	0	0
T13	122785	1	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	3	0	0
T50	0	4	0	0
T75	0	2	0	0
T77	0	14	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	72	0	0
T6	393524	1	0	0
T12	46972	1	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T47	0	3	0	0
T70	0	1	0	0
T73	0	1	0	0
T79	0	1	0	0
T105	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1399	0	0
T7	37930	369	0	0
T8	0	196	0	0
T9	0	346	0	0
T26	475770	0	0	0
T28	0	143	0	0
T29	0	345	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1159	0	0
T7	37930	309	0	0
T8	0	166	0	0
T9	0	286	0	0
T26	475770	0	0	0
T28	0	113	0	0
T29	0	285	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633988528	633915282	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	634012009	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T12,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T20,T17,T38
1	1	0	Covered	T11,T13,T16
1	1	1	Covered	T11,T6,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T6,T20
0	1	Covered	T6,T21,T22
1	0	Covered	T6,T40,T80

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T6,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T40,T80

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T6,T20
1	0	Not Covered
1	1	Covered	T6,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T11,T13,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T6
1	Covered	T12,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T20,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T6,T20,T71

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T13,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T13,T6,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T20,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T12,T13
Phase1St	198	Covered	T11,T12,T13
Phase2St	215	Covered	T11,T12,T13
Phase3St	233	Covered	T11,T12,T13
TerminalSt	249	Covered	T11,T12,T13
TimeoutSt	159	Covered	T11,T6,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T11,T12,T13
IdleSt->TimeoutSt	159	Covered	T11,T6,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T22,T106
Phase0St->Phase1St	198	Covered	T11,T12,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T54,T59
Phase1St->Phase2St	215	Covered	T11,T12,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T107,T108
Phase2St->Phase3St	233	Covered	T11,T12,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T109,T59,T110
Phase3St->TerminalSt	249	Covered	T11,T12,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T6,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T6,T20
TimeoutSt->Phase0St	172	Covered	T6,T40,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T6,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T40,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T6,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T6,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T106,T107,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T12,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T12,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T54,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T12,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T12,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T107,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T12,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T109,T59,T110
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T12,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T20,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T12,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634186842	298	0	0
CheckAccumTrig0_A	634186842	465	0	0
CheckAccumTrig1_A	634186842	24	0	0
CheckClr_A	634186842	202	0	0
CheckEn_A	633990674	302106295	0	0
CheckPhase0_A	634186842	553	0	0
CheckPhase1_A	634186842	544	0	0
CheckPhase2_A	634186842	537	0	0
CheckPhase3_A	634186842	529	0	0
CheckTimeout0_A	634186842	1158	0	0
CheckTimeoutSt1_A	634186842	124372	0	0
CheckTimeoutSt2_A	634186842	1059	0	0
CheckTimeoutStTrig_A	634186842	73	0	0
ErrorStAllEscAsserted_A	634186842	1482	0	0
ErrorStIsTerminal_A	634186842	1242	0	0
EscStateOut_A	633988528	633915282	0	0
u_state_regs_A	634186842	634012009	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	298	0	0
T7	37930	77	0	0
T8	0	37	0	0
T9	0	60	0	0
T26	475770	0	0	0
T28	0	30	0	0
T29	0	94	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	465	0	0
T6	393524	3	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	2	0	0
T18	115076	2	0	0
T20	491921	4	0	0
T38	60911	1	0	0
T39	20886	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	24	0	0
T6	393524	1	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	1	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T54	0	3	0	0
T57	0	1	0	0
T60	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	202	0	0
T6	393524	0	0	0
T13	122785	1	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	1	0	0
T20	491921	2	0	0
T21	0	4	0	0
T24	0	1	0	0
T38	60911	1	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T48	0	2	0	0
T71	0	1	0	0
T116	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633990674	302106295	0	0
T1	70631	66371	0	0
T2	94553	94454	0	0
T3	716119	667910	0	0
T4	22989	3387	0	0
T5	20801	715	0	0
T10	2318	2251	0	0
T11	39505	8830	0	0
T12	46972	2140	0	0
T13	122785	7059	0	0
T16	565479	565470	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	553	0	0
T6	393524	4	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	2	0	0
T18	115076	2	0	0
T20	491921	4	0	0
T38	60911	1	0	0
T39	20886	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	544	0	0
T6	393524	4	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	2	0	0
T18	115076	2	0	0
T20	491921	4	0	0
T38	60911	1	0	0
T39	20886	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	537	0	0
T6	393524	4	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	2	0	0
T20	491921	4	0	0
T38	60911	1	0	0
T39	20886	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	529	0	0
T6	393524	4	0	0
T11	39505	1	0	0
T12	46972	1	0	0
T13	122785	2	0	0
T16	565479	0	0	0
T17	155078	1	0	0
T18	115076	2	0	0
T20	491921	4	0	0
T38	60911	1	0	0
T39	20886	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1158	0	0
T6	393524	3	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	1	0	0
T21	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	0	1	0	0
T44	0	2	0	0
T47	0	4	0	0
T48	0	1	0	0
T70	0	4	0	0
T75	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	124372	0	0
T6	393524	390	0	0
T11	39505	117	0	0
T12	46972	0	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	816	0	0
T21	0	138	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	0	1	0	0
T44	0	227	0	0
T47	0	704	0	0
T48	0	138	0	0
T70	0	356	0	0
T75	0	264	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1059	0	0
T6	393524	1	0	0
T11	39505	1	0	0
T12	46972	0	0	0
T13	122785	0	0	0
T16	565479	0	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	1	0	0
T22	0	5	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T44	0	2	0	0
T47	0	4	0	0
T48	0	1	0	0
T50	0	4	0	0
T70	0	4	0	0
T75	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	73	0	0
T6	393524	1	0	0
T17	155078	0	0	0
T18	115076	0	0	0
T20	491921	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T38	60911	0	0	0
T39	20886	0	0	0
T40	10231	0	0	0
T41	18572	0	0	0
T42	50368	0	0	0
T46	10201	0	0	0
T50	0	3	0	0
T55	0	6	0	0
T80	0	1	0	0
T83	0	1	0	0
T105	0	1	0	0
T107	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1482	0	0
T7	37930	361	0	0
T8	0	183	0	0
T9	0	364	0	0
T26	475770	0	0	0
T28	0	189	0	0
T29	0	385	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	1242	0	0
T7	37930	301	0	0
T8	0	153	0	0
T9	0	304	0	0
T26	475770	0	0	0
T28	0	159	0	0
T29	0	325	0	0
T30	45252	0	0	0
T31	21704	0	0	0
T32	965068	0	0	0
T33	91935	0	0	0
T34	77602	0	0	0
T35	295344	0	0	0
T36	70334	0	0	0
T37	418398	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633988528	633915282	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634186842	634012009	0	0
T1	70631	70575	0	0
T2	94553	94455	0	0
T3	716119	716047	0	0
T4	22989	22865	0	0
T5	20801	20632	0	0
T10	2318	2252	0	0
T11	39505	39432	0	0
T12	46972	46877	0	0
T13	122785	122777	0	0
T16	565479	565470	0	0