Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T68,T192
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15805	0	0
DisabledNoTrigBkwd_A	2147483647	781570	0	0
DisabledNoTrigFwd_A	2147483647	1490400465	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15805	0	0
T23	95848	0	0	0
T26	391464	0	0	0
T29	1430856	0	0	0
T30	179498	0	0	0
T48	516548	0	0	0
T57	212210	0	0	0
T67	5089	1749	0	0
T68	7024	722	0	0
T69	733158	0	0	0
T70	36958	0	0	0
T71	57792	0	0	0
T72	123044	0	0	0
T116	40577	0	0	0
T192	0	761	0	0
T193	0	463	0	0
T194	0	714	0	0
T195	2887	520	0	0
T196	0	1068	0	0
T197	0	246	0	0
T198	0	631	0	0
T199	0	1012	0	0
T200	0	343	0	0
T201	0	1743	0	0
T202	0	1300	0	0
T203	0	666	0	0
T204	0	360	0	0
T205	0	621	0	0
T206	0	1267	0	0
T207	0	310	0	0
T208	0	555	0	0
T209	0	754	0	0
T210	8094	0	0	0
T211	134833	0	0	0
T212	149212	0	0	0
T213	6407	0	0	0
T214	78309	0	0	0
T215	101601	0	0	0
T216	42079	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	781570	0	0
T1	984808	468	0	0
T2	3965208	1088	0	0
T3	132912	4	0	0
T4	2044876	2537	0	0
T5	476456	1	0	0
T6	0	5	0	0
T7	0	6	0	0
T8	0	431	0	0
T14	0	5032	0	0
T15	0	1878	0	0
T16	0	1638	0	0
T17	0	4840	0	0
T18	307276	104	0	0
T19	38032	0	0	0
T20	160528	0	0	0
T21	137140	0	0	0
T22	1100316	100	0	0
T44	46378	500	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	29	0	0
T48	0	1841	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490400465	0	0
T1	1969616	998727	0	0
T2	3965208	2118731	0	0
T3	132912	127384	0	0
T4	2044876	1892863	0	0
T5	476456	327585	0	0
T18	307276	163000	0	0
T19	38032	28983	0	0
T20	160528	69178	0	0
T21	137140	75682	0	0
T22	1100316	312764	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T194
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	673875608	1436	0	0
DisabledNoTrigBkwd_A	673875608	236695	0	0
DisabledNoTrigFwd_A	673875608	356028287	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1436	0	0
T23	47924	0	0	0
T26	195732	0	0	0
T29	715428	0	0	0
T30	89749	0	0	0
T48	258274	0	0	0
T68	3512	722	0	0
T69	366579	0	0	0
T70	18479	0	0	0
T71	28896	0	0	0
T72	123044	0	0	0
T194	0	714	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	236695	0	0
T1	492404	466	0	0
T2	991302	151	0	0
T3	33228	4	0	0
T4	511219	191	0	0
T5	119114	1	0	0
T14	0	2884	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	3	0	0
T44	0	7	0	0
T45	0	2	0	0
T47	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	356028287	0	0
T1	492404	12441	0	0
T2	991302	767156	0	0
T3	33228	27865	0	0
T4	511219	444759	0	0
T5	119114	86392	0	0
T18	76819	72265	0	0
T19	9508	615	0	0
T20	40132	23328	0	0
T21	34285	20262	0	0
T22	275079	3043	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T18,T4
1	1	Covered	T1,T2,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T201,T203
1	1	Covered	T1,T2,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	673875608	3910	0	0
DisabledNoTrigBkwd_A	673875608	179518	0	0
DisabledNoTrigFwd_A	673875608	385705823	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	3910	0	0
T57	212210	0	0	0
T116	40577	0	0	0
T195	2887	520	0	0
T201	0	1743	0	0
T203	0	666	0	0
T204	0	360	0	0
T205	0	621	0	0
T210	8094	0	0	0
T211	134833	0	0	0
T212	149212	0	0	0
T213	6407	0	0	0
T214	78309	0	0	0
T215	101601	0	0	0
T216	42079	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	179518	0	0
T1	492404	2	0	0
T2	991302	473	0	0
T3	33228	0	0	0
T4	511219	2123	0	0
T5	119114	0	0	0
T8	0	424	0	0
T15	0	560	0	0
T18	76819	70	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	46	0	0
T44	0	66	0	0
T46	0	1	0	0
T47	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	385705823	0	0
T1	492404	2675	0	0
T2	991302	37413	0	0
T3	33228	33173	0	0
T4	511219	525244	0	0
T5	119114	119027	0	0
T18	76819	13365	0	0
T19	9508	9456	0	0
T20	40132	17087	0	0
T21	34285	14626	0	0
T22	275079	3068	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T18,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T197,T207
1	1	Covered	T2,T18,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T18,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	673875608	3614	0	0
DisabledNoTrigBkwd_A	673875608	190347	0	0
DisabledNoTrigFwd_A	673875608	352533285	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	3614	0	0
T23	47924	0	0	0
T26	195732	0	0	0
T29	715428	0	0	0
T30	89749	0	0	0
T48	258274	0	0	0
T67	5089	1749	0	0
T68	3512	0	0	0
T69	366579	0	0	0
T70	18479	0	0	0
T71	28896	0	0	0
T197	0	246	0	0
T207	0	310	0	0
T208	0	555	0	0
T209	0	754	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	190347	0	0
T2	991302	278	0	0
T3	33228	0	0	0
T4	511219	119	0	0
T5	119114	0	0	0
T8	0	3	0	0
T14	0	2143	0	0
T15	0	1002	0	0
T18	76819	34	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	51	0	0
T44	23189	427	0	0
T46	0	2	0	0
T47	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	352533285	0	0
T1	492404	491806	0	0
T2	991302	659625	0	0
T3	33228	33173	0	0
T4	511219	453576	0	0
T5	119114	119027	0	0
T18	76819	613	0	0
T19	9508	9456	0	0
T20	40132	7867	0	0
T21	34285	21391	0	0
T22	275079	31666	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T18
1	1	Covered	T2,T4,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T193,T196
1	1	Covered	T2,T4,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	673875608	6845	0	0
DisabledNoTrigBkwd_A	673875608	175010	0	0
DisabledNoTrigFwd_A	673875608	396133070	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	6845	0	0
T32	149819	0	0	0
T192	1575	761	0	0
T193	1149	463	0	0
T196	0	1068	0	0
T198	0	631	0	0
T199	0	1012	0	0
T200	0	343	0	0
T202	0	1300	0	0
T206	0	1267	0	0
T217	30510	0	0	0
T218	45471	0	0	0
T219	214132	0	0	0
T220	5028	0	0	0
T221	411008	0	0	0
T222	97267	0	0	0
T223	30487	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	175010	0	0
T2	991302	186	0	0
T3	33228	0	0	0
T4	511219	104	0	0
T5	119114	0	0	0
T6	0	5	0	0
T7	0	6	0	0
T8	0	4	0	0
T14	0	5	0	0
T15	0	316	0	0
T16	0	1638	0	0
T17	0	4840	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T44	23189	0	0	0
T48	0	1841	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	396133070	0	0
T1	492404	491805	0	0
T2	991302	654537	0	0
T3	33228	33173	0	0
T4	511219	469284	0	0
T5	119114	3139	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	20896	0	0
T21	34285	19403	0	0
T22	275079	274987	0	0