SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T6,T15 | Yes | T4,T6,T15 | INPUT |
ping_ok_o | Yes | Yes | T4,T15,T8 | Yes | T4,T15,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T44 | Yes | T2,T4,T44 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T6,T15 | Yes | T4,T15,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T15,T16 | Yes | T4,T6,T15 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T15,T8 | Yes | T4,T15,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T15,T8 | Yes | T4,T15,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T16,T72 | Yes | T4,T16,T72 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T15,T69 | Yes | T4,T15,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T15,T224 | Yes | T4,T15,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T6,T8,T16 | Yes | T6,T8,T16 | INPUT |
ping_ok_o | Yes | Yes | T8,T16,T17 | Yes | T8,T16,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T6,T16,T17 | Yes | T16,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T225 | Yes | T6,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T6,T69 | Yes | T4,T6,T69 | INPUT |
ping_ok_o | Yes | Yes | T4,T69,T73 | Yes | T4,T69,T73 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T44 | Yes | T2,T4,T44 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T6,T69 | Yes | T4,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T224,T225 | Yes | T4,T6,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T7 | Yes | T1,T4,T7 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T7 | Yes | T1,T4,T7 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T16,T72 | Yes | T2,T16,T72 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T72 | Yes | T4,T16,T72 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T72 | Yes | T4,T16,T72 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T6,T7,T17 | Yes | T6,T7,T17 | INPUT |
ping_ok_o | Yes | Yes | T7,T17,T48 | Yes | T7,T17,T48 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T16 | Yes | T4,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T6,T17,T48 | Yes | T27,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T27,T224,T225 | Yes | T6,T17,T48 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T16,T69,T224 | Yes | T16,T69,T224 | INPUT |
ping_ok_o | Yes | Yes | T16,T69,T224 | Yes | T16,T69,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T44,T17,T26 | Yes | T44,T17,T26 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T69,T224 | Yes | T16,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T225 | Yes | T16,T69,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T15,T16,T72 | Yes | T15,T16,T72 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T7,T8 | Yes | T1,T7,T8 | INPUT |
ping_ok_o | Yes | Yes | T1,T7,T8 | Yes | T1,T7,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T224,T225,T49 | Yes | T224,T225,T49 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T224,T225,T49 | Yes | T224,T225,T49 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T8,T16,T17 | Yes | T8,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T16,T17,T69 | Yes | T16,T17,T69 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T29 | Yes | T4,T15,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T8,T16,T17 | Yes | T16,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T225 | Yes | T8,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T48,T74,T224 | Yes | T48,T74,T224 | INPUT |
ping_ok_o | Yes | Yes | T48,T74,T224 | Yes | T48,T74,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T17 | Yes | T4,T15,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T48,T74,T224 | Yes | T224,T225,T31 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T224,T225,T31 | Yes | T48,T74,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T46,T15 | Yes | T4,T46,T15 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T1,T4,T16 | Yes | T4,T16,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T224 | Yes | T1,T4,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T7,T8,T27 | Yes | T7,T8,T27 | INPUT |
ping_ok_o | Yes | Yes | T7,T8,T27 | Yes | T7,T8,T27 | OUTPUT |
integ_fail_o | Yes | Yes | T16,T17,T27 | Yes | T16,T17,T27 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T27,T224,T225 | Yes | T27,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T27,T224,T225 | Yes | T27,T224,T225 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T8,T16,T17 | Yes | T8,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T8,T16,T17 | Yes | T8,T16,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T16 | Yes | T2,T4,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T17,T9 | Yes | T16,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T225 | Yes | T16,T17,T9 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T16,T17,T69 | Yes | T16,T17,T69 | INPUT |
ping_ok_o | Yes | Yes | T16,T17,T69 | Yes | T16,T17,T69 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T16,T17 | Yes | T2,T16,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T17,T69 | Yes | T16,T17,T72 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T17,T72 | Yes | T16,T17,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T16,T17 | Yes | T1,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T1,T16,T17 | Yes | T1,T16,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T72,T110 | Yes | T4,T72,T110 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T17,T69 | Yes | T16,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T225 | Yes | T16,T17,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T73,T74 | Yes | T4,T73,T74 | INPUT |
ping_ok_o | Yes | Yes | T4,T73,T74 | Yes | T4,T73,T74 | OUTPUT |
integ_fail_o | Yes | Yes | T16,T17,T29 | Yes | T16,T17,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T74,T224 | Yes | T4,T74,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T74,T224 | Yes | T4,T74,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T6 | Yes | T1,T4,T6 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T14 | Yes | T2,T4,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T6,T16 | Yes | T4,T16,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T224 | Yes | T4,T6,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T14,T8,T16 | Yes | T14,T8,T16 | INPUT |
ping_ok_o | Yes | Yes | T14,T8,T16 | Yes | T14,T8,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T15 | Yes | T2,T4,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T16,T74 | Yes | T14,T16,T27 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T16,T27 | Yes | T14,T16,T74 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T17,T69 | Yes | T4,T17,T69 | INPUT |
ping_ok_o | Yes | Yes | T4,T17,T69 | Yes | T4,T17,T69 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T17 | Yes | T2,T14,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T69 | Yes | T4,T69,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T69,T224 | Yes | T4,T17,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T14,T8,T16 | Yes | T14,T8,T16 | INPUT |
ping_ok_o | Yes | Yes | T14,T8,T16 | Yes | T14,T8,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T48 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T16,T48 | Yes | T14,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T6,T16,T17 | Yes | T6,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T16,T17,T74 | Yes | T16,T17,T74 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T44,T29 | Yes | T4,T44,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T6,T16,T17 | Yes | T16,T74,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T74,T224 | Yes | T6,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T44,T14 | Yes | T2,T44,T14 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T1,T4,T16 | Yes | T1,T4,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T7 | Yes | T4,T14,T7 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T7 | Yes | T4,T14,T7 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T44 | Yes | T2,T4,T44 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T15,T72 | Yes | T2,T15,T72 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | INPUT |
ping_ok_o | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T26,T27 | Yes | T14,T26,T27 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T7 | Yes | T1,T4,T7 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T7 | Yes | T1,T4,T7 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T48 | Yes | T4,T17,T48 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T17,T48 | Yes | T4,T17,T48 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T17,T73,T27 | Yes | T17,T73,T27 | INPUT |
ping_ok_o | Yes | Yes | T17,T73,T27 | Yes | T17,T73,T27 | OUTPUT |
integ_fail_o | Yes | Yes | T15,T29,T26 | Yes | T15,T29,T26 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T17,T27,T224 | Yes | T17,T27,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T17,T27,T224 | Yes | T17,T27,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T8,T16 | Yes | T4,T8,T16 | INPUT |
ping_ok_o | Yes | Yes | T4,T8,T16 | Yes | T4,T8,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T16,T17 | Yes | T2,T16,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T74 | Yes | T4,T16,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T224 | Yes | T4,T16,T74 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T16 | Yes | T4,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T1,T4,T14 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T1,T4,T14 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T14,T17,T224 | Yes | T14,T17,T224 | INPUT |
ping_ok_o | Yes | Yes | T14,T17,T224 | Yes | T14,T17,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T17 | Yes | T14,T15,T17 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T17,T224 | Yes | T14,T224,T32 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T224,T32 | Yes | T14,T17,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T26 | Yes | T14,T15,T26 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T72 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T16,T72 | Yes | T14,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T74 | Yes | T4,T14,T74 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T74 | Yes | T4,T14,T74 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T74 | Yes | T4,T14,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T224 | Yes | T4,T14,T74 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T14,T69 | Yes | T1,T14,T69 | INPUT |
ping_ok_o | Yes | Yes | T1,T14,T69 | Yes | T1,T14,T69 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T44,T15 | Yes | T4,T44,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T69,T74 | Yes | T14,T69,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T69,T224 | Yes | T14,T69,T74 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T16,T17,T48 | Yes | T16,T17,T48 | INPUT |
ping_ok_o | Yes | Yes | T16,T17,T48 | Yes | T16,T17,T48 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T16 | Yes | T2,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T17,T48 | Yes | T16,T17,T27 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T17,T27 | Yes | T16,T17,T48 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T8,T17 | Yes | T4,T8,T17 | INPUT |
ping_ok_o | Yes | Yes | T4,T8,T17 | Yes | T4,T8,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T16 | Yes | T2,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T8,T17 | Yes | T4,T8,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T8,T224 | Yes | T4,T8,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T17,T72,T224 | Yes | T17,T72,T224 | INPUT |
ping_ok_o | Yes | Yes | T17,T72,T224 | Yes | T17,T72,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T16 | Yes | T4,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T17,T72,T224 | Yes | T17,T72,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T17,T72,T224 | Yes | T17,T72,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T7,T8 | Yes | T4,T7,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T7,T8 | Yes | T4,T7,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T15 | Yes | T2,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T17 | Yes | T4,T16,T17 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T17 | Yes | T4,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T17 | Yes | T1,T4,T17 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T17 | Yes | T1,T4,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T14 | Yes | T2,T4,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T48 | Yes | T4,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T224,T225 | Yes | T4,T17,T48 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T72,T9 | Yes | T4,T72,T9 | INPUT |
ping_ok_o | Yes | Yes | T4,T72,T27 | Yes | T4,T72,T27 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T16 | Yes | T4,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T72,T9 | Yes | T4,T72,T27 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T72,T27 | Yes | T4,T72,T9 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T8,T16,T224 | Yes | T8,T16,T224 | INPUT |
ping_ok_o | Yes | Yes | T8,T16,T224 | Yes | T8,T16,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T29,T49,T50 | Yes | T29,T49,T50 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T224,T32 | Yes | T16,T224,T32 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T32 | Yes | T16,T224,T32 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T16 | Yes | T2,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T224 | Yes | T4,T14,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T16,T74 | Yes | T1,T16,T74 | INPUT |
ping_ok_o | Yes | Yes | T1,T16,T74 | Yes | T1,T16,T74 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T14 | Yes | T2,T4,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T74,T27 | Yes | T16,T27,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T27,T224 | Yes | T16,T74,T27 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T17,T72 | Yes | T4,T17,T72 | INPUT |
ping_ok_o | Yes | Yes | T4,T17,T72 | Yes | T4,T17,T72 | OUTPUT |
integ_fail_o | Yes | Yes | T15,T16,T32 | Yes | T15,T16,T32 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T72 | Yes | T4,T17,T72 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T17,T72 | Yes | T4,T17,T72 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T8 | Yes | T1,T4,T8 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T8 | Yes | T1,T4,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T9 | Yes | T4,T224,T32 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T224,T32 | Yes | T4,T17,T9 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T17,T48 | Yes | T1,T17,T48 | INPUT |
ping_ok_o | Yes | Yes | T1,T17,T48 | Yes | T1,T17,T48 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T44 | Yes | T2,T4,T44 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T17,T48,T224 | Yes | T224,T225,T31 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T224,T225,T31 | Yes | T17,T48,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T8,T17 | Yes | T4,T8,T17 | INPUT |
ping_ok_o | Yes | Yes | T4,T8,T17 | Yes | T4,T8,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T224 | Yes | T4,T17,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T17,T224 | Yes | T4,T17,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T8 | Yes | T4,T14,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T17,T75 | Yes | T14,T17,T75 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T6,T14 | Yes | T1,T6,T14 | INPUT |
ping_ok_o | Yes | Yes | T1,T14,T8 | Yes | T1,T14,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T46,T15,T17 | Yes | T46,T15,T17 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T6,T14,T17 | Yes | T14,T72,T74 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T72,T74 | Yes | T6,T14,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T8,T16 | Yes | T1,T8,T16 | INPUT |
ping_ok_o | Yes | Yes | T1,T8,T16 | Yes | T1,T8,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T14,T15 | Yes | T2,T14,T15 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T224,T32 | Yes | T16,T224,T32 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T224,T32 | Yes | T16,T224,T32 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T16,T29 | Yes | T4,T16,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T15 | Yes | T4,T14,T15 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T48 | Yes | T4,T14,T48 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T48 | Yes | T4,T14,T48 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T29 | Yes | T4,T14,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T48 | Yes | T4,T14,T48 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T48 | Yes | T4,T14,T48 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T7,T16 | Yes | T4,T7,T16 | INPUT |
ping_ok_o | Yes | Yes | T4,T7,T16 | Yes | T4,T7,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T16 | Yes | T4,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T224 | Yes | T4,T16,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T224 | Yes | T4,T16,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T14,T16 | Yes | T1,T14,T16 | INPUT |
ping_ok_o | Yes | Yes | T1,T14,T16 | Yes | T1,T14,T16 | OUTPUT |
integ_fail_o | Yes | Yes | T29,T49,T50 | Yes | T29,T49,T50 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T14,T16,T17 | Yes | T14,T16,T48 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T14,T16,T48 | Yes | T14,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T14 | Yes | T2,T4,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T224 | Yes | T4,T14,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T16,T72,T9 | Yes | T16,T72,T9 | INPUT |
ping_ok_o | Yes | Yes | T16,T72,T224 | Yes | T16,T72,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T44,T14 | Yes | T4,T44,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T16,T72,T9 | Yes | T16,T72,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T16,T72,T224 | Yes | T16,T72,T9 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T15,T29 | Yes | T4,T15,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T224 | Yes | T4,T14,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T17,T69 | Yes | T4,T17,T69 | INPUT |
ping_ok_o | Yes | Yes | T4,T17,T69 | Yes | T4,T17,T69 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T16 | Yes | T14,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T17,T69 | Yes | T4,T72,T74 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T72,T74 | Yes | T4,T17,T69 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T16,T17 | Yes | T4,T16,T17 | INPUT |
ping_ok_o | Yes | Yes | T4,T16,T17 | Yes | T4,T16,T17 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T17 | Yes | T4,T16,T74 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T74 | Yes | T4,T16,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T8,T48,T74 | Yes | T8,T48,T74 | INPUT |
ping_ok_o | Yes | Yes | T8,T48,T74 | Yes | T8,T48,T74 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T4,T14 | Yes | T2,T4,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T48,T74,T224 | Yes | T74,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T74,T224,T225 | Yes | T48,T74,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T14,T7 | Yes | T4,T14,T7 | INPUT |
ping_ok_o | Yes | Yes | T4,T14,T7 | Yes | T4,T14,T7 | OUTPUT |
integ_fail_o | Yes | Yes | T4,T44,T14 | Yes | T4,T44,T14 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T16 | Yes | T4,T14,T16 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | INPUT |
ping_ok_o | Yes | Yes | T1,T4,T14 | Yes | T1,T4,T14 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T16 | Yes | T14,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T14,T17 | Yes | T4,T14,T17 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T7,T8 | Yes | T4,T7,T8 | INPUT |
ping_ok_o | Yes | Yes | T4,T7,T8 | Yes | T4,T7,T8 | OUTPUT |
integ_fail_o | Yes | Yes | T2,T15,T29 | Yes | T2,T15,T29 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T16,T74 | Yes | T4,T16,T224 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T16,T224 | Yes | T4,T16,T74 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T2,T17,T224 | Yes | T2,T17,T224 | INPUT |
ping_ok_o | Yes | Yes | T2,T17,T224 | Yes | T2,T17,T224 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T27 | Yes | T14,T15,T27 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T2,T17,T224 | Yes | T224,T225,T95 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T224,T225,T95 | Yes | T2,T17,T224 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 13 | 13 | 100.00 |
Total Bits | 32 | 32 | 100.00 |
Total Bits 0->1 | 16 | 16 | 100.00 |
Total Bits 1->0 | 16 | 16 | 100.00 |
Ports | 13 | 13 | 100.00 |
Port Bits | 32 | 32 | 100.00 |
Port Bits 0->1 | 16 | 16 | 100.00 |
Port Bits 1->0 | 16 | 16 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T4,T14 | Yes | T1,T2,T3 | INPUT |
init_trig_i[3:0] | Yes | Yes | T1,T2,T4 | Yes | T1,T2,T3 | INPUT |
ping_req_i | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | INPUT |
ping_ok_o | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
integ_fail_o | Yes | Yes | T14,T15,T16 | Yes | T14,T15,T16 | OUTPUT |
alert_o | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_o.ack_p | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
alert_rx_o.ping_n | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
alert_rx_o.ping_p | Yes | Yes | T4,T224,T225 | Yes | T4,T224,T225 | OUTPUT |
alert_tx_i.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_tx_i.alert_p | Yes | Yes | T2,T3,T5 | Yes | T1,T2,T3 | INPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |