Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T5
1	0	1	Covered	T1,T2,T18
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T5,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T4,T20
0	1	Covered	T4,T20,T21
1	0	Covered	T15,T16,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T4,T20
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T20
1	0	Covered	T4,T24,T25
1	1	Covered	T4,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T18

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T5,T4,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T5,T4,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T26,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T15,T16
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T29,T26,T30
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T15,T16,T26
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T5,T4,T20
TimeoutSt->Phase0St	172	Covered	T4,T20,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T28,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T15,T16
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T30,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T26,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1158	0	0
CheckAccumTrig0_A	2147483647	2539	0	0
CheckAccumTrig1_A	2147483647	107	0	0
CheckClr_A	2147483647	1213	0	0
CheckEn_A	2147483647	1186089664	0	0
CheckPhase0_A	2147483647	2826	0	0
CheckPhase1_A	2147483647	2756	0	0
CheckPhase2_A	2147483647	2687	0	0
CheckPhase3_A	2147483647	2637	0	0
CheckTimeout0_A	2147483647	7399	0	0
CheckTimeoutSt1_A	2147483647	810364	0	0
CheckTimeoutSt2_A	2147483647	7053	0	0
CheckTimeoutStTrig_A	2147483647	228	0	0
ErrorStAllEscAsserted_A	2147483647	5692	0	0
ErrorStIsTerminal_A	2147483647	4732	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158	0	0
T11	169280	300	0	0
T12	0	326	0	0
T13	0	142	0	0
T33	0	134	0	0
T34	0	256	0	0
T35	1685840	0	0	0
T36	2268416	0	0	0
T37	1448612	0	0	0
T38	2982236	0	0	0
T39	76596	0	0	0
T40	141608	0	0	0
T41	566252	0	0	0
T42	1095528	0	0	0
T43	167608	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2539	0	0
T1	984808	3	0	0
T2	3965208	12	0	0
T3	132912	1	0	0
T4	2044876	10	0	0
T5	476456	1	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T14	0	9	0	0
T15	0	17	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	307276	2	0	0
T19	38032	0	0	0
T20	160528	0	0	0
T21	137140	0	0	0
T22	1100316	3	0	0
T44	46378	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	9	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107	0	0
T8	985106	0	0	0
T9	788489	0	0	0
T15	892648	5	0	0
T16	1075470	1	0	0
T17	1139262	0	0	0
T23	95848	1	0	0
T26	391464	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	715428	0	0	0
T30	89749	0	0	0
T32	0	1	0	0
T48	774822	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	6	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	53944	0	0	0
T65	251068	0	0	0
T66	246162	0	0	0
T67	15267	0	0	0
T68	10536	0	0	0
T69	733158	0	0	0
T70	18479	0	0	0
T71	28896	0	0	0
T72	123044	0	0	0
T73	305605	0	0	0
T74	348067	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1213	0	0
T1	492404	2	0	0
T2	1982604	5	0	0
T3	66456	0	0	0
T4	1022438	2	0	0
T5	238228	0	0	0
T6	835254	0	0	0
T7	330918	2	0	0
T14	380590	1	0	0
T15	0	13	0	0
T16	0	10	0	0
T17	0	2	0	0
T18	153638	0	0	0
T19	19016	0	0	0
T20	120396	1	0	0
T21	137140	1	0	0
T22	1100316	0	0	0
T23	0	1	0	0
T26	0	13	0	0
T29	0	13	0	0
T32	0	1	0	0
T44	69567	1	0	0
T45	48926	0	0	0
T46	7258	1	0	0
T47	20871	7	0	0
T48	0	1	0	0
T69	0	3	0	0
T72	0	6	0	0
T75	0	1	0	0
T76	2472	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1186089664	0	0
T1	1969616	998727	0	0
T2	3965208	1804523	0	0
T3	132912	105238	0	0
T4	2044876	1435956	0	0
T5	476456	244257	0	0
T18	307276	162998	0	0
T19	38032	28980	0	0
T20	160528	69175	0	0
T21	137140	72888	0	0
T22	1100316	312763	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2826	0	0
T1	984808	3	0	0
T2	3965208	12	0	0
T3	132912	1	0	0
T4	2044876	12	0	0
T5	476456	1	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	0	9	0	0
T15	0	24	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	307276	2	0	0
T19	38032	0	0	0
T20	160528	1	0	0
T21	137140	1	0	0
T22	1100316	3	0	0
T44	46378	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	9	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2756	0	0
T1	984808	3	0	0
T2	3965208	12	0	0
T3	132912	1	0	0
T4	2044876	11	0	0
T5	476456	1	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	0	9	0	0
T15	0	23	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	307276	2	0	0
T19	38032	0	0	0
T20	160528	1	0	0
T21	137140	1	0	0
T22	1100316	3	0	0
T44	46378	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	9	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2687	0	0
T1	984808	3	0	0
T2	3965208	12	0	0
T3	132912	1	0	0
T4	2044876	11	0	0
T5	476456	1	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	0	9	0	0
T15	0	23	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	307276	2	0	0
T19	38032	0	0	0
T20	160528	1	0	0
T21	137140	1	0	0
T22	1100316	3	0	0
T44	46378	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	9	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2637	0	0
T1	984808	3	0	0
T2	3965208	12	0	0
T3	132912	1	0	0
T4	2044876	11	0	0
T5	476456	1	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	0	9	0	0
T15	0	22	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	307276	2	0	0
T19	38032	0	0	0
T20	160528	1	0	0
T21	137140	1	0	0
T22	1100316	3	0	0
T44	46378	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	9	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7399	0	0
T4	2044876	15	0	0
T5	119114	3	0	0
T6	1670508	0	0	0
T14	570885	19	0	0
T15	0	12	0	0
T16	0	17	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	160528	13	0	0
T21	137140	8	0	0
T22	1100316	0	0	0
T23	0	5	0	0
T26	0	9	0	0
T27	0	3	0	0
T29	0	213	0	0
T44	92756	0	0	0
T45	97852	0	0	0
T46	10887	0	0	0
T66	0	20	0	0
T72	0	6	0	0
T76	3708	0	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	810364	0	0
T4	2044876	2134	0	0
T5	119114	465	0	0
T6	1670508	0	0	0
T14	570885	2592	0	0
T15	0	2451	0	0
T16	0	1878	0	0
T17	0	26	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	160528	1649	0	0
T21	137140	1034	0	0
T22	1100316	0	0	0
T23	0	333	0	0
T26	0	872	0	0
T27	0	200	0	0
T29	0	13558	0	0
T44	92756	0	0	0
T45	97852	0	0	0
T46	10887	0	0	0
T66	0	2617	0	0
T72	0	669	0	0
T76	3708	0	0	0
T77	0	238	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7053	0	0
T4	2044876	13	0	0
T5	119114	3	0	0
T6	1670508	0	0	0
T14	570885	19	0	0
T15	0	3	0	0
T16	0	14	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	160528	12	0	0
T21	137140	7	0	0
T22	1100316	0	0	0
T23	0	4	0	0
T26	0	10	0	0
T27	0	2	0	0
T29	0	210	0	0
T32	0	11	0	0
T44	92756	0	0	0
T45	97852	0	0	0
T46	10887	0	0	0
T66	0	20	0	0
T72	0	7	0	0
T76	3708	0	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	228	0	0
T4	511219	2	0	0
T6	835254	0	0	0
T7	165459	0	0	0
T8	492553	0	0	0
T14	380590	0	0	0
T15	446324	4	0	0
T16	358490	1	0	0
T17	379754	0	0	0
T20	80264	1	0	0
T21	68570	1	0	0
T22	550158	0	0	0
T26	0	3	0	0
T28	0	1	0	0
T29	0	3	0	0
T35	0	3	0	0
T44	46378	0	0	0
T45	48926	0	0	0
T46	7258	0	0	0
T48	258274	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T53	0	4	0	0
T64	26972	0	0	0
T65	125534	0	0	0
T66	82054	0	0	0
T67	5089	0	0	0
T68	3512	0	0	0
T72	0	3	0	0
T76	2472	0	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	4	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5692	0	0
T11	169280	1410	0	0
T12	0	1453	0	0
T13	0	674	0	0
T33	0	700	0	0
T34	0	1455	0	0
T35	1685840	0	0	0
T36	2268416	0	0	0
T37	1448612	0	0	0
T38	2982236	0	0	0
T39	76596	0	0	0
T40	141608	0	0	0
T41	566252	0	0	0
T42	1095528	0	0	0
T43	167608	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4732	0	0
T11	169280	1170	0	0
T12	0	1213	0	0
T13	0	554	0	0
T33	0	580	0	0
T34	0	1215	0	0
T35	1685840	0	0	0
T36	2268416	0	0	0
T37	1448612	0	0	0
T38	2982236	0	0	0
T39	76596	0	0	0
T40	141608	0	0	0
T41	566252	0	0	0
T42	1095528	0	0	0
T43	167608	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1969616	1969588	0	0
T2	3965208	3964032	0	0
T3	132912	132692	0	0
T4	2044876	2044756	0	0
T5	476456	476108	0	0
T18	307276	307028	0	0
T19	38032	37824	0	0
T20	160528	160144	0	0
T21	137140	136764	0	0
T22	1100316	1099948	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1969616	1969588	0	0
T2	3965208	3964032	0	0
T3	132912	132692	0	0
T4	2044876	2044756	0	0
T5	476456	476108	0	0
T18	307276	307028	0	0
T19	38032	37824	0	0
T20	160528	160144	0	0
T21	137140	136764	0	0
T22	1100316	1099948	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T18,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T18,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T20
1	0	1	Covered	T18,T4,T22
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T4,T20,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T21
0	1	Covered	T20,T15,T29
1	0	Covered	T15,T16,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T20,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T21
1	0	Not Covered
1	1	Covered	T20,T15,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T4,T20
1	Covered	T2,T14,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T4
1	Covered	T22,T44,T46

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T20
1	Covered	T4,T15,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T22
1	Covered	T18,T20,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T18,T4,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T20,T22,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T22,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T20,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T18,T4
Phase1St	198	Covered	T2,T18,T4
Phase2St	215	Covered	T2,T18,T4
Phase3St	233	Covered	T2,T18,T4
TerminalSt	249	Covered	T2,T18,T4
TimeoutSt	159	Covered	T4,T20,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T18,T4
IdleSt->TimeoutSt	159	Covered	T4,T20,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T83,T86,T59
Phase0St->Phase1St	198	Covered	T2,T18,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T16,T77
Phase1St->Phase2St	215	Covered	T2,T18,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T27,T50
Phase2St->Phase3St	233	Covered	T2,T18,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T57,T87
Phase3St->TerminalSt	249	Covered	T2,T18,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T20,T21
TimeoutSt->Phase0St	172	Covered	T20,T15,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T15,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T83,T59,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T18,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T18,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T16,T77
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T18,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T18,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T50,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T18,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T18,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T57,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T18,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T18,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T14,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T18,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	673875608	315	0	0
CheckAccumTrig0_A	673875608	585	0	0
CheckAccumTrig1_A	673875608	25	0	0
CheckClr_A	673875608	292	0	0
CheckEn_A	673714800	276315051	0	0
CheckPhase0_A	673875608	657	0	0
CheckPhase1_A	673875608	642	0	0
CheckPhase2_A	673875608	632	0	0
CheckPhase3_A	673875608	624	0	0
CheckTimeout0_A	673875608	1830	0	0
CheckTimeoutSt1_A	673875608	206180	0	0
CheckTimeoutSt2_A	673875608	1748	0	0
CheckTimeoutStTrig_A	673875608	56	0	0
ErrorStAllEscAsserted_A	673875608	1461	0	0
ErrorStIsTerminal_A	673875608	1221	0	0
EscStateOut_A	673713549	673641466	0	0
u_state_regs_A	673875608	673700503	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	315	0	0
T11	42320	81	0	0
T12	0	67	0	0
T13	0	55	0	0
T33	0	42	0	0
T34	0	70	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	585	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T8	0	1	0	0
T14	0	3	0	0
T15	0	6	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	23189	1	0	0
T46	0	1	0	0
T47	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	25	0	0
T8	492553	0	0	0
T15	446324	2	0	0
T16	358490	1	0	0
T17	379754	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T48	258274	0	0	0
T57	0	1	0	0
T64	26972	0	0	0
T65	125534	0	0	0
T66	82054	0	0	0
T67	5089	0	0	0
T68	3512	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	292	0	0
T6	417627	0	0	0
T7	165459	0	0	0
T14	190295	1	0	0
T15	0	5	0	0
T16	0	7	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T26	0	7	0	0
T29	0	3	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	1	0	0
T47	0	5	0	0
T72	0	1	0	0
T75	0	1	0	0
T76	1236	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673714800	276315051	0	0
T1	492404	491806	0	0
T2	991302	659622	0	0
T3	33228	33172	0	0
T4	511219	452810	0	0
T5	119114	119026	0	0
T18	76819	613	0	0
T19	9508	9455	0	0
T20	40132	7866	0	0
T21	34285	21391	0	0
T22	275079	31666	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	657	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T14	0	3	0	0
T15	0	10	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	23189	1	0	0
T46	0	1	0	0
T47	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	642	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T14	0	3	0	0
T15	0	9	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	23189	1	0	0
T46	0	1	0	0
T47	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	632	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T14	0	3	0	0
T15	0	9	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	23189	1	0	0
T46	0	1	0	0
T47	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	624	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T14	0	3	0	0
T15	0	9	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	23189	1	0	0
T46	0	1	0	0
T47	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1830	0	0
T4	511219	4	0	0
T6	417627	0	0	0
T14	190295	0	0	0
T15	0	5	0	0
T16	0	1	0	0
T20	40132	5	0	0
T21	34285	2	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T27	0	2	0	0
T29	0	204	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T72	0	5	0	0
T76	1236	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	206180	0	0
T4	511219	617	0	0
T6	417627	0	0	0
T14	190295	0	0	0
T15	0	656	0	0
T16	0	24	0	0
T20	40132	606	0	0
T21	34285	246	0	0
T22	275079	0	0	0
T23	0	121	0	0
T26	0	142	0	0
T27	0	81	0	0
T29	0	12627	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T72	0	616	0	0
T76	1236	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1748	0	0
T4	511219	4	0	0
T6	417627	0	0	0
T14	190295	0	0	0
T15	0	1	0	0
T20	40132	4	0	0
T21	34285	2	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T27	0	1	0	0
T29	0	203	0	0
T32	0	1	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T72	0	4	0	0
T76	1236	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	56	0	0
T6	417627	0	0	0
T7	165459	0	0	0
T14	190295	0	0	0
T15	0	2	0	0
T20	40132	1	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T29	0	1	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T49	0	1	0	0
T53	0	1	0	0
T72	0	1	0	0
T76	1236	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T83	0	2	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1461	0	0
T11	42320	368	0	0
T12	0	388	0	0
T13	0	172	0	0
T33	0	171	0	0
T34	0	362	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1221	0	0
T11	42320	308	0	0
T12	0	328	0	0
T13	0	142	0	0
T33	0	141	0	0
T34	0	302	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673713549	673641466	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	673700503	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T20
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T20

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T4
1	0	1	Covered	T2,T44,T14
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T4,T20,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T21
0	1	Covered	T4,T21,T26
1	0	Covered	T16,T95,T96

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T20,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T95,T96

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T21
1	0	Not Covered
1	1	Covered	T4,T21,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T21,T6
1	Covered	T2,T4,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T4,T21,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T15,T48,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T4,T6,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T21,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T21,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T21
Phase1St	198	Covered	T2,T4,T21
Phase2St	215	Covered	T2,T4,T21
Phase3St	233	Covered	T2,T4,T21
TerminalSt	249	Covered	T2,T4,T21
TimeoutSt	159	Covered	T4,T20,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T6
IdleSt->TimeoutSt	159	Covered	T4,T20,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T52,T97,T98
Phase0St->Phase1St	198	Covered	T2,T4,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T16,T99,T57
Phase1St->Phase2St	215	Covered	T2,T4,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T100,T31,T101
Phase2St->Phase3St	233	Covered	T2,T4,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T49,T28,T102
Phase3St->TerminalSt	249	Covered	T2,T4,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T20,T21
TimeoutSt->Phase0St	172	Covered	T4,T21,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T52,T97,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T99,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T100,T31,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T28,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T7,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	673875608	252	0	0
CheckAccumTrig0_A	673875608	520	0	0
CheckAccumTrig1_A	673875608	19	0	0
CheckClr_A	673875608	226	0	0
CheckEn_A	673714800	311549821	0	0
CheckPhase0_A	673875608	586	0	0
CheckPhase1_A	673875608	572	0	0
CheckPhase2_A	673875608	554	0	0
CheckPhase3_A	673875608	545	0	0
CheckTimeout0_A	673875608	2206	0	0
CheckTimeoutSt1_A	673875608	236189	0	0
CheckTimeoutSt2_A	673875608	2128	0	0
CheckTimeoutStTrig_A	673875608	55	0	0
ErrorStAllEscAsserted_A	673875608	1408	0	0
ErrorStIsTerminal_A	673875608	1168	0	0
EscStateOut_A	673713549	673641466	0	0
u_state_regs_A	673875608	673700503	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	252	0	0
T11	42320	63	0	0
T12	0	89	0	0
T13	0	31	0	0
T33	0	13	0	0
T34	0	56	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	520	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	2	0	0
T5	119114	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T44	23189	0	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	19	0	0
T16	358490	1	0	0
T17	379754	0	0	0
T23	47924	0	0	0
T26	195732	0	0	0
T29	715428	0	0	0
T48	258274	0	0	0
T66	82054	0	0	0
T67	5089	0	0	0
T68	3512	0	0	0
T69	366579	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	226	0	0
T6	417627	0	0	0
T7	165459	2	0	0
T14	190295	0	0	0
T16	0	1	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T26	0	1	0	0
T29	0	3	0	0
T32	0	1	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T47	20871	0	0	0
T69	0	1	0	0
T72	0	2	0	0
T76	1236	0	0	0
T110	0	1	0	0
T111	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673714800	311549821	0	0
T1	492404	491805	0	0
T2	991302	654534	0	0
T3	33228	33172	0	0
T4	511219	407952	0	0
T5	119114	3139	0	0
T18	76819	76756	0	0
T19	9508	9455	0	0
T20	40132	20895	0	0
T21	34285	16609	0	0
T22	275079	274986	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	586	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	3	0	0
T5	119114	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T44	23189	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	572	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	3	0	0
T5	119114	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T44	23189	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	554	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	3	0	0
T5	119114	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T44	23189	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	545	0	0
T2	991302	1	0	0
T3	33228	0	0	0
T4	511219	3	0	0
T5	119114	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T44	23189	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	2206	0	0
T4	511219	2	0	0
T6	417627	0	0	0
T14	190295	4	0	0
T15	0	1	0	0
T16	0	15	0	0
T17	0	1	0	0
T20	40132	2	0	0
T21	34285	3	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T66	0	8	0	0
T76	1236	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	236189	0	0
T4	511219	245	0	0
T6	417627	0	0	0
T14	190295	922	0	0
T15	0	643	0	0
T16	0	1850	0	0
T17	0	26	0	0
T20	40132	285	0	0
T21	34285	364	0	0
T22	275079	0	0	0
T23	0	45	0	0
T26	0	320	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T66	0	1016	0	0
T76	1236	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	2128	0	0
T4	511219	1	0	0
T6	417627	0	0	0
T14	190295	4	0	0
T15	0	1	0	0
T16	0	14	0	0
T17	0	1	0	0
T20	40132	2	0	0
T21	34285	2	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	4	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T66	0	8	0	0
T76	1236	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	55	0	0
T4	511219	1	0	0
T6	417627	0	0	0
T14	190295	0	0	0
T20	40132	0	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T76	1236	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1408	0	0
T11	42320	374	0	0
T12	0	367	0	0
T13	0	169	0	0
T33	0	151	0	0
T34	0	347	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1168	0	0
T11	42320	314	0	0
T12	0	307	0	0
T13	0	139	0	0
T33	0	121	0	0
T34	0	287	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673713549	673641466	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	673700503	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T5
1	0	1	Covered	T1,T4,T22
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T5,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T4,T20
0	1	Covered	T15,T16,T29
1	0	Covered	T23,T49,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T4,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T49,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T20
1	0	Covered	T25
1	1	Covered	T15,T16,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T4,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T14,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T5,T4,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T5,T4,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T31,T57
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T113,T49
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T30,T114
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T32,T113
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T4,T20
TimeoutSt->Phase0St	172	Covered	T15,T16,T29

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T29
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T31,T57
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T113,T49
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T30,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T32,T113
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T47,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	673875608	342	0	0
CheckAccumTrig0_A	673875608	915	0	0
CheckAccumTrig1_A	673875608	43	0	0
CheckClr_A	673875608	464	0	0
CheckEn_A	673714800	281224340	0	0
CheckPhase0_A	673875608	996	0	0
CheckPhase1_A	673875608	973	0	0
CheckPhase2_A	673875608	942	0	0
CheckPhase3_A	673875608	916	0	0
CheckTimeout0_A	673875608	2008	0	0
CheckTimeoutSt1_A	673875608	196594	0	0
CheckTimeoutSt2_A	673875608	1905	0	0
CheckTimeoutStTrig_A	673875608	56	0	0
ErrorStAllEscAsserted_A	673875608	1427	0	0
ErrorStIsTerminal_A	673875608	1187	0	0
EscStateOut_A	673713549	673641466	0	0
u_state_regs_A	673875608	673700503	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	342	0	0
T11	42320	81	0	0
T12	0	103	0	0
T13	0	34	0	0
T33	0	56	0	0
T34	0	68	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	915	0	0
T1	492404	1	0	0
T2	991302	7	0	0
T3	33228	1	0	0
T4	511219	4	0	0
T5	119114	1	0	0
T14	0	5	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	43	0	0
T9	788489	0	0	0
T23	47924	1	0	0
T26	195732	0	0	0
T28	0	1	0	0
T30	89749	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	4	0	0
T59	0	1	0	0
T69	366579	0	0	0
T70	18479	0	0	0
T71	28896	0	0	0
T72	123044	0	0	0
T73	305605	0	0	0
T74	348067	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	464	0	0
T2	991302	5	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T29	0	6	0	0
T44	23189	0	0	0
T47	0	2	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673714800	281224340	0	0
T1	492404	12441	0	0
T2	991302	452955	0	0
T3	33228	5722	0	0
T4	511219	196319	0	0
T5	119114	3066	0	0
T18	76819	72264	0	0
T19	9508	615	0	0
T20	40132	23327	0	0
T21	34285	20262	0	0
T22	275079	3043	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	996	0	0
T1	492404	1	0	0
T2	991302	7	0	0
T3	33228	1	0	0
T4	511219	4	0	0
T5	119114	1	0	0
T14	0	5	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	973	0	0
T1	492404	1	0	0
T2	991302	7	0	0
T3	33228	1	0	0
T4	511219	3	0	0
T5	119114	1	0	0
T14	0	5	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	942	0	0
T1	492404	1	0	0
T2	991302	7	0	0
T3	33228	1	0	0
T4	511219	3	0	0
T5	119114	1	0	0
T14	0	5	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	916	0	0
T1	492404	1	0	0
T2	991302	7	0	0
T3	33228	1	0	0
T4	511219	3	0	0
T5	119114	1	0	0
T14	0	5	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	2008	0	0
T4	511219	4	0	0
T5	119114	3	0	0
T6	417627	0	0	0
T14	0	14	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	3	0	0
T21	34285	2	0	0
T22	275079	0	0	0
T23	0	2	0	0
T29	0	9	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T66	0	12	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	196594	0	0
T4	511219	629	0	0
T5	119114	465	0	0
T6	417627	0	0	0
T14	0	1205	0	0
T15	0	805	0	0
T16	0	4	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	371	0	0
T21	34285	281	0	0
T22	275079	0	0	0
T23	0	46	0	0
T29	0	931	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T66	0	1601	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1905	0	0
T4	511219	4	0	0
T5	119114	3	0	0
T6	417627	0	0	0
T14	0	14	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	3	0	0
T21	34285	2	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	3	0	0
T29	0	7	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T66	0	12	0	0
T72	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	56	0	0
T8	492553	0	0	0
T15	446324	2	0	0
T16	358490	1	0	0
T17	379754	0	0	0
T26	0	1	0	0
T29	0	2	0	0
T48	258274	0	0	0
T53	0	1	0	0
T64	26972	0	0	0
T65	125534	0	0	0
T66	82054	0	0	0
T67	5089	0	0	0
T68	3512	0	0	0
T72	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1427	0	0
T11	42320	340	0	0
T12	0	354	0	0
T13	0	149	0	0
T33	0	195	0	0
T34	0	389	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1187	0	0
T11	42320	280	0	0
T12	0	294	0	0
T13	0	119	0	0
T33	0	165	0	0
T34	0	329	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673713549	673641466	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	673700503	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T20
1	0	1	Covered	T2,T18,T22
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T4,T20,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T21
0	1	Covered	T4,T26,T72
1	0	Covered	T15,T50,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T20,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T50,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T21
1	0	Covered	T4,T24
1	1	Covered	T4,T26,T72

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T2,T4,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T4,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T2,T4,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T4
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T18,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T18,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T18
Phase1St	198	Covered	T1,T2,T18
Phase2St	215	Covered	T1,T2,T18
Phase3St	233	Covered	T1,T2,T18
TerminalSt	249	Covered	T1,T2,T18
TimeoutSt	159	Covered	T4,T20,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T18
IdleSt->TimeoutSt	159	Covered	T4,T20,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T115,T89,T81
Phase1St->Phase2St	215	Covered	T1,T2,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T103,T57,T116
Phase2St->Phase3St	233	Covered	T1,T2,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T117,T118
Phase3St->TerminalSt	249	Covered	T1,T2,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T20,T21
TimeoutSt->Phase0St	172	Covered	T4,T15,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T15,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T28,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T115,T89,T81
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T103,T57,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T117,T118,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	673875608	249	0	0
CheckAccumTrig0_A	673875608	519	0	0
CheckAccumTrig1_A	673875608	20	0	0
CheckClr_A	673875608	231	0	0
CheckEn_A	673714800	317000452	0	0
CheckPhase0_A	673875608	587	0	0
CheckPhase1_A	673875608	569	0	0
CheckPhase2_A	673875608	559	0	0
CheckPhase3_A	673875608	552	0	0
CheckTimeout0_A	673875608	1355	0	0
CheckTimeoutSt1_A	673875608	171401	0	0
CheckTimeoutSt2_A	673875608	1272	0	0
CheckTimeoutStTrig_A	673875608	61	0	0
ErrorStAllEscAsserted_A	673875608	1396	0	0
ErrorStIsTerminal_A	673875608	1156	0	0
EscStateOut_A	673713549	673641466	0	0
u_state_regs_A	673875608	673700503	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	249	0	0
T11	42320	75	0	0
T12	0	67	0	0
T13	0	22	0	0
T33	0	23	0	0
T34	0	62	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	519	0	0
T1	492404	2	0	0
T2	991302	3	0	0
T3	33228	0	0	0
T4	511219	3	0	0
T5	119114	0	0	0
T8	0	1	0	0
T15	0	7	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	20	0	0
T8	492553	0	0	0
T15	446324	3	0	0
T16	358490	0	0	0
T17	379754	0	0	0
T48	258274	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	26972	0	0	0
T65	125534	0	0	0
T66	82054	0	0	0
T67	5089	0	0	0
T68	3512	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	231	0	0
T1	492404	2	0	0
T2	991302	0	0	0
T3	33228	0	0	0
T4	511219	1	0	0
T5	119114	0	0	0
T15	0	6	0	0
T17	0	1	0	0
T18	76819	0	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T26	0	3	0	0
T29	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T69	0	1	0	0
T72	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673714800	317000452	0	0
T1	492404	2675	0	0
T2	991302	37412	0	0
T3	33228	33172	0	0
T4	511219	378875	0	0
T5	119114	119026	0	0
T18	76819	13365	0	0
T19	9508	9455	0	0
T20	40132	17087	0	0
T21	34285	14626	0	0
T22	275079	3068	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	587	0	0
T1	492404	2	0	0
T2	991302	3	0	0
T3	33228	0	0	0
T4	511219	4	0	0
T5	119114	0	0	0
T8	0	1	0	0
T15	0	10	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	569	0	0
T1	492404	2	0	0
T2	991302	3	0	0
T3	33228	0	0	0
T4	511219	4	0	0
T5	119114	0	0	0
T8	0	1	0	0
T15	0	10	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	559	0	0
T1	492404	2	0	0
T2	991302	3	0	0
T3	33228	0	0	0
T4	511219	4	0	0
T5	119114	0	0	0
T8	0	1	0	0
T15	0	10	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	552	0	0
T1	492404	2	0	0
T2	991302	3	0	0
T3	33228	0	0	0
T4	511219	4	0	0
T5	119114	0	0	0
T8	0	1	0	0
T15	0	9	0	0
T18	76819	1	0	0
T19	9508	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1355	0	0
T4	511219	5	0	0
T6	417627	0	0	0
T14	190295	1	0	0
T15	0	4	0	0
T20	40132	3	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T27	0	1	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T72	0	1	0	0
T76	1236	0	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	171401	0	0
T4	511219	643	0	0
T6	417627	0	0	0
T14	190295	465	0	0
T15	0	347	0	0
T20	40132	387	0	0
T21	34285	143	0	0
T22	275079	0	0	0
T23	0	121	0	0
T26	0	410	0	0
T27	0	119	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T72	0	53	0	0
T76	1236	0	0	0
T77	0	238	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1272	0	0
T4	511219	4	0	0
T6	417627	0	0	0
T14	190295	1	0	0
T15	0	1	0	0
T20	40132	3	0	0
T21	34285	1	0	0
T22	275079	0	0	0
T23	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	0	10	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T76	1236	0	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	61	0	0
T4	511219	1	0	0
T6	417627	0	0	0
T14	190295	0	0	0
T20	40132	0	0	0
T21	34285	0	0	0
T22	275079	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T35	0	2	0	0
T44	23189	0	0	0
T45	24463	0	0	0
T46	3629	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T72	0	1	0	0
T76	1236	0	0	0
T82	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1396	0	0
T11	42320	328	0	0
T12	0	344	0	0
T13	0	184	0	0
T33	0	183	0	0
T34	0	357	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	1156	0	0
T11	42320	268	0	0
T12	0	284	0	0
T13	0	154	0	0
T33	0	153	0	0
T34	0	297	0	0
T35	421460	0	0	0
T36	567104	0	0	0
T37	362153	0	0	0
T38	745559	0	0	0
T39	19149	0	0	0
T40	35402	0	0	0
T41	141563	0	0	0
T42	273882	0	0	0
T43	41902	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673713549	673641466	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673875608	673700503	0	0
T1	492404	492397	0	0
T2	991302	991008	0	0
T3	33228	33173	0	0
T4	511219	511189	0	0
T5	119114	119027	0	0
T18	76819	76757	0	0
T19	9508	9456	0	0
T20	40132	40036	0	0
T21	34285	34191	0	0
T22	275079	274987	0	0