Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T52,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15731	0	0
DisabledNoTrigBkwd_A	2147483647	831188	0	0
DisabledNoTrigFwd_A	2147483647	1503471613	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15731	0	0
T22	1467	665	0	0
T52	0	786	0	0
T93	108476	0	0	0
T110	138673	0	0	0
T205	0	772	0	0
T206	0	650	0	0
T207	0	641	0	0
T208	0	1487	0	0
T209	0	405	0	0
T210	3439	1029	0	0
T211	0	980	0	0
T212	3655	1224	0	0
T213	0	590	0	0
T214	0	886	0	0
T215	0	941	0	0
T216	0	956	0	0
T217	0	880	0	0
T218	0	430	0	0
T219	0	825	0	0
T220	0	392	0	0
T221	0	424	0	0
T222	0	768	0	0
T223	31727	0	0	0
T224	46645	0	0	0
T225	88073	0	0	0
T226	15967	0	0	0
T227	115751	0	0	0
T228	17372	0	0	0
T229	39151	0	0	0
T230	875362	0	0	0
T231	518773	0	0	0
T232	7709	0	0	0
T233	456860	0	0	0
T234	163015	0	0	0
T235	416049	0	0	0
T236	398343	0	0	0
T237	265344	0	0	0
T238	18305	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	831188	0	0
T1	548889	114	0	0
T2	658424	1899	0	0
T3	133884	79	0	0
T4	1877744	4440	0	0
T5	0	1884	0	0
T6	0	895	0	0
T8	0	1	0	0
T16	1010664	442	0	0
T17	305372	81	0	0
T18	227816	25	0	0
T19	25304	5	0	0
T20	76672	26	0	0
T21	765940	220	0	0
T22	1467	32	0	0
T27	0	644	0	0
T28	0	2	0	0
T29	0	23	0	0
T52	0	10	0	0
T53	0	65	0	0
T54	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1503471613	0	0
T1	731852	205548	0	0
T2	658424	499658	0	0
T3	133884	43428	0	0
T4	1877744	1002622	0	0
T16	1010664	828001	0	0
T17	305372	238726	0	0
T18	227816	133550	0	0
T19	25304	13176	0	0
T20	76672	27095	0	0
T21	765940	398579	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T216
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674783191	1985	0	0
DisabledNoTrigBkwd_A	674783191	224390	0	0
DisabledNoTrigFwd_A	674783191	355579953	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1985	0	0
T93	108476	0	0	0
T110	138673	0	0	0
T210	3439	1029	0	0
T216	0	956	0	0
T223	31727	0	0	0
T224	46645	0	0	0
T225	88073	0	0	0
T226	15967	0	0	0
T227	115751	0	0	0
T228	17372	0	0	0
T229	39151	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	224390	0	0
T2	164606	1899	0	0
T3	33471	26	0	0
T4	469436	0	0	0
T5	0	2	0	0
T16	252666	51	0	0
T17	76343	81	0	0
T18	56954	8	0	0
T19	6326	5	0	0
T20	19168	2	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	12	0	0
T53	0	28	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	355579953	0	0
T1	182963	164340	0	0
T2	164606	5870	0	0
T3	33471	2932	0	0
T4	469436	468512	0	0
T16	252666	242898	0	0
T17	76343	9964	0	0
T18	56954	22604	0	0
T19	6326	1593	0	0
T20	19168	11695	0	0
T21	191485	191389	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T213,T219
1	1	Covered	T1,T3,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674783191	3063	0	0
DisabledNoTrigBkwd_A	674783191	201982	0	0
DisabledNoTrigFwd_A	674783191	391615582	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	3063	0	0
T212	3655	1224	0	0
T213	0	590	0	0
T219	0	825	0	0
T221	0	424	0	0
T230	875362	0	0	0
T231	518773	0	0	0
T232	7709	0	0	0
T233	456860	0	0	0
T234	163015	0	0	0
T235	416049	0	0	0
T236	398343	0	0	0
T237	265344	0	0	0
T238	18305	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	201982	0	0
T1	182963	65	0	0
T2	164606	0	0	0
T3	33471	30	0	0
T4	469436	1650	0	0
T5	0	959	0	0
T6	0	298	0	0
T16	252666	303	0	0
T17	76343	0	0	0
T18	56954	14	0	0
T19	6326	0	0	0
T20	19168	7	0	0
T21	191485	109	0	0
T53	0	37	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	391615582	0	0
T1	182963	16556	0	0
T2	164606	164596	0	0
T3	33471	5355	0	0
T4	469436	47269	0	0
T16	252666	103080	0	0
T17	76343	76254	0	0
T18	56954	3048	0	0
T19	6326	2172	0	0
T20	19168	4631	0	0
T21	191485	5857	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T3,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T52,T205
1	1	Covered	T1,T3,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674783191	6211	0	0
DisabledNoTrigBkwd_A	674783191	241343	0	0
DisabledNoTrigFwd_A	674783191	364910449	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	6211	0	0
T5	140263	0	0	0
T6	148821	0	0	0
T8	109823	0	0	0
T22	1467	665	0	0
T27	54048	0	0	0
T29	15958	0	0	0
T52	3293	786	0	0
T53	26655	0	0	0
T54	110571	0	0	0
T70	83262	0	0	0
T205	0	772	0	0
T207	0	641	0	0
T208	0	1487	0	0
T211	0	980	0	0
T217	0	880	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	241343	0	0
T1	182963	25	0	0
T2	164606	0	0	0
T3	33471	23	0	0
T4	469436	2790	0	0
T5	0	921	0	0
T16	252666	3	0	0
T17	76343	0	0	0
T18	56954	3	0	0
T19	6326	0	0	0
T20	19168	6	0	0
T21	191485	111	0	0
T22	0	32	0	0
T52	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	364910449	0	0
T1	182963	3077	0	0
T2	164606	164596	0	0
T3	33471	2940	0	0
T4	469436	17412	0	0
T16	252666	249402	0	0
T17	76343	76254	0	0
T18	56954	50997	0	0
T19	6326	3183	0	0
T20	19168	6992	0	0
T21	191485	9944	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T209,T214
1	1	Covered	T1,T3,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674783191	4472	0	0
DisabledNoTrigBkwd_A	674783191	163473	0	0
DisabledNoTrigFwd_A	674783191	391365629	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	4472	0	0
T88	19415	0	0	0
T94	127341	0	0	0
T206	3626	650	0	0
T209	0	405	0	0
T214	0	886	0	0
T215	0	941	0	0
T218	0	430	0	0
T220	0	392	0	0
T222	0	768	0	0
T239	267122	0	0	0
T240	12166	0	0	0
T241	27927	0	0	0
T242	10944	0	0	0
T243	19974	0	0	0
T244	27355	0	0	0
T245	128825	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	163473	0	0
T1	182963	24	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	2	0	0
T6	0	597	0	0
T8	0	1	0	0
T16	252666	85	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	11	0	0
T21	191485	0	0	0
T27	0	632	0	0
T28	0	2	0	0
T29	0	23	0	0
T54	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	391365629	0	0
T1	182963	21575	0	0
T2	164606	164596	0	0
T3	33471	32201	0	0
T4	469436	469429	0	0
T16	252666	232621	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	3777	0	0
T21	191485	191389	0	0