Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24,T25,T26
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T16
1	0	1	Covered	T1,T16,T4
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T3,T16,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T18
0	1	Covered	T27,T8,T28
1	0	Covered	T16,T18,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T16,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T18,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T18
1	0	Covered	T30,T31
1	1	Covered	T27,T8,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T16,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T16,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T32,T33,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T32,T34,T35
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T36,T37,T38
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T34,T39
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T16,T4,T18
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T16,T18
TimeoutSt->Phase0St	172	Covered	T16,T18,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T40
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T34,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T34,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1225	0	0
CheckAccumTrig0_A	2147483647	2282	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1047	0	0
CheckEn_A	2147483647	1184800924	0	0
CheckPhase0_A	2147483647	2610	0	0
CheckPhase1_A	2147483647	2569	0	0
CheckPhase2_A	2147483647	2523	0	0
CheckPhase3_A	2147483647	2460	0	0
CheckTimeout0_A	2147483647	4931	0	0
CheckTimeoutSt1_A	2147483647	511357	0	0
CheckTimeoutSt2_A	2147483647	4538	0	0
CheckTimeoutStTrig_A	2147483647	270	0	0
ErrorStAllEscAsserted_A	2147483647	6388	0	0
ErrorStIsTerminal_A	2147483647	5308	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1225	0	0
T10	153660	327	0	0
T11	0	248	0	0
T12	0	276	0	0
T41	0	126	0	0
T42	0	248	0	0
T43	536800	0	0	0
T44	430716	0	0	0
T45	443236	0	0	0
T46	589840	0	0	0
T47	1287372	0	0	0
T48	5460	0	0	0
T49	590136	0	0	0
T50	1072616	0	0	0
T51	18600	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T1	548889	3	0	0
T2	658424	1	0	0
T3	133884	3	0	0
T4	1877744	7	0	0
T5	0	4	0	0
T6	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T16	1010664	12	0	0
T17	305372	1	0	0
T18	227816	7	0	0
T19	25304	2	0	0
T20	76672	6	0	0
T21	765940	2	0	0
T22	1467	1	0	0
T27	0	2	0	0
T29	0	2	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T4	469436	0	0	0
T5	280526	0	0	0
T6	148821	0	0	0
T7	101989	0	0	0
T8	109823	0	0	0
T13	288916	0	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	113908	1	0	0
T19	12652	0	0	0
T20	38336	0	0	0
T21	382970	0	0	0
T22	2934	0	0	0
T25	0	3	0	0
T28	23268	0	0	0
T29	15958	1	0	0
T36	68535	0	0	0
T44	0	1	0	0
T50	0	1	0	0
T52	3293	0	0	0
T53	26655	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	5	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	166524	0	0	0
T71	13452	0	0	0
T72	35325	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1047	0	0
T4	1408308	5	0	0
T5	561052	0	0	0
T6	148821	0	0	0
T8	0	3	0	0
T15	0	1	0	0
T16	757998	5	0	0
T17	229029	0	0	0
T18	170862	6	0	0
T19	18978	1	0	0
T20	76672	3	0	0
T21	765940	0	0	0
T22	5868	0	0	0
T27	54048	0	0	0
T29	0	4	0	0
T32	0	9	0	0
T33	0	3	0	0
T36	0	2	0	0
T52	3293	0	0	0
T53	26655	3	0	0
T54	110571	5	0	0
T55	0	4	0	0
T70	333048	0	0	0
T71	0	2	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	4	0	0
T76	0	4	0	0
T77	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1184800924	0	0
T1	731852	205547	0	0
T2	658424	499658	0	0
T3	133884	43427	0	0
T4	1877744	953045	0	0
T16	1010664	590032	0	0
T17	305372	238723	0	0
T18	227816	126257	0	0
T19	25304	13173	0	0
T20	76672	19165	0	0
T21	765940	398577	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2610	0	0
T1	548889	3	0	0
T2	658424	1	0	0
T3	133884	3	0	0
T4	1877744	7	0	0
T5	0	4	0	0
T6	0	2	0	0
T8	0	2	0	0
T16	1010664	13	0	0
T17	305372	1	0	0
T18	227816	8	0	0
T19	25304	2	0	0
T20	76672	6	0	0
T21	765940	2	0	0
T22	1467	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	3	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T1	548889	3	0	0
T2	658424	1	0	0
T3	133884	3	0	0
T4	1877744	7	0	0
T5	0	4	0	0
T6	0	2	0	0
T8	0	2	0	0
T16	1010664	13	0	0
T17	305372	1	0	0
T18	227816	8	0	0
T19	25304	2	0	0
T20	76672	6	0	0
T21	765940	2	0	0
T22	1467	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	3	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	7	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2523	0	0
T1	548889	3	0	0
T2	658424	1	0	0
T3	133884	3	0	0
T4	1877744	7	0	0
T5	0	4	0	0
T6	0	2	0	0
T8	0	2	0	0
T16	1010664	13	0	0
T17	305372	1	0	0
T18	227816	8	0	0
T19	25304	2	0	0
T20	76672	6	0	0
T21	765940	2	0	0
T22	1467	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	3	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	7	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2460	0	0
T1	548889	3	0	0
T2	658424	1	0	0
T3	133884	3	0	0
T4	1877744	6	0	0
T5	0	4	0	0
T6	0	2	0	0
T8	0	2	0	0
T16	1010664	13	0	0
T17	305372	1	0	0
T18	227816	8	0	0
T19	25304	2	0	0
T20	76672	6	0	0
T21	765940	2	0	0
T22	1467	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	3	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	7	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4931	0	0
T3	100413	3	0	0
T4	1877744	0	0	0
T5	561052	0	0	0
T8	0	238	0	0
T16	1010664	2	0	0
T17	305372	0	0	0
T18	227816	2	0	0
T19	25304	1	0	0
T20	76672	1	0	0
T21	765940	0	0	0
T22	5868	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	6	0	0
T30	0	3	0	0
T32	0	64	0	0
T54	0	38	0	0
T55	0	5	0	0
T56	0	2	0	0
T70	83262	15	0	0
T71	0	2	0	0
T74	0	15	0	0
T75	0	7	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	511357	0	0
T3	100413	705	0	0
T4	1877744	0	0	0
T5	561052	0	0	0
T8	0	50508	0	0
T16	1010664	75	0	0
T17	305372	0	0	0
T18	227816	44	0	0
T19	25304	47	0	0
T20	76672	30	0	0
T21	765940	0	0	0
T22	5868	0	0	0
T27	0	657	0	0
T28	0	1287	0	0
T29	0	226	0	0
T30	0	328	0	0
T32	0	22515	0	0
T54	0	4684	0	0
T55	0	832	0	0
T56	0	256	0	0
T70	83262	3045	0	0
T71	0	471	0	0
T74	0	2927	0	0
T75	0	840	0	0
T78	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4538	0	0
T3	100413	3	0	0
T4	1877744	0	0	0
T5	561052	0	0	0
T8	0	236	0	0
T16	1010664	1	0	0
T17	305372	0	0	0
T18	227816	1	0	0
T19	25304	1	0	0
T20	76672	1	0	0
T21	765940	0	0	0
T22	5868	0	0	0
T29	0	4	0	0
T30	0	29	0	0
T32	0	56	0	0
T54	0	33	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0
T70	83262	15	0	0
T71	0	2	0	0
T74	0	14	0	0
T75	0	6	0	0
T76	0	8	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	270	0	0
T7	203978	0	0	0
T8	219646	1	0	0
T9	929965	0	0	0
T13	577832	0	0	0
T27	54048	1	0	0
T28	46536	1	0	0
T29	15958	0	0	0
T31	0	2	0	0
T32	277681	6	0	0
T33	368689	0	0	0
T35	0	5	0	0
T36	137070	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T54	110571	0	0	0
T56	42433	0	0	0
T60	0	2	0	0
T71	26904	0	0	0
T72	70650	0	0	0
T75	103631	4	0	0
T76	678446	1	0	0
T77	16703	1	0	0
T79	250690	0	0	0
T80	22899	1	0	0
T81	0	1	0	0
T82	0	4	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	3	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	127983	0	0	0
T90	122269	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6388	0	0
T10	153660	1472	0	0
T11	0	1381	0	0
T12	0	1404	0	0
T41	0	710	0	0
T42	0	1421	0	0
T43	536800	0	0	0
T44	430716	0	0	0
T45	443236	0	0	0
T46	589840	0	0	0
T47	1287372	0	0	0
T48	5460	0	0	0
T49	590136	0	0	0
T50	1072616	0	0	0
T51	18600	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5308	0	0
T10	153660	1232	0	0
T11	0	1141	0	0
T12	0	1164	0	0
T41	0	590	0	0
T42	0	1181	0	0
T43	536800	0	0	0
T44	430716	0	0	0
T45	443236	0	0	0
T46	589840	0	0	0
T47	1287372	0	0	0
T48	5460	0	0	0
T49	590136	0	0	0
T50	1072616	0	0	0
T51	18600	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731852	731532	0	0
T2	658424	658384	0	0
T3	133884	133668	0	0
T4	1877744	1877716	0	0
T16	1010664	1010616	0	0
T17	305372	305016	0	0
T18	227816	227604	0	0
T19	25304	24912	0	0
T20	76672	76344	0	0
T21	765940	765556	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731852	731532	0	0
T2	658424	658384	0	0
T3	133884	133668	0	0
T4	1877744	1877716	0	0
T16	1010664	1010616	0	0
T17	305372	305016	0	0
T18	227816	227604	0	0
T19	25304	24912	0	0
T20	76672	76344	0	0
T21	765940	765556	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T18,T19
1	0	1	Covered	T1,T16,T4
1	1	0	Covered	T2,T16,T18
1	1	1	Covered	T3,T19,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T20
0	1	Covered	T8,T28,T32
1	0	Covered	T29,T59,T91

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T19,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T59,T91

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Not Covered
1	1	Covered	T8,T28,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T1,T16,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T4,T5,T54

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T4,T21,T54

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T4
1	Covered	T3,T16,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T16,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T16
Phase1St	198	Covered	T1,T3,T16
Phase2St	215	Covered	T1,T3,T16
Phase3St	233	Covered	T1,T3,T16
TerminalSt	249	Covered	T1,T3,T16
TimeoutSt	159	Covered	T3,T19,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T3,T16
IdleSt->TimeoutSt	159	Covered	T3,T19,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T84,T40
Phase0St->Phase1St	198	Covered	T1,T3,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T34,T40
Phase1St->Phase2St	215	Covered	T1,T3,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T64,T92,T93
Phase2St->Phase3St	233	Covered	T1,T3,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T34,T94
Phase3St->TerminalSt	249	Covered	T1,T3,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T4,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T19,T20
TimeoutSt->Phase0St	172	Covered	T29,T8,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T8,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T40,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T34,T40
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T64,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T34,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674783191	280	0	0
CheckAccumTrig0_A	674783191	477	0	0
CheckAccumTrig1_A	674783191	20	0	0
CheckClr_A	674783191	204	0	0
CheckEn_A	674522911	302746830	0	0
CheckPhase0_A	674783191	551	0	0
CheckPhase1_A	674783191	544	0	0
CheckPhase2_A	674783191	533	0	0
CheckPhase3_A	674783191	519	0	0
CheckTimeout0_A	674783191	1512	0	0
CheckTimeoutSt1_A	674783191	166026	0	0
CheckTimeoutSt2_A	674783191	1425	0	0
CheckTimeoutStTrig_A	674783191	64	0	0
ErrorStAllEscAsserted_A	674783191	1581	0	0
ErrorStIsTerminal_A	674783191	1311	0	0
EscStateOut_A	674521019	674451549	0	0
u_state_regs_A	674783191	674599046	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	280	0	0
T10	38415	71	0	0
T11	0	75	0	0
T12	0	56	0	0
T41	0	23	0	0
T42	0	55	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	477	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	6	0	0
T5	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T22	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	20	0	0
T7	101989	0	0	0
T8	109823	0	0	0
T9	929965	0	0	0
T13	288916	0	0	0
T14	403996	0	0	0
T28	23268	0	0	0
T29	15958	1	0	0
T36	68535	0	0	0
T59	0	1	0	0
T61	0	4	0	0
T64	0	1	0	0
T71	13452	0	0	0
T72	35325	0	0	0
T91	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	3	0	0
T99	0	1	0	0
T100	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	204	0	0
T4	469436	5	0	0
T5	140263	0	0	0
T15	0	1	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T32	0	6	0	0
T33	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T70	83262	0	0	0
T75	0	2	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674522911	302746830	0	0
T1	182963	3077	0	0
T2	164606	164596	0	0
T3	33471	2940	0	0
T4	469436	12037	0	0
T16	252666	197214	0	0
T17	76343	76253	0	0
T18	56954	50996	0	0
T19	6326	3182	0	0
T20	19168	6992	0	0
T21	191485	9944	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	551	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	6	0	0
T5	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T22	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	544	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	6	0	0
T5	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T22	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	533	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	6	0	0
T5	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T22	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	519	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	5	0	0
T5	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T22	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1512	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	215	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	1	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	0	8	0	0
T54	0	14	0	0
T55	0	1	0	0
T70	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	166026	0	0
T3	33471	235	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	43442	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	47	0	0
T20	19168	30	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T28	0	698	0	0
T29	0	63	0	0
T32	0	2256	0	0
T54	0	1889	0	0
T55	0	31	0	0
T70	0	2024	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1425	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	214	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	1	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	1	0	0
T32	0	6	0	0
T54	0	14	0	0
T55	0	1	0	0
T70	0	10	0	0
T79	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	64	0	0
T7	101989	0	0	0
T8	109823	1	0	0
T9	929965	0	0	0
T13	288916	0	0	0
T14	403996	0	0	0
T28	23268	1	0	0
T30	0	1	0	0
T32	0	2	0	0
T36	68535	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T71	13452	0	0	0
T72	35325	0	0	0
T75	0	2	0	0
T77	0	1	0	0
T80	0	1	0	0
T82	0	3	0	0
T101	13663	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1581	0	0
T10	38415	358	0	0
T11	0	362	0	0
T12	0	353	0	0
T41	0	159	0	0
T42	0	349	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1311	0	0
T10	38415	298	0	0
T11	0	302	0	0
T12	0	293	0	0
T41	0	129	0	0
T42	0	289	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674521019	674451549	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	674599046	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T27
1	0	1	Covered	T1,T16,T6
1	1	0	Covered	T2,T3,T18
1	1	1	Covered	T3,T54,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T54,T29
0	1	Covered	T54,T8,T28
1	0	Covered	T29,T56,T77

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T54,T29
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T56,T77

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T54,T29
1	0	Not Covered
1	1	Covered	T54,T8,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T20,T27,T74

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T20,T5,T6
1	Covered	T1,T16,T54

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T54,T29,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T20,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T5,T54

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T6,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T6,T54

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T16,T20
Phase1St	198	Covered	T1,T16,T20
Phase2St	215	Covered	T1,T16,T20
Phase3St	233	Covered	T1,T16,T20
TerminalSt	249	Covered	T1,T16,T20
TimeoutSt	159	Covered	T3,T54,T29

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T16,T20
IdleSt->TimeoutSt	159	Covered	T3,T54,T29
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T102,T45
Phase0St->Phase1St	198	Covered	T1,T16,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T103,T104,T105
Phase1St->Phase2St	215	Covered	T1,T16,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T106,T35
Phase2St->Phase3St	233	Covered	T1,T16,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T107,T102,T108
Phase3St->TerminalSt	249	Covered	T1,T16,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T20,T54
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T29,T8
TimeoutSt->Phase0St	172	Covered	T54,T29,T8

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T54,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T54,T29,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T54,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T29,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T102,T45,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T103,T104,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T16,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T16,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T106,T35
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T16,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T16,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T102,T108
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T16,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T16,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T54,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674783191	320	0	0
CheckAccumTrig0_A	674783191	499	0	0
CheckAccumTrig1_A	674783191	21	0	0
CheckClr_A	674783191	234	0	0
CheckEn_A	674522911	324259016	0	0
CheckPhase0_A	674783191	589	0	0
CheckPhase1_A	674783191	584	0	0
CheckPhase2_A	674783191	574	0	0
CheckPhase3_A	674783191	562	0	0
CheckTimeout0_A	674783191	1010	0	0
CheckTimeoutSt1_A	674783191	101702	0	0
CheckTimeoutSt2_A	674783191	906	0	0
CheckTimeoutStTrig_A	674783191	82	0	0
ErrorStAllEscAsserted_A	674783191	1581	0	0
ErrorStIsTerminal_A	674783191	1311	0	0
EscStateOut_A	674521019	674451549	0	0
u_state_regs_A	674783191	674599046	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	320	0	0
T10	38415	102	0	0
T11	0	41	0	0
T12	0	74	0	0
T41	0	42	0	0
T42	0	61	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	499	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T54	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	21	0	0
T7	101989	0	0	0
T8	109823	0	0	0
T9	929965	0	0	0
T13	288916	0	0	0
T14	403996	0	0	0
T25	0	1	0	0
T28	23268	0	0	0
T29	15958	1	0	0
T36	68535	0	0	0
T56	0	1	0	0
T71	13452	0	0	0
T72	35325	0	0	0
T77	0	1	0	0
T84	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	234	0	0
T5	140263	0	0	0
T6	148821	0	0	0
T8	0	1	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	54048	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T52	3293	0	0	0
T53	26655	0	0	0
T54	110571	4	0	0
T70	83262	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T79	0	5	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674522911	324259016	0	0
T1	182963	21575	0	0
T2	164606	164596	0	0
T3	33471	32200	0	0
T4	469436	469428	0	0
T16	252666	183061	0	0
T17	76343	76253	0	0
T18	56954	56900	0	0
T19	6326	6227	0	0
T20	19168	3777	0	0
T21	191485	191388	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	589	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T54	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	584	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T54	0	7	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	574	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T54	0	7	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	562	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	0	0	0
T4	469436	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	3	0	0
T21	191485	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T54	0	7	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1010	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	20	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T28	0	1	0	0
T29	0	3	0	0
T32	0	21	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	2	0	0
T74	0	1	0	0
T75	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	101702	0	0
T3	33471	235	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	5996	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T28	0	589	0	0
T29	0	102	0	0
T32	0	7267	0	0
T54	0	140	0	0
T55	0	687	0	0
T56	0	256	0	0
T74	0	70	0	0
T75	0	613	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	906	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	19	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	2	0	0
T30	0	26	0	0
T32	0	19	0	0
T56	0	1	0	0
T75	0	3	0	0
T80	0	1	0	0
T83	0	1	0	0
T115	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	82	0	0
T7	101989	0	0	0
T8	109823	1	0	0
T9	929965	0	0	0
T13	288916	0	0	0
T28	23268	1	0	0
T29	15958	0	0	0
T32	0	2	0	0
T36	68535	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T54	110571	5	0	0
T55	0	1	0	0
T71	13452	0	0	0
T72	35325	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T80	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1581	0	0
T10	38415	359	0	0
T11	0	323	0	0
T12	0	348	0	0
T41	0	194	0	0
T42	0	357	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1311	0	0
T10	38415	299	0	0
T11	0	263	0	0
T12	0	288	0	0
T41	0	164	0	0
T42	0	297	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674521019	674451549	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	674599046	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T16,T18
1	0	1	Covered	T1,T16,T21
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T16,T18,T70

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T70
0	1	Covered	T27,T32,T75
1	0	Covered	T18,T55,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T18,T70
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T55,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T70
1	0	Covered	T30
1	1	Covered	T27,T32,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T16,T20,T53

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T8,T28,T55

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T4
1	Covered	T3,T16,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T18
1	Covered	T1,T16,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T16,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T16
Phase1St	198	Covered	T1,T3,T16
Phase2St	215	Covered	T1,T3,T16
Phase3St	233	Covered	T1,T3,T16
TerminalSt	249	Covered	T1,T3,T16
TimeoutSt	159	Covered	T16,T18,T70

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T3,T16
IdleSt->TimeoutSt	159	Covered	T16,T18,T70
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T39,T116
Phase0St->Phase1St	198	Covered	T1,T3,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T35,T24,T117
Phase1St->Phase2St	215	Covered	T1,T3,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T58,T39,T49
Phase2St->Phase3St	233	Covered	T1,T3,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T39,T64,T25
Phase3St->TerminalSt	249	Covered	T1,T3,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T18,T54
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T70,T54
TimeoutSt->Phase0St	172	Covered	T18,T27,T55

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T70
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T55
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T70
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T70,T54
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T39,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T24,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T58,T39,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T64,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T18,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674783191	316	0	0
CheckAccumTrig0_A	674783191	487	0	0
CheckAccumTrig1_A	674783191	25	0	0
CheckClr_A	674783191	225	0	0
CheckEn_A	674522911	296699418	0	0
CheckPhase0_A	674783191	568	0	0
CheckPhase1_A	674783191	557	0	0
CheckPhase2_A	674783191	547	0	0
CheckPhase3_A	674783191	536	0	0
CheckTimeout0_A	674783191	1009	0	0
CheckTimeoutSt1_A	674783191	112551	0	0
CheckTimeoutSt2_A	674783191	916	0	0
CheckTimeoutStTrig_A	674783191	67	0	0
ErrorStAllEscAsserted_A	674783191	1629	0	0
ErrorStIsTerminal_A	674783191	1359	0	0
EscStateOut_A	674521019	674451549	0	0
u_state_regs_A	674783191	674599046	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	316	0	0
T10	38415	68	0	0
T11	0	77	0	0
T12	0	76	0	0
T41	0	36	0	0
T42	0	59	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	487	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T16	252666	5	0	0
T17	76343	0	0	0
T18	56954	3	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	25	0	0
T5	140263	0	0	0
T6	148821	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T25	0	1	0	0
T52	3293	0	0	0
T53	26655	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	83262	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	225	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	3	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T55	0	1	0	0
T70	83262	0	0	0
T71	0	2	0	0
T75	0	2	0	0
T76	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674522911	296699418	0	0
T1	182963	16556	0	0
T2	164606	164596	0	0
T3	33471	5355	0	0
T4	469436	3068	0	0
T16	252666	102080	0	0
T17	76343	76253	0	0
T18	56954	3048	0	0
T19	6326	2171	0	0
T20	19168	4631	0	0
T21	191485	5857	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	568	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T16	252666	5	0	0
T17	76343	0	0	0
T18	56954	4	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	557	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T16	252666	5	0	0
T17	76343	0	0	0
T18	56954	4	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	547	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T16	252666	5	0	0
T17	76343	0	0	0
T18	56954	4	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	536	0	0
T1	182963	1	0	0
T2	164606	0	0	0
T3	33471	1	0	0
T4	469436	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T16	252666	5	0	0
T17	76343	0	0	0
T18	56954	4	0	0
T19	6326	0	0	0
T20	19168	1	0	0
T21	191485	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1009	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	3	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T32	0	24	0	0
T54	0	19	0	0
T55	0	2	0	0
T70	83262	5	0	0
T71	0	2	0	0
T74	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	112551	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	1070	0	0
T16	252666	73	0	0
T17	76343	0	0	0
T18	56954	3	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	657	0	0
T32	0	10861	0	0
T54	0	2655	0	0
T55	0	51	0	0
T70	83262	1021	0	0
T71	0	471	0	0
T74	0	1640	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	916	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	3	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T32	0	21	0	0
T54	0	19	0	0
T55	0	1	0	0
T70	83262	5	0	0
T71	0	2	0	0
T74	0	8	0	0
T75	0	1	0	0
T76	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	67	0	0
T7	101989	0	0	0
T8	109823	0	0	0
T13	288916	0	0	0
T27	54048	1	0	0
T28	23268	0	0	0
T29	15958	0	0	0
T32	0	3	0	0
T35	0	4	0	0
T36	68535	0	0	0
T54	110571	0	0	0
T71	13452	0	0	0
T72	35325	0	0	0
T75	0	2	0	0
T76	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1629	0	0
T10	38415	377	0	0
T11	0	363	0	0
T12	0	355	0	0
T41	0	182	0	0
T42	0	352	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1359	0	0
T10	38415	317	0	0
T11	0	303	0	0
T12	0	295	0	0
T41	0	152	0	0
T42	0	292	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674521019	674451549	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	674599046	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24,T25,T26
1	1	1	Covered	T2,T3,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T16
1	0	1	Covered	T1,T16,T54
1	1	0	Covered	T3,T70,T27
1	1	1	Covered	T3,T16,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T18
0	1	Covered	T32,T38,T35
1	0	Covered	T16,T57,T60

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T16,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T57,T60

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T18
1	0	Covered	T31
1	1	Covered	T32,T38,T35

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T17
1	Covered	T2,T16,T72

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T17
1	Covered	T3,T16,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T18,T19,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T16,T17,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T16,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T16
Phase1St	198	Covered	T2,T3,T16
Phase2St	215	Covered	T2,T3,T16
Phase3St	233	Covered	T2,T3,T16
TerminalSt	249	Covered	T2,T3,T16
TimeoutSt	159	Covered	T3,T16,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T16
IdleSt->TimeoutSt	159	Covered	T3,T16,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T30,T84
Phase0St->Phase1St	198	Covered	T2,T3,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T118,T60,T119
Phase1St->Phase2St	215	Covered	T2,T3,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T36,T37,T38
Phase2St->Phase3St	233	Covered	T2,T3,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T39,T120,T121
Phase3St->TerminalSt	249	Covered	T2,T3,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T18,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T18,T29
TimeoutSt->Phase0St	172	Covered	T16,T32,T57

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T32,T57
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T29
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T60,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T118,T60,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T120,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674783191	309	0	0
CheckAccumTrig0_A	674783191	819	0	0
CheckAccumTrig1_A	674783191	51	0	0
CheckClr_A	674783191	384	0	0
CheckEn_A	674522911	261095660	0	0
CheckPhase0_A	674783191	902	0	0
CheckPhase1_A	674783191	884	0	0
CheckPhase2_A	674783191	869	0	0
CheckPhase3_A	674783191	843	0	0
CheckTimeout0_A	674783191	1400	0	0
CheckTimeoutSt1_A	674783191	131078	0	0
CheckTimeoutSt2_A	674783191	1291	0	0
CheckTimeoutStTrig_A	674783191	57	0	0
ErrorStAllEscAsserted_A	674783191	1597	0	0
ErrorStIsTerminal_A	674783191	1327	0	0
EscStateOut_A	674521019	674451549	0	0
u_state_regs_A	674783191	674599046	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	309	0	0
T10	38415	86	0	0
T11	0	55	0	0
T12	0	70	0	0
T41	0	25	0	0
T42	0	73	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	819	0	0
T2	164606	1	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	0	1	0	0
T16	252666	3	0	0
T17	76343	1	0	0
T18	56954	3	0	0
T19	6326	2	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T53	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	51	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	56954	0	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T25	0	2	0	0
T44	0	1	0	0
T50	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T70	83262	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	384	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T8	0	1	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	2	0	0
T19	6326	1	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T36	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T70	83262	0	0	0
T72	0	3	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674522911	261095660	0	0
T1	182963	164339	0	0
T2	164606	5870	0	0
T3	33471	2932	0	0
T4	469436	468512	0	0
T16	252666	107677	0	0
T17	76343	9964	0	0
T18	56954	15313	0	0
T19	6326	1593	0	0
T20	19168	3765	0	0
T21	191485	191388	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	902	0	0
T2	164606	1	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	0	1	0	0
T16	252666	4	0	0
T17	76343	1	0	0
T18	56954	3	0	0
T19	6326	2	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T53	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	884	0	0
T2	164606	1	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	0	1	0	0
T16	252666	4	0	0
T17	76343	1	0	0
T18	56954	3	0	0
T19	6326	2	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T53	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	869	0	0
T2	164606	1	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	0	1	0	0
T16	252666	4	0	0
T17	76343	1	0	0
T18	56954	3	0	0
T19	6326	2	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T53	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	843	0	0
T2	164606	1	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	0	1	0	0
T16	252666	4	0	0
T17	76343	1	0	0
T18	56954	3	0	0
T19	6326	2	0	0
T20	19168	1	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T27	0	1	0	0
T53	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1400	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T16	252666	1	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	11	0	0
T55	0	1	0	0
T74	0	6	0	0
T75	0	2	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	131078	0	0
T3	33471	235	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T16	252666	2	0	0
T17	76343	0	0	0
T18	56954	41	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	61	0	0
T30	0	328	0	0
T32	0	2131	0	0
T55	0	63	0	0
T74	0	1217	0	0
T75	0	227	0	0
T78	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1291	0	0
T3	33471	1	0	0
T4	469436	0	0	0
T5	140263	0	0	0
T16	252666	0	0	0
T17	76343	0	0	0
T18	56954	1	0	0
T19	6326	0	0	0
T20	19168	0	0	0
T21	191485	0	0	0
T22	1467	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	10	0	0
T55	0	1	0	0
T57	0	1	0	0
T74	0	6	0	0
T75	0	2	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	57	0	0
T31	0	2	0	0
T32	277681	1	0	0
T33	368689	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T56	42433	0	0	0
T60	0	2	0	0
T75	103631	0	0	0
T76	678446	0	0	0
T77	16703	0	0	0
T79	250690	0	0	0
T80	22899	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	127983	0	0	0
T90	122269	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1597	0	0
T10	38415	378	0	0
T11	0	333	0	0
T12	0	348	0	0
T41	0	175	0	0
T42	0	363	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	1327	0	0
T10	38415	318	0	0
T11	0	273	0	0
T12	0	288	0	0
T41	0	145	0	0
T42	0	303	0	0
T43	134200	0	0	0
T44	107679	0	0	0
T45	110809	0	0	0
T46	147460	0	0	0
T47	321843	0	0	0
T48	1365	0	0	0
T49	147534	0	0	0
T50	268154	0	0	0
T51	4650	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674521019	674451549	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674783191	674599046	0	0
T1	182963	182883	0	0
T2	164606	164596	0	0
T3	33471	33417	0	0
T4	469436	469429	0	0
T16	252666	252654	0	0
T17	76343	76254	0	0
T18	56954	56901	0	0
T19	6326	6228	0	0
T20	19168	19086	0	0
T21	191485	191389	0	0