Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T91,T221
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12874	0	0
DisabledNoTrigBkwd_A	2147483647	781757	0	0
DisabledNoTrigFwd_A	2147483647	1577811819	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12874	0	0
T15	45720	0	0	0
T39	2994	632	0	0
T40	32863	0	0	0
T41	104462	0	0	0
T42	167210	0	0	0
T43	618640	0	0	0
T52	637556	0	0	0
T58	92518	0	0	0
T59	19485	0	0	0
T67	47425	0	0	0
T85	40318	0	0	0
T86	24516	0	0	0
T91	1507	599	0	0
T119	88425	0	0	0
T120	392595	0	0	0
T134	8544	0	0	0
T136	0	344	0	0
T140	111086	0	0	0
T221	0	615	0	0
T222	5304	1844	0	0
T223	0	311	0	0
T224	0	294	0	0
T225	0	352	0	0
T226	0	403	0	0
T227	0	499	0	0
T228	0	938	0	0
T229	0	340	0	0
T230	0	511	0	0
T231	0	782	0	0
T232	0	844	0	0
T233	0	599	0	0
T234	0	621	0	0
T235	0	797	0	0
T236	0	894	0	0
T237	0	655	0	0
T238	234750	0	0	0
T239	113101	0	0	0
T240	14012	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	781757	0	0
T1	95028	216	0	0
T2	1345344	3161	0	0
T3	66816	9	0	0
T4	3725952	1706	0	0
T5	274872	0	0	0
T6	644964	15501	0	0
T7	750760	279	0	0
T8	126720	0	0	0
T9	208572	129	0	0
T10	1520912	2655	0	0
T15	0	40	0	0
T36	0	560	0	0
T37	0	23	0	0
T38	0	15273	0	0
T39	0	16	0	0
T40	0	56	0	0
T41	0	3	0	0
T43	0	3536	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1577811819	0	0
T1	95028	59678	0	0
T2	1345344	714559	0	0
T3	66816	52989	0	0
T4	3725952	2789094	0	0
T5	274872	2840	0	0
T6	644964	1022003	0	0
T7	750760	368545	0	0
T8	126720	85126	0	0
T9	208572	169907	0	0
T10	1520912	1318149	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T222,T223,T226
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711619072	4152	0	0
DisabledNoTrigBkwd_A	711619072	234006	0	0
DisabledNoTrigFwd_A	711619072	342959776	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	4152	0	0
T52	637556	0	0	0
T85	40318	0	0	0
T86	24516	0	0	0
T119	88425	0	0	0
T120	392595	0	0	0
T134	8544	0	0	0
T222	5304	1844	0	0
T223	0	311	0	0
T226	0	403	0	0
T229	0	340	0	0
T233	0	599	0	0
T237	0	655	0	0
T238	234750	0	0	0
T239	113101	0	0	0
T240	14012	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	234006	0	0
T1	23757	5	0	0
T2	336336	1201	0	0
T3	16704	9	0	0
T4	931488	1703	0	0
T5	68718	0	0	0
T6	161241	8334	0	0
T7	187690	121	0	0
T8	31680	0	0	0
T9	52143	118	0	0
T10	380228	427	0	0
T36	0	195	0	0
T37	0	21	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	342959776	0	0
T1	23757	14838	0	0
T2	336336	7152	0	0
T3	16704	8766	0	0
T4	931488	4565	0	0
T5	68718	704	0	0
T6	161241	211869	0	0
T7	187690	1846	0	0
T8	31680	28763	0	0
T9	52143	40432	0	0
T10	380228	326383	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T136,T224
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711619072	4368	0	0
DisabledNoTrigBkwd_A	711619072	184999	0	0
DisabledNoTrigFwd_A	711619072	418742072	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	4368	0	0
T15	45720	0	0	0
T39	2994	632	0	0
T40	32863	0	0	0
T41	104462	0	0	0
T42	167210	0	0	0
T43	618640	0	0	0
T58	92518	0	0	0
T59	19485	0	0	0
T67	47425	0	0	0
T136	0	344	0	0
T140	111086	0	0	0
T224	0	294	0	0
T225	0	352	0	0
T227	0	499	0	0
T231	0	782	0	0
T232	0	844	0	0
T234	0	621	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	184999	0	0
T1	23757	208	0	0
T2	336336	1956	0	0
T3	16704	0	0	0
T4	931488	3	0	0
T5	68718	0	0	0
T6	161241	2496	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	876	0	0
T15	0	40	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	0	16	0	0
T43	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	418742072	0	0
T1	23757	18473	0	0
T2	336336	37184	0	0
T3	16704	10947	0	0
T4	931488	924687	0	0
T5	68718	708	0	0
T6	161241	131071	0	0
T7	187690	177498	0	0
T8	31680	1638	0	0
T9	52143	48346	0	0
T10	380228	499209	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T230,T236
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711619072	2004	0	0
DisabledNoTrigBkwd_A	711619072	177072	0	0
DisabledNoTrigFwd_A	711619072	401506309	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	2004	0	0
T16	124681	0	0	0
T19	34007	0	0	0
T23	967460	0	0	0
T60	4555	0	0	0
T61	89251	0	0	0
T71	119783	0	0	0
T72	123483	0	0	0
T76	30491	0	0	0
T91	1507	599	0	0
T92	89702	0	0	0
T230	0	511	0	0
T236	0	894	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	177072	0	0
T1	23757	2	0	0
T2	336336	4	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	2160	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	10	0	0
T10	380228	431	0	0
T36	0	98	0	0
T37	0	1	0	0
T38	0	9630	0	0
T40	0	23	0	0
T41	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	401506309	0	0
T1	23757	7898	0	0
T2	336336	333895	0	0
T3	16704	16638	0	0
T4	931488	928431	0	0
T5	68718	712	0	0
T6	161241	299873	0	0
T7	187690	186275	0	0
T8	31680	28399	0	0
T9	52143	32788	0	0
T10	380228	328132	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T6,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T221,T228,T235
1	1	Covered	T1,T6,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711619072	2350	0	0
DisabledNoTrigBkwd_A	711619072	185680	0	0
DisabledNoTrigFwd_A	711619072	414603662	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	2350	0	0
T49	304643	0	0	0
T82	30357	0	0	0
T142	48134	0	0	0
T221	1390	615	0	0
T228	0	938	0	0
T235	0	797	0	0
T241	19710	0	0	0
T242	55239	0	0	0
T243	134510	0	0	0
T244	530629	0	0	0
T245	22455	0	0	0
T246	19583	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	185680	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	2511	0	0
T7	187690	158	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	921	0	0
T36	0	267	0	0
T38	0	5639	0	0
T40	0	33	0	0
T41	0	1	0	0
T43	0	3523	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	414603662	0	0
T1	23757	18469	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	716	0	0
T6	161241	379190	0	0
T7	187690	2926	0	0
T8	31680	26326	0	0
T9	52143	48341	0	0
T10	380228	164425	0	0