Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T2,T4,T6
1	1	0	Covered	T1,T6,T8
1	1	1	Covered	T6,T8,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T10,T14
1	0	Covered	T10,T15,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T8,T10
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T6,T17,T18
1	1	Covered	T6,T10,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T6,T8,T10
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T10,T19,T20
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T21,T22
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T2,T6,T15
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T21,T23,T24
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T6,T8,T10
TimeoutSt->Phase0St	172	Covered	T6,T10,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T10,T19,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T21,T22
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T6,T15
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T23,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	952	0	0
CheckAccumTrig0_A	2147483647	2347	0	0
CheckAccumTrig1_A	2147483647	102	0	0
CheckClr_A	2147483647	1041	0	0
CheckEn_A	2147483647	1238258780	0	0
CheckPhase0_A	2147483647	2621	0	0
CheckPhase1_A	2147483647	2563	0	0
CheckPhase2_A	2147483647	2517	0	0
CheckPhase3_A	2147483647	2481	0	0
CheckTimeout0_A	2147483647	3216	0	0
CheckTimeoutSt1_A	2147483647	401581	0	0
CheckTimeoutSt2_A	2147483647	2885	0	0
CheckTimeoutStTrig_A	2147483647	222	0	0
ErrorStAllEscAsserted_A	2147483647	5024	0	0
ErrorStIsTerminal_A	2147483647	4184	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	952	0	0
T11	172716	273	0	0
T12	0	159	0	0
T13	0	114	0	0
T25	0	145	0	0
T26	0	261	0	0
T27	3243448	0	0	0
T28	3825496	0	0	0
T29	1829100	0	0	0
T30	220304	0	0	0
T31	133880	0	0	0
T32	43212	0	0	0
T33	822072	0	0	0
T34	87020	0	0	0
T35	77280	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T1	95028	4	0	0
T2	1345344	8	0	0
T3	66816	1	0	0
T4	3725952	2	0	0
T5	274872	0	0	0
T6	644964	16	0	0
T7	750760	2	0	0
T8	126720	0	0	0
T9	208572	3	0	0
T10	1520912	15	0	0
T15	0	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	8	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	102	0	0
T10	380228	2	0	0
T14	30204	0	0	0
T15	0	1	0	0
T16	124681	1	0	0
T20	0	3	0	0
T22	63742	0	0	0
T23	1934920	1	0	0
T24	1025356	1	0	0
T27	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	32863	0	0	0
T41	104462	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	92518	0	0	0
T59	19485	0	0	0
T60	9110	0	0	0
T61	178502	0	0	0
T62	249124	0	0	0
T63	120540	0	0	0
T64	186336	0	0	0
T65	79880	0	0	0
T66	3110	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1041	0	0
T1	23757	1	0	0
T2	672672	5	0	0
T3	33408	0	0	0
T4	1862976	1	0	0
T5	137436	0	0	0
T6	483723	6	0	0
T7	563070	0	0	0
T8	95040	0	0	0
T9	208572	0	0	0
T10	1520912	11	0	0
T14	60408	0	0	0
T15	0	9	0	0
T19	0	3	0	0
T21	0	2	0	0
T23	0	4	0	0
T24	0	9	0	0
T36	1220088	0	0	0
T37	185702	0	0	0
T38	926152	1	0	0
T39	5988	0	0	0
T40	32863	1	0	0
T41	104462	0	0	0
T43	0	3	0	0
T45	0	2	0	0
T58	92518	0	0	0
T67	0	1	0	0
T68	0	4	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238258780	0	0
T1	95028	25446	0	0
T2	1345344	383359	0	0
T3	66816	52986	0	0
T4	3725952	2789091	0	0
T5	274872	2836	0	0
T6	644964	767941	0	0
T7	750760	368543	0	0
T8	126720	61528	0	0
T9	208572	110205	0	0
T10	1520912	1295433	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2621	0	0
T1	95028	4	0	0
T2	1345344	8	0	0
T3	66816	1	0	0
T4	3725952	2	0	0
T5	274872	0	0	0
T6	644964	17	0	0
T7	750760	2	0	0
T8	126720	1	0	0
T9	208572	3	0	0
T10	1520912	21	0	0
T14	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	8	0	0
T39	0	1	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T1	95028	4	0	0
T2	1345344	8	0	0
T3	66816	1	0	0
T4	3725952	2	0	0
T5	274872	0	0	0
T6	644964	15	0	0
T7	750760	2	0	0
T8	126720	1	0	0
T9	208572	3	0	0
T10	1520912	21	0	0
T14	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	7	0	0
T39	0	1	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T1	95028	4	0	0
T2	1345344	7	0	0
T3	66816	1	0	0
T4	3725952	2	0	0
T5	274872	0	0	0
T6	644964	14	0	0
T7	750760	2	0	0
T8	126720	1	0	0
T9	208572	3	0	0
T10	1520912	21	0	0
T14	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	7	0	0
T39	0	1	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2481	0	0
T1	95028	4	0	0
T2	1345344	7	0	0
T3	66816	1	0	0
T4	3725952	2	0	0
T5	274872	0	0	0
T6	644964	14	0	0
T7	750760	2	0	0
T8	126720	1	0	0
T9	208572	3	0	0
T10	1520912	21	0	0
T14	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	7	0	0
T39	0	1	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3216	0	0
T6	644964	23	0	0
T7	750760	0	0	0
T8	126720	11	0	0
T9	208572	0	0	0
T10	1520912	8	0	0
T14	120816	4	0	0
T15	0	1	0	0
T16	0	4	0	0
T19	0	1	0	0
T23	0	1	0	0
T24	0	6	0	0
T36	1626784	0	0	0
T37	371404	0	0	0
T38	1852304	1	0	0
T39	11976	0	0	0
T40	0	3	0	0
T64	0	9	0	0
T70	0	1	0	0
T71	0	2	0	0
T74	0	52	0	0
T75	0	8	0	0
T76	0	7	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	401581	0	0
T6	644964	1156	0	0
T7	750760	0	0	0
T8	126720	581	0	0
T9	208572	0	0	0
T10	1520912	930	0	0
T14	120816	768	0	0
T15	0	3	0	0
T16	0	149	0	0
T19	0	55	0	0
T23	0	1	0	0
T24	0	51	0	0
T36	1626784	0	0	0
T37	371404	0	0	0
T38	1852304	149	0	0
T39	11976	0	0	0
T40	0	115	0	0
T44	0	7	0	0
T64	0	2001	0	0
T70	0	41	0	0
T71	0	108	0	0
T74	0	2272	0	0
T75	0	890	0	0
T76	0	523	0	0
T77	0	181	0	0
T78	0	97	0	0
T79	0	88	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2885	0	0
T6	644964	20	0	0
T7	750760	0	0	0
T8	126720	9	0	0
T9	208572	0	0	0
T10	1520912	1	0	0
T14	120816	3	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T24	0	1	0	0
T36	1626784	0	0	0
T37	371404	0	0	0
T38	1852304	1	0	0
T39	11976	0	0	0
T40	0	1	0	0
T47	0	2	0	0
T48	0	6	0	0
T64	0	8	0	0
T70	0	1	0	0
T74	0	3	0	0
T75	0	5	0	0
T76	0	7	0	0
T77	0	1	0	0
T80	0	6	0	0
T81	0	3	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	222	0	0
T6	161241	1	0	0
T10	760456	5	0	0
T14	60408	1	0	0
T19	34007	0	0	0
T20	0	1	0	0
T21	406165	0	0	0
T24	0	3	0	0
T27	0	1	0	0
T36	813392	0	0	0
T37	185702	0	0	0
T38	926152	0	0	0
T39	5988	0	0	0
T40	32863	2	0	0
T41	104462	0	0	0
T49	0	3	0	0
T50	0	3	0	0
T53	0	1	0	0
T58	92518	0	0	0
T59	19485	0	0	0
T69	349649	0	0	0
T70	13419	0	0	0
T74	299327	3	0	0
T75	83297	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0
T85	0	3	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T89	370302	0	0	0
T90	21105	0	0	0
T91	1507	0	0	0
T92	89702	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5024	0	0
T11	172716	1367	0	0
T12	0	715	0	0
T13	0	746	0	0
T25	0	737	0	0
T26	0	1459	0	0
T27	3243448	0	0	0
T28	3825496	0	0	0
T29	1829100	0	0	0
T30	220304	0	0	0
T31	133880	0	0	0
T32	43212	0	0	0
T33	822072	0	0	0
T34	87020	0	0	0
T35	77280	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4184	0	0
T11	172716	1127	0	0
T12	0	595	0	0
T13	0	626	0	0
T25	0	617	0	0
T26	0	1219	0	0
T27	3243448	0	0	0
T28	3825496	0	0	0
T29	1829100	0	0	0
T30	220304	0	0	0
T31	133880	0	0	0
T32	43212	0	0	0
T33	822072	0	0	0
T34	87020	0	0	0
T35	77280	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	95028	94756	0	0
T2	1345344	1345312	0	0
T3	66816	66552	0	0
T4	3725952	3725644	0	0
T5	274872	274100	0	0
T6	644964	644744	0	0
T7	750760	750388	0	0
T8	126720	126348	0	0
T9	208572	208248	0	0
T10	1520912	1520612	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	95028	94756	0	0
T2	1345344	1345312	0	0
T3	66816	66552	0	0
T4	3725952	3725644	0	0
T5	274872	274100	0	0
T6	644964	644744	0	0
T7	750760	750388	0	0
T8	126720	126348	0	0
T9	208572	208248	0	0
T10	1520912	1520612	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T8
1	0	1	Covered	T4,T6,T7
1	1	0	Covered	T1,T6,T10
1	1	1	Covered	T6,T8,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T10,T14,T24
1	0	Covered	T10,T15,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T8,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Not Covered
1	1	Covered	T10,T14,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T4,T6,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T6,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T43,T69

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T2,T6,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T6,T8,T10
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T93,T94,T95
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T84,T96
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T97,T98,T87
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T99,T100,T101
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T8,T75
TimeoutSt->Phase0St	172	Covered	T10,T14,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T14,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T75
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T102,T103,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T96,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T97,T98,T87
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T99,T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711619072	218	0	0
CheckAccumTrig0_A	711619072	496	0	0
CheckAccumTrig1_A	711619072	23	0	0
CheckClr_A	711619072	203	0	0
CheckEn_A	711479820	323516965	0	0
CheckPhase0_A	711619072	560	0	0
CheckPhase1_A	711619072	541	0	0
CheckPhase2_A	711619072	530	0	0
CheckPhase3_A	711619072	525	0	0
CheckTimeout0_A	711619072	521	0	0
CheckTimeoutSt1_A	711619072	59702	0	0
CheckTimeoutSt2_A	711619072	443	0	0
CheckTimeoutStTrig_A	711619072	55	0	0
ErrorStAllEscAsserted_A	711619072	1269	0	0
ErrorStIsTerminal_A	711619072	1059	0	0
EscStateOut_A	711478397	711407211	0	0
u_state_regs_A	711619072	711457757	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	218	0	0
T11	43179	47	0	0
T12	0	43	0	0
T13	0	29	0	0
T25	0	34	0	0
T26	0	65	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	496	0	0
T1	23757	1	0	0
T2	336336	2	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	3	0	0
T15	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	23	0	0
T10	380228	2	0	0
T14	30204	0	0	0
T15	0	1	0	0
T20	0	1	0	0
T27	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	32863	0	0	0
T41	104462	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	92518	0	0	0
T59	19485	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	203	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	0	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	5	0	0
T15	0	2	0	0
T21	0	1	0	0
T43	0	3	0	0
T67	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711479820	323516965	0	0
T1	23757	18472	0	0
T2	336336	37184	0	0
T3	16704	10946	0	0
T4	931488	924686	0	0
T5	68718	707	0	0
T6	161241	130069	0	0
T7	187690	177497	0	0
T8	31680	1638	0	0
T9	52143	48345	0	0
T10	380228	477149	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	560	0	0
T1	23757	1	0	0
T2	336336	2	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	9	0	0
T14	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	541	0	0
T1	23757	1	0	0
T2	336336	2	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	9	0	0
T14	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	530	0	0
T1	23757	1	0	0
T2	336336	2	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	9	0	0
T14	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	525	0	0
T1	23757	1	0	0
T2	336336	2	0	0
T3	16704	0	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	9	0	0
T14	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	521	0	0
T6	161241	2	0	0
T7	187690	0	0	0
T8	31680	7	0	0
T9	52143	0	0	0
T10	380228	6	0	0
T14	30204	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	0	3	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T64	0	7	0	0
T70	0	1	0	0
T75	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	59702	0	0
T6	161241	116	0	0
T7	187690	0	0	0
T8	31680	467	0	0
T9	52143	0	0	0
T10	380228	864	0	0
T14	30204	177	0	0
T15	0	3	0	0
T16	0	149	0	0
T24	0	50	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T64	0	1685	0	0
T70	0	41	0	0
T75	0	822	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	443	0	0
T6	161241	2	0	0
T7	187690	0	0	0
T8	31680	7	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	1	0	0
T20	0	2	0	0
T24	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T64	0	7	0	0
T70	0	1	0	0
T75	0	5	0	0
T80	0	2	0	0
T81	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	55	0	0
T10	380228	4	0	0
T14	30204	1	0	0
T20	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	32863	0	0	0
T41	104462	0	0	0
T49	0	2	0	0
T50	0	1	0	0
T58	92518	0	0	0
T59	19485	0	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1269	0	0
T11	43179	323	0	0
T12	0	191	0	0
T13	0	213	0	0
T25	0	194	0	0
T26	0	348	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1059	0	0
T11	43179	263	0	0
T12	0	161	0	0
T13	0	183	0	0
T25	0	164	0	0
T26	0	288	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711478397	711407211	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	711457757	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T2,T4,T7
1	1	0	Covered	T6,T8,T10
1	1	1	Covered	T6,T8,T38

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T38
0	1	Covered	T74,T78,T79
1	0	Covered	T16,T24,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T8,T38
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T24,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T38
1	0	Covered	T105
1	1	Covered	T74,T78,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T10,T36

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T6,T8,T38

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T6,T8,T38
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T10,T19,T20
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T22,T44
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T15,T24
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T106,T107
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T6,T10
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T8,T38
TimeoutSt->Phase0St	172	Covered	T74,T16,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T38
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T74,T16,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T38
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T38
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T10,T19,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T22,T44
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T15,T24
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T106,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711619072	244	0	0
CheckAccumTrig0_A	711619072	873	0	0
CheckAccumTrig1_A	711619072	45	0	0
CheckClr_A	711619072	418	0	0
CheckEn_A	711479820	276515311	0	0
CheckPhase0_A	711619072	951	0	0
CheckPhase1_A	711619072	926	0	0
CheckPhase2_A	711619072	908	0	0
CheckPhase3_A	711619072	894	0	0
CheckTimeout0_A	711619072	791	0	0
CheckTimeoutSt1_A	711619072	102261	0	0
CheckTimeoutSt2_A	711619072	694	0	0
CheckTimeoutStTrig_A	711619072	51	0	0
ErrorStAllEscAsserted_A	711619072	1229	0	0
ErrorStIsTerminal_A	711619072	1019	0	0
EscStateOut_A	711478397	711407211	0	0
u_state_regs_A	711619072	711457757	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	244	0	0
T11	43179	77	0	0
T12	0	42	0	0
T13	0	35	0	0
T25	0	42	0	0
T26	0	48	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	873	0	0
T1	23757	1	0	0
T2	336336	5	0	0
T3	16704	1	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	7	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	45	0	0
T16	124681	1	0	0
T20	0	1	0	0
T23	967460	0	0	0
T24	512678	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	4555	0	0	0
T61	89251	0	0	0
T62	124562	0	0	0
T63	60270	0	0	0
T64	93168	0	0	0
T65	39940	0	0	0
T66	1555	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	418	0	0
T2	336336	4	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	0	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	4	0	0
T15	0	7	0	0
T19	0	3	0	0
T21	0	1	0	0
T23	0	2	0	0
T24	0	6	0	0
T36	406696	0	0	0
T38	0	1	0	0
T68	0	4	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711479820	276515311	0	0
T1	23757	2295	0	0
T2	336336	7152	0	0
T3	16704	8766	0	0
T4	931488	4565	0	0
T5	68718	703	0	0
T6	161241	209846	0	0
T7	187690	1846	0	0
T8	31680	28762	0	0
T9	52143	9362	0	0
T10	380228	326172	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	951	0	0
T1	23757	1	0	0
T2	336336	5	0	0
T3	16704	1	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	6	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	926	0	0
T1	23757	1	0	0
T2	336336	5	0	0
T3	16704	1	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	6	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	908	0	0
T1	23757	1	0	0
T2	336336	4	0	0
T3	16704	1	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	6	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	894	0	0
T1	23757	1	0	0
T2	336336	4	0	0
T3	16704	1	0	0
T4	931488	1	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	6	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	791	0	0
T6	161241	17	0	0
T7	187690	0	0	0
T8	31680	2	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T24	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	1	0	0
T39	2994	0	0	0
T74	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	102261	0	0
T6	161241	992	0	0
T7	187690	0	0	0
T8	31680	114	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T19	0	55	0	0
T24	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	149	0	0
T39	2994	0	0	0
T44	0	7	0	0
T74	0	1518	0	0
T77	0	181	0	0
T78	0	97	0	0
T79	0	88	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	694	0	0
T6	161241	17	0	0
T7	187690	0	0	0
T8	31680	2	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T19	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	1	0	0
T39	2994	0	0	0
T47	0	2	0	0
T48	0	6	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	4	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	51	0	0
T19	34007	0	0	0
T21	406165	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T69	349649	0	0	0
T70	13419	0	0	0
T74	299327	1	0	0
T75	83297	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	3	0	0
T89	370302	0	0	0
T90	21105	0	0	0
T91	1507	0	0	0
T92	89702	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1229	0	0
T11	43179	337	0	0
T12	0	156	0	0
T13	0	187	0	0
T25	0	179	0	0
T26	0	370	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1019	0	0
T11	43179	277	0	0
T12	0	126	0	0
T13	0	157	0	0
T25	0	149	0	0
T26	0	310	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711478397	711407211	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	711457757	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T8
1	0	1	Covered	T4,T6,T10
1	1	0	Covered	T6,T8,T10
1	1	1	Covered	T6,T10,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T14
0	1	Covered	T6,T10,T40
1	0	Covered	T23,T45,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T10,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T45,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T14
1	0	Covered	T6
1	1	Covered	T6,T10,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T10,T37,T91

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T6,T9,T36

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T9
1	Covered	T2,T6,T10

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T6,T10

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T6
Phase1St	198	Covered	T1,T2,T6
Phase2St	215	Covered	T1,T2,T6
Phase3St	233	Covered	T1,T2,T6
TerminalSt	249	Covered	T1,T2,T6
TimeoutSt	159	Covered	T6,T10,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T6
IdleSt->TimeoutSt	159	Covered	T6,T10,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T108,T93,T109
Phase0St->Phase1St	198	Covered	T1,T2,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T110,T111
Phase1St->Phase2St	215	Covered	T1,T2,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T45,T112
Phase2St->Phase3St	233	Covered	T1,T2,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T87,T113
Phase3St->TerminalSt	249	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T10,T40
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T10,T14
TimeoutSt->Phase0St	172	Covered	T6,T10,T40

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T40
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T108,T109,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T6,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T110,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T45,T112
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T87,T113
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T10,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711619072	254	0	0
CheckAccumTrig0_A	711619072	467	0	0
CheckAccumTrig1_A	711619072	17	0	0
CheckClr_A	711619072	182	0	0
CheckEn_A	711479820	298223601	0	0
CheckPhase0_A	711619072	529	0	0
CheckPhase1_A	711619072	522	0	0
CheckPhase2_A	711619072	512	0	0
CheckPhase3_A	711619072	506	0	0
CheckTimeout0_A	711619072	1100	0	0
CheckTimeoutSt1_A	711619072	142404	0	0
CheckTimeoutSt2_A	711619072	1030	0	0
CheckTimeoutStTrig_A	711619072	50	0	0
ErrorStAllEscAsserted_A	711619072	1303	0	0
ErrorStIsTerminal_A	711619072	1093	0	0
EscStateOut_A	711478397	711407211	0	0
u_state_regs_A	711619072	711457757	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	254	0	0
T11	43179	87	0	0
T12	0	31	0	0
T13	0	23	0	0
T25	0	36	0	0
T26	0	77	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	467	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	7	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	17	0	0
T20	0	1	0	0
T22	63742	0	0	0
T23	967460	1	0	0
T24	512678	0	0	0
T45	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T60	4555	0	0	0
T61	89251	0	0	0
T62	124562	0	0	0
T63	60270	0	0	0
T64	93168	0	0	0
T65	39940	0	0	0
T66	1555	0	0	0
T115	0	3	0	0
T116	0	1	0	0
T117	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	182	0	0
T6	161241	6	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	2	0	0
T14	30204	0	0	0
T20	0	3	0	0
T23	0	2	0	0
T24	0	3	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	0	1	0	0
T45	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T118	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711479820	298223601	0	0
T1	23757	2333	0	0
T2	336336	2695	0	0
T3	16704	16637	0	0
T4	931488	928430	0	0
T5	68718	711	0	0
T6	161241	299868	0	0
T7	187690	186274	0	0
T8	31680	28398	0	0
T9	52143	5777	0	0
T10	380228	328132	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	529	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	8	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	522	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	6	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	512	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	5	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	506	0	0
T1	23757	1	0	0
T2	336336	1	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	5	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1100	0	0
T6	161241	2	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	2	0	0
T14	30204	3	0	0
T23	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	0	3	0	0
T64	0	1	0	0
T71	0	2	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	142404	0	0
T6	161241	48	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	66	0	0
T14	30204	591	0	0
T23	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	0	115	0	0
T64	0	316	0	0
T71	0	108	0	0
T74	0	754	0	0
T75	0	68	0	0
T76	0	523	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1030	0	0
T6	161241	1	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	1	0	0
T14	30204	3	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	0	1	0	0
T64	0	1	0	0
T71	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T76	0	7	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	50	0	0
T6	161241	1	0	0
T7	187690	0	0	0
T8	31680	0	0	0
T9	52143	0	0	0
T10	380228	1	0	0
T14	30204	0	0	0
T24	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	0	2	0	0
T47	0	2	0	0
T50	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1303	0	0
T11	43179	359	0	0
T12	0	200	0	0
T13	0	181	0	0
T25	0	197	0	0
T26	0	366	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1093	0	0
T11	43179	299	0	0
T12	0	170	0	0
T13	0	151	0	0
T25	0	167	0	0
T26	0	306	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711478397	711407211	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	711457757	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T8
1	0	1	Covered	T6,T7,T10
1	1	0	Covered	T6,T8,T10
1	1	1	Covered	T6,T8,T74

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T74
0	1	Covered	T8,T75,T16
1	0	Covered	T120,T121,T122

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T8,T74
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T120,T121,T122

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T74
1	0	Covered	T17,T18
1	1	Covered	T8,T75,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T8,T36

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T6,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T7,T10,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T38,T41

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T10,T38

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T6,T7
Phase1St	198	Covered	T1,T6,T7
Phase2St	215	Covered	T1,T6,T7
Phase3St	233	Covered	T1,T6,T7
TerminalSt	249	Covered	T1,T6,T7
TimeoutSt	159	Covered	T6,T8,T74

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T6,T7
IdleSt->TimeoutSt	159	Covered	T6,T8,T74
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T48,T123,T100
Phase0St->Phase1St	198	Covered	T1,T6,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T38,T55,T124
Phase1St->Phase2St	215	Covered	T1,T6,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T53,T125,T126
Phase2St->Phase3St	233	Covered	T1,T6,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T21,T53,T35
Phase3St->TerminalSt	249	Covered	T1,T6,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T9,T10
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T8,T74
TimeoutSt->Phase0St	172	Covered	T8,T75,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T74
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T75,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T74
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T126,T127,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T6,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T6,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T38,T55,T124
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T6,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T6,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T53,T125,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T6,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T6,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T53,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T6,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T6,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T38,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T6,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711619072	236	0	0
CheckAccumTrig0_A	711619072	511	0	0
CheckAccumTrig1_A	711619072	17	0	0
CheckClr_A	711619072	238	0	0
CheckEn_A	711479820	340002903	0	0
CheckPhase0_A	711619072	581	0	0
CheckPhase1_A	711619072	574	0	0
CheckPhase2_A	711619072	567	0	0
CheckPhase3_A	711619072	556	0	0
CheckTimeout0_A	711619072	804	0	0
CheckTimeoutSt1_A	711619072	97214	0	0
CheckTimeoutSt2_A	711619072	718	0	0
CheckTimeoutStTrig_A	711619072	66	0	0
ErrorStAllEscAsserted_A	711619072	1223	0	0
ErrorStIsTerminal_A	711619072	1013	0	0
EscStateOut_A	711478397	711407211	0	0
u_state_regs_A	711619072	711457757	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	236	0	0
T11	43179	62	0	0
T12	0	43	0	0
T13	0	27	0	0
T25	0	33	0	0
T26	0	71	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	511	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	0	0	0
T9	52143	1	0	0
T10	380228	2	0	0
T36	0	1	0	0
T38	0	6	0	0
T40	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	17	0	0
T85	40318	0	0	0
T86	24516	0	0	0
T97	257119	0	0	0
T120	392595	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	8544	0	0	0
T135	504916	0	0	0
T136	3643	0	0	0
T137	60393	0	0	0
T138	268170	0	0	0
T139	6407	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	238	0	0
T9	52143	1	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	5	0	0
T39	2994	0	0	0
T40	32863	2	0	0
T41	104462	1	0	0
T58	92518	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T75	0	1	0	0
T140	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711479820	340002903	0	0
T1	23757	2346	0	0
T2	336336	336328	0	0
T3	16704	16637	0	0
T4	931488	931410	0	0
T5	68718	715	0	0
T6	161241	128158	0	0
T7	187690	2926	0	0
T8	31680	2730	0	0
T9	52143	46721	0	0
T10	380228	163980	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	581	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	1	0	0
T9	52143	1	0	0
T10	380228	2	0	0
T36	0	1	0	0
T38	0	6	0	0
T40	0	3	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	574	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	1	0	0
T9	52143	1	0	0
T10	380228	2	0	0
T36	0	1	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	567	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	1	0	0
T9	52143	1	0	0
T10	380228	2	0	0
T36	0	1	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	556	0	0
T1	23757	1	0	0
T2	336336	0	0	0
T3	16704	0	0	0
T4	931488	0	0	0
T5	68718	0	0	0
T6	161241	3	0	0
T7	187690	1	0	0
T8	31680	1	0	0
T9	52143	1	0	0
T10	380228	2	0	0
T36	0	1	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	804	0	0
T6	161241	2	0	0
T7	187690	0	0	0
T8	31680	2	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	2	0	0
T24	0	2	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T46	0	3	0	0
T64	0	1	0	0
T74	0	46	0	0
T75	0	2	0	0
T78	0	1	0	0
T80	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	97214	0	0
T6	161241	103	0	0
T7	187690	0	0	0
T8	31680	102	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	99	0	0
T24	0	320	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T46	0	135	0	0
T64	0	184	0	0
T74	0	3416	0	0
T75	0	161	0	0
T78	0	55	0	0
T80	0	1831	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	718	0	0
T6	161241	2	0	0
T7	187690	0	0	0
T8	31680	1	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	1	0	0
T24	0	2	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T46	0	3	0	0
T74	0	46	0	0
T80	0	8	0	0
T82	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	66	0	0
T8	31680	1	0	0
T9	52143	0	0	0
T10	380228	0	0	0
T14	30204	0	0	0
T16	0	1	0	0
T36	406696	0	0	0
T37	92851	0	0	0
T38	463076	0	0	0
T39	2994	0	0	0
T40	32863	0	0	0
T50	0	4	0	0
T53	0	1	0	0
T58	92518	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T78	0	1	0	0
T94	0	1	0	0
T120	0	1	0	0
T135	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1223	0	0
T11	43179	348	0	0
T12	0	168	0	0
T13	0	165	0	0
T25	0	167	0	0
T26	0	375	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	1013	0	0
T11	43179	288	0	0
T12	0	138	0	0
T13	0	135	0	0
T25	0	137	0	0
T26	0	315	0	0
T27	810862	0	0	0
T28	956374	0	0	0
T29	457275	0	0	0
T30	55076	0	0	0
T31	33470	0	0	0
T32	10803	0	0	0
T33	205518	0	0	0
T34	21755	0	0	0
T35	19320	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711478397	711407211	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711619072	711457757	0	0
T1	23757	23689	0	0
T2	336336	336328	0	0
T3	16704	16638	0	0
T4	931488	931411	0	0
T5	68718	68525	0	0
T6	161241	161186	0	0
T7	187690	187597	0	0
T8	31680	31587	0	0
T9	52143	52062	0	0
T10	380228	380153	0	0