Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T193,T194
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13580	0	0
DisabledNoTrigBkwd_A	2147483647	856015	0	0
DisabledNoTrigFwd_A	2147483647	1393459362	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13580	0	0
T17	141954	0	0	0
T26	313027	0	0	0
T34	855893	0	0	0
T55	1627	653	0	0
T64	133376	0	0	0
T72	315859	0	0	0
T80	158487	0	0	0
T81	15227	0	0	0
T82	31542	0	0	0
T182	12839	0	0	0
T193	0	296	0	0
T194	0	708	0	0
T195	1144	389	0	0
T196	3120	808	0	0
T197	1694	729	0	0
T198	0	786	0	0
T199	0	877	0	0
T200	0	674	0	0
T201	0	449	0	0
T202	0	381	0	0
T203	0	716	0	0
T204	0	900	0	0
T205	0	418	0	0
T206	0	884	0	0
T207	0	1062	0	0
T208	0	563	0	0
T209	0	723	0	0
T210	0	638	0	0
T211	0	926	0	0
T212	42189	0	0	0
T213	522984	0	0	0
T214	42428	0	0	0
T215	98920	0	0	0
T216	247783	0	0	0
T217	39626	0	0	0
T218	5380	0	0	0
T219	17797	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	856015	0	0
T1	1048188	605	0	0
T2	109408	1	0	0
T3	2366544	4	0	0
T4	3739964	4321	0	0
T5	3959248	4473	0	0
T6	1064028	1820	0	0
T10	188176	0	0	0
T13	1885304	6494	0	0
T14	0	6504	0	0
T16	0	1007	0	0
T18	142232	8	0	0
T19	1087804	240	0	0
T20	0	436	0	0
T22	0	1	0	0
T23	0	9301	0	0
T24	0	1513	0	0
T26	0	2341	0	0
T33	0	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393459362	0	0
T1	1048188	300043	0	0
T2	109408	83864	0	0
T3	2366544	885548	0	0
T4	3739964	1872603	0	0
T5	3959248	1979719	0	0
T6	1064028	826932	0	0
T10	188176	84988	0	0
T13	1885304	550870	0	0
T18	142232	103209	0	0
T19	1087804	1230206	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T196,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693566296	4326	0	0
DisabledNoTrigBkwd_A	693566296	224191	0	0
DisabledNoTrigFwd_A	693566296	340965123	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	4326	0	0
T195	1144	389	0	0
T196	3120	808	0	0
T205	0	418	0	0
T207	0	1062	0	0
T209	0	723	0	0
T211	0	926	0	0
T212	42189	0	0	0
T213	522984	0	0	0
T214	42428	0	0	0
T215	98920	0	0	0
T216	247783	0	0	0
T217	39626	0	0	0
T218	5380	0	0	0
T219	17797	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	224191	0	0
T1	262047	36	0	0
T2	27352	1	0	0
T3	591636	4	0	0
T4	934991	2273	0	0
T5	989812	2480	0	0
T6	266007	1808	0	0
T10	47044	0	0	0
T13	471326	2073	0	0
T18	35558	0	0	0
T19	271951	198	0	0
T20	0	197	0	0
T23	0	1650	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	340965123	0	0
T1	262047	238720	0	0
T2	27352	2072	0	0
T3	591636	83280	0	0
T4	934991	582	0	0
T5	989812	1612	0	0
T6	266007	34266	0	0
T10	47044	21247	0	0
T13	471326	18803	0	0
T18	35558	35495	0	0
T19	271951	141416	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T193,T204
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693566296	3296	0	0
DisabledNoTrigBkwd_A	693566296	209280	0	0
DisabledNoTrigFwd_A	693566296	320612427	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	3296	0	0
T17	141954	0	0	0
T26	313027	0	0	0
T34	855893	0	0	0
T55	1627	653	0	0
T64	133376	0	0	0
T72	315859	0	0	0
T80	158487	0	0	0
T81	15227	0	0	0
T82	31542	0	0	0
T182	12839	0	0	0
T193	0	296	0	0
T204	0	900	0	0
T206	0	884	0	0
T208	0	563	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	209280	0	0
T1	262047	178	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2040	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	2307	0	0
T18	35558	0	0	0
T19	271951	1	0	0
T20	0	125	0	0
T22	0	1	0	0
T23	0	24	0	0
T24	0	2	0	0
T33	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	320612427	0	0
T1	262047	20421	0	0
T2	27352	27264	0	0
T3	591636	448326	0	0
T4	934991	7771	0	0
T5	989812	987765	0	0
T6	266007	263515	0	0
T10	47044	21247	0	0
T13	471326	8284	0	0
T18	35558	35495	0	0
T19	271951	617125	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T201
1	1	Covered	T1,T18,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693566296	2345	0	0
DisabledNoTrigBkwd_A	693566296	213285	0	0
DisabledNoTrigFwd_A	693566296	358557815	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	2345	0	0
T100	605231	0	0	0
T197	1694	729	0	0
T198	0	786	0	0
T201	0	449	0	0
T202	0	381	0	0
T220	36922	0	0	0
T221	84357	0	0	0
T222	39764	0	0	0
T223	224484	0	0	0
T224	5412	0	0	0
T225	499657	0	0	0
T226	163671	0	0	0
T227	113541	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	213285	0	0
T1	262047	219	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	1993	0	0
T6	266007	6	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	1007	0	0
T18	35558	8	0	0
T19	271951	39	0	0
T23	0	6541	0	0
T24	0	6	0	0
T26	0	2341	0	0
T33	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	358557815	0	0
T1	262047	30142	0	0
T2	27352	27264	0	0
T3	591636	726	0	0
T4	934991	934899	0	0
T5	989812	590	0	0
T6	266007	263689	0	0
T10	47044	21247	0	0
T13	471326	470262	0	0
T18	35558	3491	0	0
T19	271951	268321	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T3,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T199,T200
1	1	Covered	T1,T3,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693566296	3613	0	0
DisabledNoTrigBkwd_A	693566296	209259	0	0
DisabledNoTrigFwd_A	693566296	373323997	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	3613	0	0
T44	996769	0	0	0
T85	16947	0	0	0
T86	13050	0	0	0
T194	1472	708	0	0
T199	0	877	0	0
T200	0	674	0	0
T203	0	716	0	0
T210	0	638	0	0
T228	17106	0	0	0
T229	847878	0	0	0
T230	24981	0	0	0
T231	68209	0	0	0
T232	18275	0	0	0
T233	795914	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	209259	0	0
T1	262047	172	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	8	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	2114	0	0
T14	0	6504	0	0
T18	35558	0	0	0
T19	271951	2	0	0
T20	0	114	0	0
T23	0	1086	0	0
T24	0	1505	0	0
T33	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	373323997	0	0
T1	262047	10760	0	0
T2	27352	27264	0	0
T3	591636	353216	0	0
T4	934991	929351	0	0
T5	989812	989752	0	0
T6	266007	265462	0	0
T10	47044	21247	0	0
T13	471326	53521	0	0
T18	35558	28728	0	0
T19	271951	203344	0	0