Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T21
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T19
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T19,T22
1	1	1	Covered	T1,T2,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T19,T23
1	0	Covered	T23,T24,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Not Covered
1	1	Covered	T1,T19,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T18
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T19
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T19,T24,T25
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T19,T24
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T26,T27,T28
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T24,T29
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T19
TimeoutSt->Phase0St	172	Covered	T1,T19,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T25,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T19,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T24,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1218	0	0
CheckAccumTrig0_A	2147483647	2446	0	0
CheckAccumTrig1_A	2147483647	110	0	0
CheckClr_A	2147483647	1085	0	0
CheckEn_A	2147483647	1054117877	0	0
CheckPhase0_A	2147483647	2756	0	0
CheckPhase1_A	2147483647	2684	0	0
CheckPhase2_A	2147483647	2616	0	0
CheckPhase3_A	2147483647	2567	0	0
CheckTimeout0_A	2147483647	4587	0	0
CheckTimeoutSt1_A	2147483647	517146	0	0
CheckTimeoutSt2_A	2147483647	4218	0	0
CheckTimeoutStTrig_A	2147483647	251	0	0
ErrorStAllEscAsserted_A	2147483647	5926	0	0
ErrorStIsTerminal_A	2147483647	4966	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1218	0	0
T10	188176	348	0	0
T11	0	165	0	0
T12	0	285	0	0
T13	1885304	0	0	0
T14	1736656	0	0	0
T15	152524	0	0	0
T16	1387596	0	0	0
T20	1565292	0	0	0
T22	128056	0	0	0
T23	1261604	0	0	0
T24	2484180	0	0	0
T31	0	134	0	0
T32	0	286	0	0
T33	71856	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T1	1048188	10	0	0
T2	109408	1	0	0
T3	2366544	1	0	0
T4	3739964	4	0	0
T5	3959248	5	0	0
T6	1064028	7	0	0
T10	188176	0	0	0
T13	1885304	3	0	0
T14	0	4	0	0
T16	0	2	0	0
T18	142232	1	0	0
T19	1087804	11	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	7	0	0
T24	0	7	0	0
T26	0	2	0	0
T33	0	4	0	0
T34	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110	0	0
T7	1429102	0	0	0
T15	76262	0	0	0
T16	693798	0	0	0
T17	283908	0	0	0
T23	315401	1	0	0
T24	1242090	1	0	0
T25	0	2	0	0
T26	313027	0	0	0
T33	35928	0	0	0
T35	0	1	0	0
T36	295809	1	0	0
T37	90918	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	128174	0	0	0
T54	97202	0	0	0
T55	3254	0	0	0
T56	68745	0	0	0
T57	175936	0	0	0
T58	33275	0	0	0
T59	278289	0	0	0
T60	65636	0	0	0
T61	35204	0	0	0
T62	177900	0	0	0
T63	167044	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1085	0	0
T1	262047	0	0	0
T2	54704	1	0	0
T3	1183272	0	0	0
T4	1869982	0	0	0
T5	2969436	3	0	0
T6	1064028	3	0	0
T10	188176	0	0	0
T13	1885304	0	0	0
T14	1302492	0	0	0
T15	38131	0	0	0
T16	0	1	0	0
T18	71116	0	0	0
T19	1087804	6	0	0
T20	782646	0	0	0
T22	64028	1	0	0
T23	630802	3	0	0
T24	1242090	17	0	0
T26	0	6	0	0
T27	0	6	0	0
T28	0	4	0	0
T29	0	1	0	0
T34	0	5	0	0
T64	0	1	0	0
T65	0	4	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	3	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1054117877	0	0
T1	1048188	273604	0	0
T2	109408	83861	0	0
T3	2366544	885547	0	0
T4	3739964	943845	0	0
T5	3959248	1979717	0	0
T6	1064028	314553	0	0
T10	2312	2016	0	0
T13	1885304	517834	0	0
T18	142232	103206	0	0
T19	1087804	1155543	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2756	0	0
T1	1048188	11	0	0
T2	109408	1	0	0
T3	2366544	1	0	0
T4	3739964	4	0	0
T5	3959248	5	0	0
T6	1064028	7	0	0
T10	188176	0	0	0
T13	1885304	3	0	0
T14	0	4	0	0
T16	0	2	0	0
T18	142232	1	0	0
T19	1087804	13	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	12	0	0
T24	0	8	0	0
T26	0	2	0	0
T33	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2684	0	0
T1	1048188	11	0	0
T2	109408	1	0	0
T3	2366544	1	0	0
T4	3739964	4	0	0
T5	3959248	4	0	0
T6	1064028	7	0	0
T10	188176	0	0	0
T13	1885304	3	0	0
T14	0	4	0	0
T16	0	2	0	0
T18	142232	1	0	0
T19	1087804	11	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	12	0	0
T24	0	8	0	0
T26	0	2	0	0
T33	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2616	0	0
T1	1048188	11	0	0
T2	109408	1	0	0
T3	2366544	1	0	0
T4	3739964	4	0	0
T5	3959248	4	0	0
T6	1064028	7	0	0
T10	188176	0	0	0
T13	1885304	3	0	0
T14	0	4	0	0
T16	0	2	0	0
T18	142232	1	0	0
T19	1087804	11	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	12	0	0
T24	0	8	0	0
T26	0	1	0	0
T33	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2567	0	0
T1	1048188	11	0	0
T2	109408	1	0	0
T3	2366544	1	0	0
T4	3739964	4	0	0
T5	3959248	4	0	0
T6	1064028	6	0	0
T10	188176	0	0	0
T13	1885304	3	0	0
T14	0	4	0	0
T16	0	2	0	0
T18	142232	1	0	0
T19	1087804	11	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	12	0	0
T24	0	8	0	0
T26	0	1	0	0
T33	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4587	0	0
T1	524094	2	0	0
T2	82056	1	0	0
T3	1774908	0	0	0
T4	2804973	0	0	0
T5	2969436	0	0	0
T6	798021	0	0	0
T10	188176	0	0	0
T13	1885304	0	0	0
T14	868328	0	0	0
T15	38131	0	0	0
T16	0	2	0	0
T18	106674	0	0	0
T19	1087804	36	0	0
T20	391323	0	0	0
T22	32014	1	0	0
T23	315401	8	0	0
T24	621045	2	0	0
T25	0	2	0	0
T28	0	2	0	0
T33	17964	0	0	0
T34	0	18	0	0
T35	0	1	0	0
T53	0	7	0	0
T64	0	11	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	15	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	517146	0	0
T1	524094	684	0	0
T2	82056	159	0	0
T3	1774908	0	0	0
T4	2804973	0	0	0
T5	2969436	0	0	0
T6	798021	0	0	0
T10	188176	0	0	0
T13	1885304	0	0	0
T14	868328	0	0	0
T15	38131	0	0	0
T16	0	123	0	0
T18	106674	0	0	0
T19	1087804	10661	0	0
T20	391323	0	0	0
T22	32014	176	0	0
T23	315401	1105	0	0
T24	621045	76	0	0
T25	0	14	0	0
T28	0	119	0	0
T33	17964	0	0	0
T34	0	3288	0	0
T53	0	973	0	0
T64	0	637	0	0
T70	0	229	0	0
T71	0	167	0	0
T72	0	36	0	0
T73	0	3278	0	0
T74	0	142	0	0
T75	0	131	0	0
T76	0	268	0	0
T77	0	87	0	0
T78	0	191	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4218	0	0
T1	262047	1	0	0
T2	54704	1	0	0
T3	1183272	0	0	0
T4	1869982	0	0	0
T5	1979624	0	0	0
T6	532014	0	0	0
T10	94088	0	0	0
T13	942652	0	0	0
T14	434164	0	0	0
T16	0	2	0	0
T17	141954	0	0	0
T18	71116	0	0	0
T19	543902	20	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	313027	0	0	0
T28	0	1	0	0
T34	855893	15	0	0
T36	0	31	0	0
T38	0	3	0	0
T53	64087	7	0	0
T54	48601	0	0	0
T55	1627	0	0	0
T58	0	2	0	0
T64	133376	9	0	0
T71	0	1	0	0
T73	0	14	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	158487	0	0	0
T81	15227	0	0	0
T82	31542	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	188176	0	0	0
T13	1885304	0	0	0
T14	1302492	0	0	0
T15	114393	0	0	0
T18	35558	0	0	0
T19	1087804	4	0	0
T20	1173969	0	0	0
T22	96042	0	0	0
T23	946203	4	0	0
T24	1863135	0	0	0
T33	53892	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T58	0	1	0	0
T60	0	2	0	0
T64	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	5	0	0
T89	0	1	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5926	0	0
T10	188176	1492	0	0
T11	0	735	0	0
T12	0	1515	0	0
T13	1885304	0	0	0
T14	1736656	0	0	0
T15	152524	0	0	0
T16	1387596	0	0	0
T20	1565292	0	0	0
T22	128056	0	0	0
T23	1261604	0	0	0
T24	2484180	0	0	0
T31	0	724	0	0
T32	0	1460	0	0
T33	71856	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4966	0	0
T10	188176	1252	0	0
T11	0	615	0	0
T12	0	1275	0	0
T13	1885304	0	0	0
T14	1736656	0	0	0
T15	152524	0	0	0
T16	1387596	0	0	0
T20	1565292	0	0	0
T22	128056	0	0	0
T23	1261604	0	0	0
T24	2484180	0	0	0
T31	0	604	0	0
T32	0	1220	0	0
T33	71856	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1048188	1047048	0	0
T2	109408	109056	0	0
T3	2366544	2366224	0	0
T4	3739964	3739596	0	0
T5	3959248	3959008	0	0
T6	1064028	1064008	0	0
T10	292	0	0	0
T13	1885304	1885272	0	0
T14	0	1736616	0	0
T18	142232	141980	0	0
T19	1087804	1087764	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1048188	1047048	0	0
T2	109408	109056	0	0
T3	2366544	2366224	0	0
T4	3739964	3739596	0	0
T5	3959248	3959008	0	0
T6	1064028	1064008	0	0
T10	188176	84988	0	0
T13	1885304	1885272	0	0
T18	142232	141980	0	0
T19	1087804	1087764	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T19
1	0	1	Covered	T3,T5,T19
1	1	0	Covered	T19,T24,T53
1	1	1	Covered	T2,T19,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T23
0	1	Covered	T19,T23,T70
1	0	Covered	T23,T35,T39

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T19,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T35,T39

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T23
1	0	Not Covered
1	1	Covered	T19,T23,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T19,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T5,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T19,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T19,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T30,T91
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T19,T24
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T77,T92,T91
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T93,T92
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T23
TimeoutSt->Phase0St	172	Covered	T19,T23,T70

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T23,T70
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T30,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T24,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T77,T92,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T93,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693566296	271	0	0
CheckAccumTrig0_A	693566296	858	0	0
CheckAccumTrig1_A	693566296	42	0	0
CheckClr_A	693566296	415	0	0
CheckEn_A	693400511	228547725	0	0
CheckPhase0_A	693566296	955	0	0
CheckPhase1_A	693566296	928	0	0
CheckPhase2_A	693566296	908	0	0
CheckPhase3_A	693566296	892	0	0
CheckTimeout0_A	693566296	771	0	0
CheckTimeoutSt1_A	693566296	86205	0	0
CheckTimeoutSt2_A	693566296	656	0	0
CheckTimeoutStTrig_A	693566296	72	0	0
ErrorStAllEscAsserted_A	693566296	1495	0	0
ErrorStIsTerminal_A	693566296	1255	0	0
EscStateOut_A	693399168	693329590	0	0
u_state_regs_A	693566296	693394925	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	271	0	0
T10	47044	90	0	0
T11	0	49	0	0
T12	0	47	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	24	0	0
T32	0	61	0	0
T33	17964	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	858	0	0
T1	262047	2	0	0
T2	27352	1	0	0
T3	591636	1	0	0
T4	934991	1	0	0
T5	989812	3	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	42	0	0
T7	714551	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T17	141954	0	0	0
T23	315401	1	0	0
T24	621045	0	0	0
T33	17964	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	64087	0	0	0
T54	48601	0	0	0
T55	1627	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	415	0	0
T2	27352	1	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T16	0	1	0	0
T18	35558	0	0	0
T19	271951	1	0	0
T23	0	3	0	0
T24	0	17	0	0
T26	0	5	0	0
T34	0	2	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693400511	228547725	0	0
T1	262047	213337	0	0
T2	27352	2072	0	0
T3	591636	83280	0	0
T4	934991	582	0	0
T5	989812	1612	0	0
T6	266007	22624	0	0
T10	578	504	0	0
T13	471326	18803	0	0
T18	35558	35494	0	0
T19	271951	66849	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	955	0	0
T1	262047	2	0	0
T2	27352	1	0	0
T3	591636	1	0	0
T4	934991	1	0	0
T5	989812	3	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	4	0	0
T20	0	1	0	0
T23	0	6	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	928	0	0
T1	262047	2	0	0
T2	27352	1	0	0
T3	591636	1	0	0
T4	934991	1	0	0
T5	989812	2	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T23	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	908	0	0
T1	262047	2	0	0
T2	27352	1	0	0
T3	591636	1	0	0
T4	934991	1	0	0
T5	989812	2	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T23	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	892	0	0
T1	262047	2	0	0
T2	27352	1	0	0
T3	591636	1	0	0
T4	934991	1	0	0
T5	989812	2	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T23	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	771	0	0
T2	27352	1	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T23	0	7	0	0
T28	0	1	0	0
T35	0	1	0	0
T64	0	3	0	0
T70	0	1	0	0
T73	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	86205	0	0
T2	27352	159	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T18	35558	0	0	0
T19	271951	415	0	0
T23	0	1093	0	0
T28	0	117	0	0
T64	0	130	0	0
T70	0	229	0	0
T73	0	159	0	0
T76	0	268	0	0
T77	0	28	0	0
T78	0	191	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	656	0	0
T2	27352	1	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T18	35558	0	0	0
T19	271951	1	0	0
T23	0	2	0	0
T28	0	1	0	0
T36	0	31	0	0
T38	0	3	0	0
T64	0	3	0	0
T73	0	1	0	0
T76	0	2	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	72	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	2	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	4	0	0
T24	621045	0	0	0
T33	17964	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T58	0	1	0	0
T70	0	1	0	0
T77	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1495	0	0
T10	47044	388	0	0
T11	0	178	0	0
T12	0	388	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	181	0	0
T32	0	360	0	0
T33	17964	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1255	0	0
T10	47044	328	0	0
T11	0	148	0	0
T12	0	328	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	151	0	0
T32	0	300	0	0
T33	17964	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693399168	693329590	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	73	0	0	0
T13	471326	471318	0	0
T14	0	434154	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	693394925	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	47044	21247	0	0
T13	471326	471318	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T18,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T23
1	0	1	Covered	T1,T18,T5
1	1	0	Covered	T1,T19,T23
1	1	1	Covered	T1,T24,T53

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T53
0	1	Covered	T1,T77,T60
1	0	Covered	T24,T25,T37

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T24,T53
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T25,T37

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T53
1	0	Not Covered
1	1	Covered	T1,T77,T60

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T5
1	Covered	T19,T23,T34

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T5
1	Covered	T6,T24,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T19
1	Covered	T18,T5,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T18,T5,T6
1	Covered	T1,T16,T69

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T18,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T18,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T19,T33

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T18,T5
Phase1St	198	Covered	T1,T18,T5
Phase2St	215	Covered	T1,T18,T5
Phase3St	233	Covered	T1,T18,T5
TerminalSt	249	Covered	T1,T18,T5
TimeoutSt	159	Covered	T1,T24,T53

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T18,T5
IdleSt->TimeoutSt	159	Covered	T1,T24,T53
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T25,T94
Phase0St->Phase1St	198	Covered	T1,T18,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T34,T94
Phase1St->Phase2St	215	Covered	T1,T18,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T28,T25
Phase2St->Phase3St	233	Covered	T1,T18,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T41,T95,T51
Phase3St->TerminalSt	249	Covered	T1,T18,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T53,T34,T64
TimeoutSt->Phase0St	172	Covered	T1,T24,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T24,T53
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T24,T53
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T53,T34,T64
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T94,T96
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T18,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T18,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T34,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T18,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T18,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T28,T25
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T18,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T95,T51
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T18,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T19,T65
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T18,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693566296	270	0	0
CheckAccumTrig0_A	693566296	544	0	0
CheckAccumTrig1_A	693566296	23	0	0
CheckClr_A	693566296	238	0	0
CheckEn_A	693400511	275284040	0	0
CheckPhase0_A	693566296	597	0	0
CheckPhase1_A	693566296	580	0	0
CheckPhase2_A	693566296	560	0	0
CheckPhase3_A	693566296	549	0	0
CheckTimeout0_A	693566296	1311	0	0
CheckTimeoutSt1_A	693566296	134690	0	0
CheckTimeoutSt2_A	693566296	1236	0	0
CheckTimeoutStTrig_A	693566296	49	0	0
ErrorStAllEscAsserted_A	693566296	1426	0	0
ErrorStIsTerminal_A	693566296	1186	0	0
EscStateOut_A	693399168	693329590	0	0
u_state_regs_A	693566296	693394925	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	270	0	0
T10	47044	62	0	0
T11	0	35	0	0
T12	0	88	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	29	0	0
T32	0	56	0	0
T33	17964	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	544	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	1	0	0
T19	271951	6	0	0
T23	0	1	0	0
T26	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	23	0	0
T7	714551	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T17	141954	0	0	0
T24	621045	1	0	0
T25	0	2	0	0
T26	313027	0	0	0
T33	17964	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T49	0	2	0	0
T53	64087	0	0	0
T54	48601	0	0	0
T55	1627	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	238	0	0
T5	989812	1	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T19	271951	4	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T26	0	1	0	0
T28	0	3	0	0
T34	0	1	0	0
T65	0	3	0	0
T66	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693400511	275284040	0	0
T1	262047	30140	0	0
T2	27352	27263	0	0
T3	591636	726	0	0
T4	934991	934898	0	0
T5	989812	590	0	0
T6	266007	16262	0	0
T10	578	504	0	0
T13	471326	470262	0	0
T18	35558	3491	0	0
T19	271951	268320	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	597	0	0
T1	262047	2	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	1	0	0
T19	271951	4	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	0	2	0	0
T33	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	580	0	0
T1	262047	2	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	1	0	0
T19	271951	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	0	2	0	0
T33	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	560	0	0
T1	262047	2	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	1	0	0
T19	271951	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	549	0	0
T1	262047	2	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	2	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	1	0	0
T19	271951	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1311	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T18	35558	0	0	0
T19	271951	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T34	0	13	0	0
T53	0	1	0	0
T64	0	5	0	0
T73	0	8	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	134690	0	0
T1	262047	641	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T18	35558	0	0	0
T19	271951	0	0	0
T24	0	3	0	0
T25	0	14	0	0
T34	0	2394	0	0
T53	0	134	0	0
T64	0	127	0	0
T73	0	1751	0	0
T74	0	142	0	0
T75	0	131	0	0
T77	0	59	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1236	0	0
T17	141954	0	0	0
T26	313027	0	0	0
T34	855893	13	0	0
T53	64087	1	0	0
T54	48601	0	0	0
T55	1627	0	0	0
T58	0	2	0	0
T60	0	3	0	0
T64	133376	5	0	0
T73	0	8	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T80	158487	0	0	0
T81	15227	0	0	0
T82	31542	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	49	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T18	35558	0	0	0
T19	271951	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T77	0	1	0	0
T84	0	1	0	0
T88	0	2	0	0
T89	0	1	0	0
T101	0	3	0	0
T102	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1426	0	0
T10	47044	364	0	0
T11	0	196	0	0
T12	0	363	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	168	0	0
T32	0	335	0	0
T33	17964	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1186	0	0
T10	47044	304	0	0
T11	0	166	0	0
T12	0	303	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	138	0	0
T32	0	275	0	0
T33	17964	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693399168	693329590	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	73	0	0	0
T13	471326	471318	0	0
T14	0	434154	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	693394925	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	47044	21247	0	0
T13	471326	471318	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T23
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T19,T23
1	1	1	Covered	T19,T23,T34

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T34
0	1	Covered	T19,T34,T103
1	0	Covered	T28,T36,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T23,T34
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T36,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T23,T34
1	0	Not Covered
1	1	Covered	T19,T34,T103

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T4,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T4,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T6,T19,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T13,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T6
Phase1St	198	Covered	T1,T4,T6
Phase2St	215	Covered	T1,T4,T6
Phase3St	233	Covered	T1,T4,T6
TerminalSt	249	Covered	T1,T4,T6
TimeoutSt	159	Covered	T19,T23,T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T4,T6
IdleSt->TimeoutSt	159	Covered	T19,T23,T34
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T64,T65,T30
Phase0St->Phase1St	198	Covered	T1,T4,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T65,T30,T104
Phase1St->Phase2St	215	Covered	T1,T4,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T65,T30,T92
Phase2St->Phase3St	233	Covered	T1,T4,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T105,T50
Phase3St->TerminalSt	249	Covered	T1,T4,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T23,T34
TimeoutSt->Phase0St	172	Covered	T19,T34,T103

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T23,T34
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T34,T103
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T23,T34
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T23,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T65,T30,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T65,T30,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T65,T30,T92
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T105,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693566296	335	0	0
CheckAccumTrig0_A	693566296	515	0	0
CheckAccumTrig1_A	693566296	23	0	0
CheckClr_A	693566296	216	0	0
CheckEn_A	693400511	294124193	0	0
CheckPhase0_A	693566296	595	0	0
CheckPhase1_A	693566296	584	0	0
CheckPhase2_A	693566296	570	0	0
CheckPhase3_A	693566296	560	0	0
CheckTimeout0_A	693566296	1098	0	0
CheckTimeoutSt1_A	693566296	125749	0	0
CheckTimeoutSt2_A	693566296	1008	0	0
CheckTimeoutStTrig_A	693566296	65	0	0
ErrorStAllEscAsserted_A	693566296	1500	0	0
ErrorStIsTerminal_A	693566296	1260	0	0
EscStateOut_A	693399168	693329590	0	0
u_state_regs_A	693566296	693394925	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	335	0	0
T10	47044	90	0	0
T11	0	33	0	0
T12	0	82	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	42	0	0
T32	0	88	0	0
T33	17964	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	515	0	0
T1	262047	4	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T14	0	4	0	0
T18	35558	0	0	0
T19	271951	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	6	0	0
T33	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	23	0	0
T9	137102	0	0	0
T28	258327	1	0	0
T36	0	1	0	0
T44	0	1	0	0
T70	28513	0	0	0
T71	17858	0	0	0
T74	32262	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	122544	0	0	0
T114	12634	0	0	0
T115	49284	0	0	0
T116	10825	0	0	0
T117	11970	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	216	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	0	3	0	0
T18	35558	0	0	0
T19	271951	0	0	0
T23	0	2	0	0
T24	0	4	0	0
T26	0	1	0	0
T27	0	3	0	0
T33	0	1	0	0
T65	0	8	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693400511	294124193	0	0
T1	262047	9707	0	0
T2	27352	27263	0	0
T3	591636	353216	0	0
T4	934991	594	0	0
T5	989812	989751	0	0
T6	266007	265462	0	0
T10	578	504	0	0
T13	471326	20485	0	0
T18	35558	28727	0	0
T19	271951	203252	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	595	0	0
T1	262047	4	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T14	0	4	0	0
T18	35558	0	0	0
T19	271951	2	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	6	0	0
T33	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	584	0	0
T1	262047	4	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T14	0	4	0	0
T18	35558	0	0	0
T19	271951	2	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	6	0	0
T33	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	570	0	0
T1	262047	4	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T14	0	4	0	0
T18	35558	0	0	0
T19	271951	2	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	6	0	0
T33	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	560	0	0
T1	262047	4	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	2	0	0
T5	989812	0	0	0
T6	266007	1	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T14	0	4	0	0
T18	35558	0	0	0
T19	271951	2	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	6	0	0
T33	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1098	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	12	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	1	0	0
T24	621045	0	0	0
T28	0	1	0	0
T33	17964	0	0	0
T34	0	3	0	0
T64	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T79	0	4	0	0
T103	0	1	0	0
T118	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	125749	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	3882	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	12	0	0
T24	621045	0	0	0
T28	0	2	0	0
T33	17964	0	0	0
T34	0	837	0	0
T64	0	75	0	0
T72	0	36	0	0
T73	0	327	0	0
T79	0	970	0	0
T103	0	806	0	0
T118	0	51	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1008	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	11	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	1	0	0
T24	621045	0	0	0
T33	17964	0	0	0
T34	0	2	0	0
T64	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T77	0	9	0	0
T78	0	8	0	0
T79	0	3	0	0
T118	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	65	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	1	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T33	17964	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T41	0	1	0	0
T61	0	3	0	0
T79	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T119	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1500	0	0
T10	47044	371	0	0
T11	0	191	0	0
T12	0	383	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	166	0	0
T32	0	389	0	0
T33	17964	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1260	0	0
T10	47044	311	0	0
T11	0	161	0	0
T12	0	323	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	136	0	0
T32	0	329	0	0
T33	17964	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693399168	693329590	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	73	0	0	0
T13	471326	471318	0	0
T14	0	434154	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	693394925	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	47044	21247	0	0
T13	471326	471318	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T21
1	1	1	Covered	T1,T4,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T22
1	0	1	Covered	T1,T6,T19
1	1	0	Covered	T1,T19,T22
1	1	1	Covered	T1,T19,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T19,T64,T36
1	0	Covered	T24,T36,T39

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T36,T39

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Not Covered
1	1	Covered	T19,T64,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T1,T6,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T6,T20,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T6,T19,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T19
1	Covered	T4,T19,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T19,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T6
Phase1St	198	Covered	T1,T4,T6
Phase2St	215	Covered	T1,T4,T6
Phase3St	233	Covered	T1,T4,T6
TerminalSt	249	Covered	T1,T4,T6
TimeoutSt	159	Covered	T1,T19,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T4,T6
IdleSt->TimeoutSt	159	Covered	T1,T19,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T25,T120
Phase0St->Phase1St	198	Covered	T1,T4,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T77,T36
Phase1St->Phase2St	215	Covered	T1,T4,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T121,T25
Phase2St->Phase3St	233	Covered	T1,T4,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T29,T25
Phase3St->TerminalSt	249	Covered	T1,T4,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T6,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T22
TimeoutSt->Phase0St	172	Covered	T19,T24,T64

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T24,T64
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T120,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T77,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T121,T25
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T29,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T19,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693566296	342	0	0
CheckAccumTrig0_A	693566296	529	0	0
CheckAccumTrig1_A	693566296	22	0	0
CheckClr_A	693566296	216	0	0
CheckEn_A	693400511	256161919	0	0
CheckPhase0_A	693566296	609	0	0
CheckPhase1_A	693566296	592	0	0
CheckPhase2_A	693566296	578	0	0
CheckPhase3_A	693566296	566	0	0
CheckTimeout0_A	693566296	1407	0	0
CheckTimeoutSt1_A	693566296	170502	0	0
CheckTimeoutSt2_A	693566296	1318	0	0
CheckTimeoutStTrig_A	693566296	65	0	0
ErrorStAllEscAsserted_A	693566296	1505	0	0
ErrorStIsTerminal_A	693566296	1265	0	0
EscStateOut_A	693399168	693329590	0	0
u_state_regs_A	693566296	693394925	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	342	0	0
T10	47044	106	0	0
T11	0	48	0	0
T12	0	68	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	39	0	0
T32	0	81	0	0
T33	17964	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	529	0	0
T1	262047	3	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	22	0	0
T36	295809	1	0	0
T37	90918	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T56	68745	0	0	0
T57	175936	0	0	0
T58	33275	0	0	0
T59	278289	0	0	0
T60	65636	0	0	0
T61	35204	0	0	0
T62	177900	0	0	0
T63	167044	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	216	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	1	0	0
T20	391323	0	0	0
T22	32014	1	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T27	0	6	0	0
T28	0	1	0	0
T29	0	1	0	0
T34	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693400511	256161919	0	0
T1	262047	20420	0	0
T2	27352	27263	0	0
T3	591636	448325	0	0
T4	934991	7771	0	0
T5	989812	987764	0	0
T6	266007	10205	0	0
T10	578	504	0	0
T13	471326	8284	0	0
T18	35558	35494	0	0
T19	271951	617122	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	609	0	0
T1	262047	3	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	592	0	0
T1	262047	3	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	578	0	0
T1	262047	3	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	3	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	566	0	0
T1	262047	3	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	1	0	0
T5	989812	0	0	0
T6	266007	2	0	0
T10	47044	0	0	0
T13	471326	1	0	0
T18	35558	0	0	0
T19	271951	3	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1407	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	0	0	0
T19	271951	21	0	0
T22	0	1	0	0
T24	0	1	0	0
T34	0	2	0	0
T53	0	6	0	0
T64	0	2	0	0
T71	0	1	0	0
T73	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	170502	0	0
T1	262047	43	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	123	0	0
T18	35558	0	0	0
T19	271951	6364	0	0
T22	0	176	0	0
T24	0	73	0	0
T34	0	57	0	0
T53	0	839	0	0
T64	0	305	0	0
T71	0	167	0	0
T73	0	1041	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1318	0	0
T1	262047	1	0	0
T2	27352	0	0	0
T3	591636	0	0	0
T4	934991	0	0	0
T5	989812	0	0	0
T6	266007	0	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T16	0	2	0	0
T18	35558	0	0	0
T19	271951	19	0	0
T22	0	1	0	0
T34	0	2	0	0
T53	0	6	0	0
T64	0	1	0	0
T71	0	1	0	0
T73	0	5	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	65	0	0
T10	47044	0	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T19	271951	2	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T33	17964	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T88	0	3	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1505	0	0
T10	47044	369	0	0
T11	0	170	0	0
T12	0	381	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	209	0	0
T32	0	376	0	0
T33	17964	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	1265	0	0
T10	47044	309	0	0
T11	0	140	0	0
T12	0	321	0	0
T13	471326	0	0	0
T14	434164	0	0	0
T15	38131	0	0	0
T16	346899	0	0	0
T20	391323	0	0	0
T22	32014	0	0	0
T23	315401	0	0	0
T24	621045	0	0	0
T31	0	179	0	0
T32	0	316	0	0
T33	17964	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693399168	693329590	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	73	0	0	0
T13	471326	471318	0	0
T14	0	434154	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693566296	693394925	0	0
T1	262047	261762	0	0
T2	27352	27264	0	0
T3	591636	591556	0	0
T4	934991	934899	0	0
T5	989812	989752	0	0
T6	266007	266002	0	0
T10	47044	21247	0	0
T13	471326	471318	0	0
T18	35558	35495	0	0
T19	271951	271941	0	0