Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62183212	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30230596

1

T1

5979

T2

118714

T3

143752

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14213209	1			T1	3201		T2	45858		T3	55946
values[0x0]	38085395	1			T1	7423		T2	163604		T3	198326
values[0x1]	40115204	1			T1	7581		T2	163016		T3	198446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53015933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39397875

1

T1

7569

T2

149683

T3

181631

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	315967	1			T1	51		T2	1401		T3	1539
valid_sources[0x01]	312161	1			T1	88		T2	1509		T3	1880
valid_sources[0x02]	312875	1			T1	60		T2	1418		T3	1875
valid_sources[0x03]	318392	1			T1	54		T2	1457		T3	1706
valid_sources[0x04]	313792	1			T1	37		T2	1421		T3	1775
valid_sources[0x05]	314963	1			T1	91		T2	1492		T3	1716
valid_sources[0x06]	310892	1			T1	67		T2	1391		T3	1531
valid_sources[0x07]	308306	1			T1	40		T2	1463		T3	1728
valid_sources[0x08]	338272	1			T1	89		T2	1416		T3	1761
valid_sources[0x09]	319104	1			T1	100		T2	1466		T3	1766
valid_sources[0x0a]	315393	1			T1	75		T2	1405		T3	1859
valid_sources[0x0b]	316172	1			T1	100		T2	1543		T3	1786
valid_sources[0x0c]	312185	1			T1	89		T2	1443		T3	1666
valid_sources[0x0d]	321861	1			T1	80		T2	1543		T3	1869
valid_sources[0x0e]	315257	1			T1	51		T2	1458		T3	1650
valid_sources[0x0f]	763981	1			T1	57		T2	1463		T3	1689
valid_sources[0x10]	316359	1			T1	76		T2	1518		T3	1836
valid_sources[0x11]	315331	1			T1	45		T2	1402		T3	1825
valid_sources[0x12]	358818	1			T1	75		T2	1437		T3	1752
valid_sources[0x13]	318041	1			T1	113		T2	1445		T3	1760
valid_sources[0x14]	313946	1			T1	88		T2	1434		T3	1488
valid_sources[0x15]	327850	1			T1	52		T2	1400		T3	1976
valid_sources[0x16]	319177	1			T1	102		T2	1483		T3	1674
valid_sources[0x17]	913272	1			T1	99		T2	1458		T3	1704
valid_sources[0x18]	314154	1			T1	73		T2	1495		T3	1723
valid_sources[0x19]	336704	1			T1	82		T2	1476		T3	1627
valid_sources[0x1a]	310424	1			T1	44		T2	1473		T3	1715
valid_sources[0x1b]	341080	1			T1	103		T2	1534		T3	1670
valid_sources[0x1c]	316725	1			T1	67		T2	1499		T3	1720
valid_sources[0x1d]	321019	1			T1	70		T2	1487		T3	1761
valid_sources[0x1e]	315992	1			T1	62		T2	1421		T3	1901
valid_sources[0x1f]	310857	1			T1	76		T2	1459		T3	1924
valid_sources[0x20]	314742	1			T1	56		T2	1493		T3	2026
valid_sources[0x21]	312721	1			T1	64		T2	1469		T3	1855
valid_sources[0x22]	313811	1			T1	109		T2	1381		T3	1811
valid_sources[0x23]	312131	1			T1	96		T2	1426		T3	1831
valid_sources[0x24]	315190	1			T1	79		T2	1456		T3	1705
valid_sources[0x25]	317252	1			T1	48		T2	1467		T3	1678
valid_sources[0x26]	310875	1			T1	77		T2	1542		T3	1829
valid_sources[0x27]	309488	1			T1	73		T2	1540		T3	1700
valid_sources[0x28]	324148	1			T1	54		T2	1439		T3	1782
valid_sources[0x29]	604442	1			T1	69		T2	1351		T3	1836
valid_sources[0x2a]	338230	1			T1	49		T2	1529		T3	1715
valid_sources[0x2b]	312470	1			T1	73		T2	1443		T3	1794
valid_sources[0x2c]	321204	1			T1	74		T2	1498		T3	1614
valid_sources[0x2d]	316594	1			T1	61		T2	1508		T3	1880
valid_sources[0x2e]	314819	1			T1	92		T2	1400		T3	1765
valid_sources[0x2f]	313968	1			T1	70		T2	1483		T3	1713
valid_sources[0x30]	315683	1			T1	61		T2	1381		T3	1567
valid_sources[0x31]	314133	1			T1	49		T2	1441		T3	1843
valid_sources[0x32]	315564	1			T1	61		T2	1395		T3	1694
valid_sources[0x33]	310493	1			T1	70		T2	1436		T3	1599
valid_sources[0x34]	322652	1			T1	63		T2	1350		T3	1853
valid_sources[0x35]	315141	1			T1	73		T2	1495		T3	1770
valid_sources[0x36]	319970	1			T1	73		T2	1454		T3	1870
valid_sources[0x37]	350368	1			T1	71		T2	1502		T3	1662
valid_sources[0x38]	314397	1			T1	50		T2	1403		T3	1871
valid_sources[0x39]	315729	1			T1	63		T2	1522		T3	2031
valid_sources[0x3a]	315829	1			T1	86		T2	1453		T3	1898
valid_sources[0x3b]	314110	1			T1	70		T2	1349		T3	1750
valid_sources[0x3c]	564681	1			T1	53		T2	1386		T3	1683
valid_sources[0x3d]	309731	1			T1	77		T2	1516		T3	1802
valid_sources[0x3e]	319826	1			T1	104		T2	1521		T3	1814
valid_sources[0x3f]	322495	1			T1	85		T2	1403		T3	1813
valid_sources[0x40]	311539	1			T1	65		T2	1426		T3	1613
valid_sources[0x41]	317151	1			T1	86		T2	1469		T3	1683
valid_sources[0x42]	323667	1			T1	45		T2	1445		T3	1788
valid_sources[0x43]	314318	1			T1	50		T2	1438		T3	1753
valid_sources[0x44]	323990	1			T1	76		T2	1432		T3	1754
valid_sources[0x45]	316050	1			T1	73		T2	1480		T3	1774
valid_sources[0x46]	312553	1			T1	81		T2	1441		T3	1819
valid_sources[0x47]	322409	1			T1	88		T2	1413		T3	1859
valid_sources[0x48]	315332	1			T1	60		T2	1516		T3	1900
valid_sources[0x49]	684004	1			T1	44		T2	1480		T3	1791
valid_sources[0x4a]	337413	1			T1	47		T2	1436		T3	1676
valid_sources[0x4b]	316638	1			T1	63		T2	1495		T3	1662
valid_sources[0x4c]	313420	1			T1	97		T2	1448		T3	1968
valid_sources[0x4d]	314719	1			T1	45		T2	1481		T3	2000
valid_sources[0x4e]	309729	1			T1	71		T2	1435		T3	1695
valid_sources[0x4f]	313818	1			T1	68		T2	1414		T3	1884
valid_sources[0x50]	310717	1			T1	54		T2	1545		T3	1661
valid_sources[0x51]	314582	1			T1	81		T2	1381		T3	1865
valid_sources[0x52]	312376	1			T1	53		T2	1543		T3	1608
valid_sources[0x53]	315211	1			T1	62		T2	1475		T3	1810
valid_sources[0x54]	315262	1			T1	69		T2	1439		T3	1695
valid_sources[0x55]	322218	1			T1	59		T2	1437		T3	1723
valid_sources[0x56]	322715	1			T1	52		T2	1375		T3	1731
valid_sources[0x57]	313665	1			T1	91		T2	1356		T3	1720
valid_sources[0x58]	319623	1			T1	49		T2	1488		T3	1655
valid_sources[0x59]	319992	1			T1	64		T2	1462		T3	1794
valid_sources[0x5a]	315699	1			T1	79		T2	1458		T3	2067
valid_sources[0x5b]	312574	1			T1	96		T2	1509		T3	1766
valid_sources[0x5c]	777576	1			T1	103		T2	1411		T3	1902
valid_sources[0x5d]	339573	1			T1	52		T2	1557		T3	1981
valid_sources[0x5e]	313685	1			T1	97		T2	1345		T3	1822
valid_sources[0x5f]	312706	1			T1	67		T2	1541		T3	1741
valid_sources[0x60]	325240	1			T1	67		T2	1503		T3	1842
valid_sources[0x61]	319795	1			T1	87		T2	1506		T3	1922
valid_sources[0x62]	792790	1			T1	77		T2	1364		T3	1845
valid_sources[0x63]	313454	1			T1	68		T2	1357		T3	1697
valid_sources[0x64]	637027	1			T1	58		T2	1477		T3	1747
valid_sources[0x65]	317167	1			T1	69		T2	1397		T3	1681
valid_sources[0x66]	352339	1			T1	81		T2	1468		T3	1816
valid_sources[0x67]	323968	1			T1	96		T2	1536		T3	1789
valid_sources[0x68]	547036	1			T1	78		T2	1462		T3	1706
valid_sources[0x69]	315722	1			T1	47		T2	1491		T3	1967
valid_sources[0x6a]	346688	1			T1	60		T2	1461		T3	1980
valid_sources[0x6b]	311996	1			T1	54		T2	1535		T3	1827
valid_sources[0x6c]	720470	1			T1	47		T2	1399		T3	1768
valid_sources[0x6d]	316805	1			T1	53		T2	1452		T3	1922
valid_sources[0x6e]	313595	1			T1	69		T2	1452		T3	1676
valid_sources[0x6f]	520711	1			T1	82		T2	1412		T3	1882
valid_sources[0x70]	312243	1			T1	40		T2	1396		T3	1677
valid_sources[0x71]	317593	1			T1	97		T2	1447		T3	1749
valid_sources[0x72]	315387	1			T1	76		T2	1405		T3	1797
valid_sources[0x73]	524444	1			T1	65		T2	1434		T3	2014
valid_sources[0x74]	621459	1			T1	84		T2	1532		T3	1950
valid_sources[0x75]	318968	1			T1	68		T2	1372		T3	1767
valid_sources[0x76]	317283	1			T1	80		T2	1361		T3	1743
valid_sources[0x77]	320639	1			T1	48		T2	1498		T3	1822
valid_sources[0x78]	313357	1			T1	98		T2	1471		T3	1806
valid_sources[0x79]	311645	1			T1	37		T2	1460		T3	1737
valid_sources[0x7a]	700087	1			T1	85		T2	1417		T3	1735
valid_sources[0x7b]	334921	1			T1	61		T2	1477		T3	1796
valid_sources[0x7c]	314838	1			T1	56		T2	1520		T3	2036
valid_sources[0x7d]	316968	1			T1	32		T2	1411		T3	1880
valid_sources[0x7e]	806440	1			T1	83		T2	1416		T3	1950
valid_sources[0x7f]	318455	1			T1	66		T2	1505		T3	1720
valid_sources[0x80]	315194	1			T1	50		T2	1405		T3	1664

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7070052

1

T1

1559

T2

22802

T3

27727

values[0x0]

all_enables

biggest_size

14606412

1

T1

2774

T2

60986

T3

74163

values[0x1]

all_enables

biggest_size

8554132

1

T1

1646

T2

34926

T3

41862