Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T130,T212
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14000	0	0
DisabledNoTrigBkwd_A	2147483647	834859	0	0
DisabledNoTrigFwd_A	2147483647	1408581281	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14000	0	0
T10	19066	0	0	0
T19	0	859	0	0
T31	41764	0	0	0
T36	9130	1578	0	0
T37	1173930	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0
T76	96694	0	0	0
T87	225489	0	0	0
T92	841505	0	0	0
T102	178672	0	0	0
T130	0	780	0	0
T212	2832	595	0	0
T213	0	549	0	0
T214	2988	609	0	0
T215	0	771	0	0
T216	0	475	0	0
T217	0	326	0	0
T218	0	718	0	0
T219	0	643	0	0
T220	0	327	0	0
T221	0	433	0	0
T222	0	817	0	0
T223	0	811	0	0
T224	0	658	0	0
T225	0	1624	0	0
T226	0	631	0	0
T227	0	520	0	0
T228	0	276	0	0
T229	83191	0	0	0
T230	679134	0	0	0
T231	140940	0	0	0
T232	77917	0	0	0
T233	22340	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	834859	0	0
T1	612564	224	0	0
T2	3829504	2149	0	0
T3	1778440	6556	0	0
T4	710016	2059	0	0
T5	0	1460	0	0
T6	0	1	0	0
T13	849028	457	0	0
T14	0	3933	0	0
T15	0	4716	0	0
T18	17064	10	0	0
T19	17264	16	0	0
T20	190624	2	0	0
T21	399280	0	0	0
T22	424156	771	0	0
T25	0	4	0	0
T44	0	103	0	0
T45	0	52	0	0
T46	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408581281	0	0
T1	612564	230001	0	0
T2	3829504	2869825	0	0
T3	1778440	473079	0	0
T4	710016	2448682	0	0
T13	849028	752707	0	0
T18	17064	13131	0	0
T19	17264	12424	0	0
T20	190624	146146	0	0
T21	399280	202625	0	0
T22	424156	1796927	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T213,T216
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	659886278	4780	0	0
DisabledNoTrigBkwd_A	659886278	213431	0	0
DisabledNoTrigFwd_A	659886278	338777771	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	4780	0	0
T31	41764	0	0	0
T36	4565	1578	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0
T87	225489	0	0	0
T213	0	549	0	0
T216	0	475	0	0
T218	0	718	0	0
T219	0	643	0	0
T222	0	817	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	213431	0	0
T1	153141	28	0	0
T2	957376	1	0	0
T3	444610	2401	0	0
T4	177504	1240	0	0
T13	212257	345	0	0
T14	0	82	0	0
T18	4266	10	0	0
T19	4316	0	0	0
T20	47656	2	0	0
T21	99820	0	0	0
T22	106039	243	0	0
T44	0	103	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	338777771	0	0
T1	153141	63730	0	0
T2	957376	955974	0	0
T3	444610	8171	0	0
T4	177504	613052	0	0
T13	212257	145478	0	0
T18	4266	582	0	0
T19	4316	3072	0	0
T20	47656	3346	0	0
T21	99820	21342	0	0
T22	106039	382080	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T217,T220
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	659886278	2702	0	0
DisabledNoTrigBkwd_A	659886278	228235	0	0
DisabledNoTrigFwd_A	659886278	328783776	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	2702	0	0
T10	19066	0	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T76	96694	0	0	0
T92	841505	0	0	0
T102	178672	0	0	0
T212	2832	595	0	0
T217	0	326	0	0
T220	0	327	0	0
T224	0	658	0	0
T227	0	520	0	0
T228	0	276	0	0
T229	83191	0	0	0
T230	679134	0	0	0
T231	140940	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	228235	0	0
T1	153141	38	0	0
T2	957376	2	0	0
T3	444610	2559	0	0
T4	177504	545	0	0
T5	0	1	0	0
T13	212257	39	0	0
T14	0	1984	0	0
T15	0	4	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	224	0	0
T45	0	52	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	328783776	0	0
T1	153141	86453	0	0
T2	957376	955498	0	0
T3	444610	7987	0	0
T4	177504	976868	0	0
T13	212257	193145	0	0
T18	4266	4183	0	0
T19	4316	3088	0	0
T20	47656	47600	0	0
T21	99820	73712	0	0
T22	106039	564185	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T223,T226
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	659886278	2051	0	0
DisabledNoTrigBkwd_A	659886278	202248	0	0
DisabledNoTrigFwd_A	659886278	389969752	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	2051	0	0
T29	551856	0	0	0
T80	60725	0	0	0
T81	64521	0	0	0
T214	2988	609	0	0
T223	0	811	0	0
T226	0	631	0	0
T232	77917	0	0	0
T233	22340	0	0	0
T234	983348	0	0	0
T235	106868	0	0	0
T236	170893	0	0	0
T237	21621	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	202248	0	0
T1	153141	115	0	0
T2	957376	2144	0	0
T3	444610	2	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	6	0	0
T14	0	2	0	0
T15	0	2338	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	115	0	0
T25	0	4	0	0
T46	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	389969752	0	0
T1	153141	27851	0	0
T2	957376	2379	0	0
T3	444610	444073	0	0
T4	177504	176582	0	0
T13	212257	206051	0	0
T18	4266	4183	0	0
T19	4316	3119	0	0
T20	47656	47600	0	0
T21	99820	26876	0	0
T22	106039	523204	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T130,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	659886278	4467	0	0
DisabledNoTrigBkwd_A	659886278	190945	0	0
DisabledNoTrigFwd_A	659886278	351049982	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	4467	0	0
T5	286320	0	0	0
T13	212257	0	0	0
T14	515686	0	0	0
T19	4316	859	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	0	0	0
T44	30121	0	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T130	0	780	0	0
T215	0	771	0	0
T221	0	433	0	0
T225	0	1624	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	190945	0	0
T1	153141	43	0	0
T2	957376	2	0	0
T3	444610	1594	0	0
T4	177504	274	0	0
T5	0	1459	0	0
T13	212257	67	0	0
T14	0	1865	0	0
T15	0	2374	0	0
T18	4266	0	0	0
T19	4316	16	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	189	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	351049982	0	0
T1	153141	51967	0	0
T2	957376	955974	0	0
T3	444610	12848	0	0
T4	177504	682180	0	0
T13	212257	208033	0	0
T18	4266	4183	0	0
T19	4316	3145	0	0
T20	47656	47600	0	0
T21	99820	80695	0	0
T22	106039	327458	0	0