Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23,T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T21,T13
1	0	Covered	T4,T13,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T13,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T26,T27
1	1	Covered	T1,T21,T13

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T28,T29,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T3,T31,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T1,T2,T33
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T3,T13,T22
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T4
TimeoutSt->Phase0St	172	Covered	T1,T4,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T23
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T31,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T13,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	937	0	0
CheckAccumTrig0_A	2147483647	2462	0	0
CheckAccumTrig1_A	2147483647	120	0	0
CheckClr_A	2147483647	1173	0	0
CheckEn_A	2147483647	1116957807	0	0
CheckPhase0_A	2147483647	2785	0	0
CheckPhase1_A	2147483647	2720	0	0
CheckPhase2_A	2147483647	2664	0	0
CheckPhase3_A	2147483647	2596	0	0
CheckTimeout0_A	2147483647	3921	0	0
CheckTimeoutSt1_A	2147483647	490442	0	0
CheckTimeoutSt2_A	2147483647	3536	0	0
CheckTimeoutStTrig_A	2147483647	257	0	0
ErrorStAllEscAsserted_A	2147483647	4994	0	0
ErrorStIsTerminal_A	2147483647	4154	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	937	0	0
T10	76264	131	0	0
T11	0	138	0	0
T12	0	256	0	0
T31	167056	0	0	0
T34	0	275	0	0
T35	0	137	0	0
T36	18260	0	0	0
T37	2347860	0	0	0
T38	2447040	0	0	0
T39	6752	0	0	0
T40	66124	0	0	0
T41	160880	0	0	0
T42	3534080	0	0	0
T43	2122332	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2462	0	0
T1	612564	17	0	0
T2	3829504	7	0	0
T3	1778440	9	0	0
T4	710016	11	0	0
T5	0	2	0	0
T6	0	1	0	0
T13	849028	16	0	0
T14	0	17	0	0
T15	0	3	0	0
T18	17064	1	0	0
T19	17264	1	0	0
T20	190624	1	0	0
T21	399280	0	0	0
T22	424156	14	0	0
T25	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120	0	0
T4	177504	1	0	0
T5	286320	0	0	0
T7	581053	0	0	0
T13	212257	1	0	0
T16	48446	0	0	0
T17	378471	0	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	0	0	0
T25	29612	1	0	0
T32	0	1	0	0
T38	0	2	0	0
T43	0	2	0	0
T46	354478	0	0	0
T47	300293	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	0	1	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T64	10817	0	0	0
T65	23540	0	0	0
T66	166831	0	0	0
T67	66388	0	0	0
T68	536476	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1173	0	0
T1	612564	8	0	0
T2	3829504	5	0	0
T3	1778440	6	0	0
T4	710016	6	0	0
T6	0	1	0	0
T8	0	1	0	0
T13	849028	12	0	0
T14	0	9	0	0
T15	0	1	0	0
T18	17064	0	0	0
T19	17264	0	0	0
T20	190624	0	0	0
T21	399280	0	0	0
T22	424156	4	0	0
T25	0	3	0	0
T46	0	5	0	0
T65	0	1	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1116957807	0	0
T1	612564	124461	0	0
T2	3829504	1914096	0	0
T3	1778440	473079	0	0
T4	710016	2443852	0	0
T13	849028	611288	0	0
T18	17064	13128	0	0
T19	17264	12424	0	0
T20	190624	146143	0	0
T21	399280	127836	0	0
T22	424156	1765671	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2785	0	0
T1	612564	19	0	0
T2	3829504	7	0	0
T3	1778440	8	0	0
T4	710016	12	0	0
T5	0	2	0	0
T6	0	1	0	0
T13	849028	19	0	0
T14	0	11	0	0
T15	0	2	0	0
T18	17064	1	0	0
T19	17264	1	0	0
T20	190624	1	0	0
T21	399280	2	0	0
T22	424156	16	0	0
T25	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2720	0	0
T1	612564	19	0	0
T2	3829504	7	0	0
T3	1778440	7	0	0
T4	710016	12	0	0
T5	0	2	0	0
T6	0	1	0	0
T13	849028	19	0	0
T14	0	11	0	0
T15	0	2	0	0
T18	17064	1	0	0
T19	17264	1	0	0
T20	190624	1	0	0
T21	399280	2	0	0
T22	424156	16	0	0
T25	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2664	0	0
T1	612564	18	0	0
T2	3829504	6	0	0
T3	1778440	7	0	0
T4	710016	12	0	0
T5	0	2	0	0
T6	0	1	0	0
T13	849028	19	0	0
T14	0	11	0	0
T15	0	2	0	0
T18	17064	1	0	0
T19	17264	1	0	0
T20	190624	1	0	0
T21	399280	2	0	0
T22	424156	16	0	0
T25	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2596	0	0
T1	612564	18	0	0
T2	3829504	6	0	0
T3	1778440	5	0	0
T4	710016	12	0	0
T5	0	2	0	0
T6	0	1	0	0
T13	849028	18	0	0
T14	0	11	0	0
T15	0	2	0	0
T18	17064	1	0	0
T19	17264	1	0	0
T20	190624	1	0	0
T21	399280	2	0	0
T22	424156	15	0	0
T25	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3921	0	0
T1	306282	4	0	0
T2	2872128	1	0	0
T3	1333830	0	0	0
T4	710016	16	0	0
T5	572640	0	0	0
T13	849028	4	0	0
T14	0	177	0	0
T18	17064	1	0	0
T19	17264	0	0	0
T20	190624	0	0	0
T21	399280	12	0	0
T22	424156	6	0	0
T25	0	8	0	0
T33	0	2	0	0
T38	0	1	0	0
T43	0	7	0	0
T47	0	5	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	12	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	7	0	0
T73	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	490442	0	0
T1	306282	1325	0	0
T2	2872128	40	0	0
T3	1333830	0	0	0
T4	710016	1391	0	0
T5	572640	0	0	0
T13	849028	467	0	0
T14	0	11351	0	0
T18	17064	40	0	0
T19	17264	0	0	0
T20	190624	0	0	0
T21	399280	2766	0	0
T22	424156	1707	0	0
T25	0	1929	0	0
T33	0	150	0	0
T38	0	152	0	0
T43	0	822	0	0
T47	0	403	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	2118	0	0
T70	0	78	0	0
T71	0	243	0	0
T72	0	666	0	0
T73	0	303	0	0
T75	0	372	0	0
T76	0	80	0	0
T77	0	394	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3536	0	0
T1	306282	1	0	0
T2	2872128	1	0	0
T3	1333830	0	0	0
T4	710016	8	0	0
T5	572640	0	0	0
T13	849028	1	0	0
T14	0	125	0	0
T18	17064	1	0	0
T19	17264	0	0	0
T20	190624	0	0	0
T21	399280	8	0	0
T22	424156	4	0	0
T25	0	7	0	0
T33	0	8	0	0
T38	0	2	0	0
T43	0	5	0	0
T47	0	4	0	0
T51	0	7	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	8	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257	0	0
T1	153141	1	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T5	286320	0	0	0
T13	424514	2	0	0
T14	0	5	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	212078	1	0	0
T29	0	2	0	0
T31	41764	0	0	0
T32	0	1	0	0
T38	611760	3	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	1	0	0
T42	883520	0	0	0
T43	530583	0	0	0
T48	49644	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	225489	0	0	0
T88	1241	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4994	0	0
T10	76264	732	0	0
T11	0	702	0	0
T12	0	1394	0	0
T31	167056	0	0	0
T34	0	1435	0	0
T35	0	731	0	0
T36	18260	0	0	0
T37	2347860	0	0	0
T38	2447040	0	0	0
T39	6752	0	0	0
T40	66124	0	0	0
T41	160880	0	0	0
T42	3534080	0	0	0
T43	2122332	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4154	0	0
T10	76264	612	0	0
T11	0	582	0	0
T12	0	1154	0	0
T31	167056	0	0	0
T34	0	1195	0	0
T35	0	611	0	0
T36	18260	0	0	0
T37	2347860	0	0	0
T38	2447040	0	0	0
T39	6752	0	0	0
T40	66124	0	0	0
T41	160880	0	0	0
T42	3534080	0	0	0
T43	2122332	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	612564	611420	0	0
T2	3829504	3829148	0	0
T3	1778440	1778408	0	0
T4	710016	709972	0	0
T13	849028	848988	0	0
T18	17064	16732	0	0
T19	17264	17036	0	0
T20	190624	190400	0	0
T21	399280	399024	0	0
T22	424156	423936	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	612564	611420	0	0
T2	3829504	3829148	0	0
T3	1778440	1778408	0	0
T4	710016	709972	0	0
T13	849028	848988	0	0
T18	17064	16732	0	0
T19	17264	17036	0	0
T20	190624	190400	0	0
T21	399280	399024	0	0
T22	424156	423936	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T4,T13
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T4,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T18
0	1	Covered	T1,T21,T13
1	0	Covered	T4,T13,T38

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T13,T38

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Not Covered
1	1	Covered	T1,T21,T13

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T89,T60
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T90,T91
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T92,T93
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T13,T94
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T18
TimeoutSt->Phase0St	172	Covered	T1,T4,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T89,T60,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T90,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T13,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	659886278	225	0	0
CheckAccumTrig0_A	659886278	911	0	0
CheckAccumTrig1_A	659886278	48	0	0
CheckClr_A	659886278	455	0	0
CheckEn_A	659742880	242527431	0	0
CheckPhase0_A	659886278	1013	0	0
CheckPhase1_A	659886278	993	0	0
CheckPhase2_A	659886278	974	0	0
CheckPhase3_A	659886278	946	0	0
CheckTimeout0_A	659886278	1053	0	0
CheckTimeoutSt1_A	659886278	132993	0	0
CheckTimeoutSt2_A	659886278	932	0	0
CheckTimeoutStTrig_A	659886278	70	0	0
ErrorStAllEscAsserted_A	659886278	1269	0	0
ErrorStIsTerminal_A	659886278	1059	0	0
EscStateOut_A	659741468	659669365	0	0
u_state_regs_A	659886278	659724741	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	225	0	0
T10	19066	29	0	0
T11	0	28	0	0
T12	0	57	0	0
T31	41764	0	0	0
T34	0	66	0	0
T35	0	45	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	911	0	0
T1	153141	3	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	6	0	0
T13	212257	11	0	0
T14	0	8	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	1	0	0
T21	99820	0	0	0
T22	106039	3	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	48	0	0
T4	177504	1	0	0
T5	286320	0	0	0
T13	212257	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	0	0	0
T38	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	55161	0	0	0
T63	31463	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	455	0	0
T1	153141	1	0	0
T2	957376	1	0	0
T3	444610	1	0	0
T4	177504	4	0	0
T13	212257	10	0	0
T14	0	6	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	0	0	0
T25	0	3	0	0
T46	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659742880	242527431	0	0
T1	153141	31335	0	0
T2	957376	954909	0	0
T3	444610	8171	0	0
T4	177504	613050	0	0
T13	212257	74917	0	0
T18	4266	582	0	0
T19	4316	3072	0	0
T20	47656	3346	0	0
T21	99820	10885	0	0
T22	106039	372850	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1013	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	7	0	0
T13	212257	13	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	1	0	0
T21	99820	1	0	0
T22	106039	4	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	993	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	7	0	0
T13	212257	13	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	1	0	0
T21	99820	1	0	0
T22	106039	4	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	974	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	7	0	0
T13	212257	13	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	1	0	0
T21	99820	1	0	0
T22	106039	4	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	946	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	1	0	0
T4	177504	7	0	0
T13	212257	12	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	1	0	0
T21	99820	1	0	0
T22	106039	4	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1053	0	0
T1	153141	2	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	6	0	0
T13	212257	2	0	0
T14	0	36	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	1	0	0
T25	0	7	0	0
T67	0	2	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	132993	0	0
T1	153141	835	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	415	0	0
T13	212257	119	0	0
T14	0	2361	0	0
T18	4266	40	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	33	0	0
T22	106039	351	0	0
T25	0	1923	0	0
T67	0	444	0	0
T71	0	243	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	932	0	0
T1	153141	1	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	5	0	0
T13	212257	0	0	0
T14	0	33	0	0
T18	4266	1	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	0	0	0
T25	0	7	0	0
T33	0	6	0	0
T67	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	70	0	0
T1	153141	1	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T13	212257	1	0	0
T14	0	3	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	1	0	0
T38	0	1	0	0
T55	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1269	0	0
T10	19066	190	0	0
T11	0	168	0	0
T12	0	351	0	0
T31	41764	0	0	0
T34	0	373	0	0
T35	0	187	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1059	0	0
T10	19066	160	0	0
T11	0	138	0	0
T12	0	291	0	0
T31	41764	0	0	0
T34	0	313	0	0
T35	0	157	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659741468	659669365	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	659724741	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T19
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T4,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T21
0	1	Covered	T1,T21,T22
1	0	Covered	T72,T51,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T72,T51,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Not Covered
1	1	Covered	T1,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T4,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T21,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T3,T46,T38
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T70,T96,T97
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T98,T99,T100
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T101,T102
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T21
TimeoutSt->Phase0St	172	Covered	T1,T21,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T46,T38
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T70,T96,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T98,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T101,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	659886278	231	0	0
CheckAccumTrig0_A	659886278	497	0	0
CheckAccumTrig1_A	659886278	24	0	0
CheckClr_A	659886278	234	0	0
CheckEn_A	659742880	285749098	0	0
CheckPhase0_A	659886278	576	0	0
CheckPhase1_A	659886278	559	0	0
CheckPhase2_A	659886278	545	0	0
CheckPhase3_A	659886278	528	0	0
CheckTimeout0_A	659886278	989	0	0
CheckTimeoutSt1_A	659886278	121546	0	0
CheckTimeoutSt2_A	659886278	893	0	0
CheckTimeoutStTrig_A	659886278	69	0	0
ErrorStAllEscAsserted_A	659886278	1245	0	0
ErrorStIsTerminal_A	659886278	1035	0	0
EscStateOut_A	659741468	659669365	0	0
u_state_regs_A	659886278	659724741	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	231	0	0
T10	19066	31	0	0
T11	0	29	0	0
T12	0	73	0	0
T31	41764	0	0	0
T34	0	71	0	0
T35	0	27	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	497	0	0
T1	153141	3	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	3	0	0
T5	0	1	0	0
T13	212257	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	1	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	24	0	0
T9	565019	0	0	0
T29	0	1	0	0
T47	300293	0	0	0
T51	0	1	0	0
T53	0	2	0	0
T61	0	1	0	0
T72	336725	1	0	0
T73	134202	0	0	0
T74	242096	0	0	0
T94	553957	0	0	0
T97	0	3	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	44218	0	0	0
T108	899822	0	0	0
T109	194816	0	0	0
T110	139814	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	234	0	0
T1	153141	1	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	2	0	0
T13	212257	0	0	0
T14	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	2	0	0
T46	0	2	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659742880	285749098	0	0
T1	153141	22584	0	0
T2	957376	954909	0	0
T3	444610	12848	0	0
T4	177504	677355	0	0
T13	212257	191953	0	0
T18	4266	4182	0	0
T19	4316	3145	0	0
T20	47656	47599	0	0
T21	99820	16364	0	0
T22	106039	327455	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	576	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	3	0	0
T5	0	1	0	0
T13	212257	1	0	0
T14	0	3	0	0
T18	4266	0	0	0
T19	4316	1	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	559	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	3	0	0
T5	0	1	0	0
T13	212257	1	0	0
T14	0	3	0	0
T18	4266	0	0	0
T19	4316	1	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	545	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	2	0	0
T4	177504	3	0	0
T5	0	1	0	0
T13	212257	1	0	0
T14	0	3	0	0
T18	4266	0	0	0
T19	4316	1	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	528	0	0
T1	153141	4	0	0
T2	957376	1	0	0
T3	444610	1	0	0
T4	177504	3	0	0
T5	0	1	0	0
T13	212257	1	0	0
T14	0	3	0	0
T18	4266	0	0	0
T19	4316	1	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	989	0	0
T1	153141	2	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	7	0	0
T13	212257	0	0	0
T14	0	47	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	3	0	0
T22	106039	1	0	0
T67	0	4	0	0
T70	0	1	0	0
T72	0	6	0	0
T73	0	2	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	121546	0	0
T1	153141	490	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	637	0	0
T13	212257	0	0	0
T14	0	3089	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	707	0	0
T22	106039	147	0	0
T67	0	641	0	0
T70	0	78	0	0
T72	0	535	0	0
T73	0	162	0	0
T75	0	372	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	893	0	0
T1	153141	1	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	7	0	0
T13	212257	0	0	0
T14	0	47	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	2	0	0
T22	106039	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T67	0	4	0	0
T72	0	5	0	0
T73	0	1	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	69	0	0
T1	153141	1	0	0
T2	957376	0	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T13	212257	0	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	1	0	0
T22	106039	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T38	0	2	0	0
T70	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T111	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1245	0	0
T10	19066	185	0	0
T11	0	172	0	0
T12	0	371	0	0
T31	41764	0	0	0
T34	0	343	0	0
T35	0	174	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1035	0	0
T10	19066	155	0	0
T11	0	142	0	0
T12	0	311	0	0
T31	41764	0	0	0
T34	0	283	0	0
T35	0	144	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659741468	659669365	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	659724741	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T4,T21,T13
1	1	1	Covered	T4,T21,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T21,T22
0	1	Covered	T38,T77,T81
1	0	Covered	T25,T43,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T21,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T43,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T21,T22
1	0	Not Covered
1	1	Covered	T38,T77,T81

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T25,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T4,T21,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T4,T21,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T23,T96
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T96,T58
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T1,T112,T113
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T22,T32,T114
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T21,T22
TimeoutSt->Phase0St	172	Covered	T25,T38,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T38,T43
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T23,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T96,T58
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T112,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T32,T114
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	659886278	277	0	0
CheckAccumTrig0_A	659886278	537	0	0
CheckAccumTrig1_A	659886278	24	0	0
CheckClr_A	659886278	253	0	0
CheckEn_A	659742880	270866877	0	0
CheckPhase0_A	659886278	616	0	0
CheckPhase1_A	659886278	597	0	0
CheckPhase2_A	659886278	585	0	0
CheckPhase3_A	659886278	570	0	0
CheckTimeout0_A	659886278	1209	0	0
CheckTimeoutSt1_A	659886278	149003	0	0
CheckTimeoutSt2_A	659886278	1114	0	0
CheckTimeoutStTrig_A	659886278	69	0	0
ErrorStAllEscAsserted_A	659886278	1260	0	0
ErrorStIsTerminal_A	659886278	1050	0	0
EscStateOut_A	659741468	659669365	0	0
u_state_regs_A	659886278	659724741	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	277	0	0
T10	19066	45	0	0
T11	0	45	0	0
T12	0	74	0	0
T31	41764	0	0	0
T34	0	93	0	0
T35	0	20	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	537	0	0
T1	153141	6	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	2	0	0
T5	0	1	0	0
T13	212257	2	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	3	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	24	0	0
T7	581053	0	0	0
T16	48446	0	0	0
T17	378471	0	0	0
T25	29612	1	0	0
T32	0	1	0	0
T43	0	2	0	0
T46	354478	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T64	10817	0	0	0
T65	23540	0	0	0
T66	166831	0	0	0
T67	66388	0	0	0
T68	536476	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	253	0	0
T1	153141	4	0	0
T2	957376	0	0	0
T3	444610	2	0	0
T4	177504	0	0	0
T13	212257	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	1	0	0
T46	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659742880	270866877	0	0
T1	153141	54073	0	0
T2	957376	1899	0	0
T3	444610	7987	0	0
T4	177504	976865	0	0
T13	212257	146597	0	0
T18	4266	4182	0	0
T19	4316	3088	0	0
T20	47656	47599	0	0
T21	99820	73711	0	0
T22	106039	558375	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	616	0	0
T1	153141	6	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	2	0	0
T5	0	1	0	0
T13	212257	2	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	3	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	597	0	0
T1	153141	6	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	2	0	0
T5	0	1	0	0
T13	212257	2	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	3	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	585	0	0
T1	153141	5	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	2	0	0
T5	0	1	0	0
T13	212257	2	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	3	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	570	0	0
T1	153141	5	0	0
T2	957376	1	0	0
T3	444610	3	0	0
T4	177504	2	0	0
T5	0	1	0	0
T13	212257	2	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1209	0	0
T4	177504	1	0	0
T5	286320	0	0	0
T13	212257	0	0	0
T14	0	42	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	3	0	0
T22	106039	3	0	0
T25	0	1	0	0
T38	0	1	0	0
T43	0	7	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	6	0	0
T72	0	1	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	149003	0	0
T4	177504	73	0	0
T5	286320	0	0	0
T13	212257	0	0	0
T14	0	2550	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	785	0	0
T22	106039	820	0	0
T25	0	6	0	0
T38	0	152	0	0
T43	0	822	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	1033	0	0
T72	0	131	0	0
T77	0	394	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1114	0	0
T4	177504	1	0	0
T5	286320	0	0	0
T13	212257	0	0	0
T14	0	42	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	3	0	0
T22	106039	3	0	0
T43	0	5	0	0
T51	0	7	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T67	0	6	0	0
T72	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	69	0	0
T29	0	2	0	0
T31	41764	0	0	0
T32	0	1	0	0
T38	611760	1	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0
T48	49644	0	0	0
T56	0	1	0	0
T77	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	225489	0	0	0
T88	1241	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1260	0	0
T10	19066	197	0	0
T11	0	176	0	0
T12	0	350	0	0
T31	41764	0	0	0
T34	0	368	0	0
T35	0	169	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1050	0	0
T10	19066	167	0	0
T11	0	146	0	0
T12	0	290	0	0
T31	41764	0	0	0
T34	0	308	0	0
T35	0	139	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659741468	659669365	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	659724741	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T4,T13,T22
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T2,T4,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T21
0	1	Covered	T13,T14,T76
1	0	Covered	T47,T38,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T38,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T21
1	0	Covered	T26,T27
1	1	Covered	T13,T14,T76

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T2,T22,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T94

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T13,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T22,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T13,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T13
Phase3St	233	Covered	T1,T2,T13
TerminalSt	249	Covered	T1,T2,T13
TimeoutSt	159	Covered	T2,T4,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T4,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T117,T118
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T119,T120
Phase1St->Phase2St	215	Covered	T1,T2,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T121,T32
Phase2St->Phase3St	233	Covered	T1,T2,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T58,T59
Phase3St->TerminalSt	249	Covered	T1,T2,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T21
TimeoutSt->Phase0St	172	Covered	T13,T14,T47

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T47
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T117,T118
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T119,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T121,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T58,T59
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	659886278	204	0	0
CheckAccumTrig0_A	659886278	517	0	0
CheckAccumTrig1_A	659886278	24	0	0
CheckClr_A	659886278	231	0	0
CheckEn_A	659742880	317814401	0	0
CheckPhase0_A	659886278	580	0	0
CheckPhase1_A	659886278	571	0	0
CheckPhase2_A	659886278	560	0	0
CheckPhase3_A	659886278	552	0	0
CheckTimeout0_A	659886278	670	0	0
CheckTimeoutSt1_A	659886278	86900	0	0
CheckTimeoutSt2_A	659886278	597	0	0
CheckTimeoutStTrig_A	659886278	49	0	0
ErrorStAllEscAsserted_A	659886278	1220	0	0
ErrorStIsTerminal_A	659886278	1010	0	0
EscStateOut_A	659741468	659669365	0	0
u_state_regs_A	659886278	659724741	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	204	0	0
T10	19066	26	0	0
T11	0	36	0	0
T12	0	52	0	0
T31	41764	0	0	0
T34	0	45	0	0
T35	0	45	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	517	0	0
T1	153141	5	0	0
T2	957376	4	0	0
T3	444610	1	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0
T25	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	24	0	0
T33	127861	0	0	0
T38	0	1	0	0
T47	300293	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T60	0	2	0	0
T73	134202	0	0	0
T74	242096	0	0	0
T75	40698	0	0	0
T109	194816	0	0	0
T110	139814	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	62521	0	0	0
T127	17074	0	0	0
T128	17707	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	231	0	0
T1	153141	2	0	0
T2	957376	3	0	0
T3	444610	1	0	0
T4	177504	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T13	212257	2	0	0
T14	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	1	0	0
T46	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659742880	317814401	0	0
T1	153141	16469	0	0
T2	957376	2379	0	0
T3	444610	444073	0	0
T4	177504	176582	0	0
T13	212257	197821	0	0
T18	4266	4182	0	0
T19	4316	3119	0	0
T20	47656	47599	0	0
T21	99820	26876	0	0
T22	106039	506991	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	580	0	0
T1	153141	5	0	0
T2	957376	4	0	0
T3	444610	1	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	3	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0
T25	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	571	0	0
T1	153141	5	0	0
T2	957376	4	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	3	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0
T25	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	560	0	0
T1	153141	5	0	0
T2	957376	3	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	3	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0
T25	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	552	0	0
T1	153141	5	0	0
T2	957376	3	0	0
T3	444610	0	0	0
T4	177504	0	0	0
T6	0	1	0	0
T13	212257	3	0	0
T14	0	4	0	0
T15	0	1	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	0	0	0
T22	106039	4	0	0
T25	0	1	0	0
T46	0	1	0	0
T68	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	670	0	0
T2	957376	1	0	0
T3	444610	0	0	0
T4	177504	2	0	0
T5	286320	0	0	0
T13	212257	2	0	0
T14	0	52	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	5	0	0
T22	106039	1	0	0
T33	0	2	0	0
T47	0	5	0	0
T73	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	86900	0	0
T2	957376	40	0	0
T3	444610	0	0	0
T4	177504	266	0	0
T5	286320	0	0	0
T13	212257	348	0	0
T14	0	3351	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	1241	0	0
T22	106039	389	0	0
T33	0	150	0	0
T47	0	403	0	0
T73	0	141	0	0
T76	0	80	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	597	0	0
T2	957376	1	0	0
T3	444610	0	0	0
T4	177504	2	0	0
T5	286320	0	0	0
T13	212257	1	0	0
T14	0	50	0	0
T18	4266	0	0	0
T19	4316	0	0	0
T20	47656	0	0	0
T21	99820	5	0	0
T22	106039	1	0	0
T33	0	2	0	0
T38	0	2	0	0
T47	0	4	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	49	0	0
T5	286320	0	0	0
T13	212257	1	0	0
T14	515686	2	0	0
T15	412916	0	0	0
T22	106039	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	30121	0	0	0
T45	118822	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T62	55161	0	0	0
T63	31463	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T123	0	1	0	0
T129	0	1	0	0
T130	3857	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1220	0	0
T10	19066	160	0	0
T11	0	186	0	0
T12	0	322	0	0
T31	41764	0	0	0
T34	0	351	0	0
T35	0	201	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	1010	0	0
T10	19066	130	0	0
T11	0	156	0	0
T12	0	262	0	0
T31	41764	0	0	0
T34	0	291	0	0
T35	0	171	0	0
T36	4565	0	0	0
T37	586965	0	0	0
T38	611760	0	0	0
T39	1688	0	0	0
T40	16531	0	0	0
T41	40220	0	0	0
T42	883520	0	0	0
T43	530583	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659741468	659669365	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659886278	659724741	0	0
T1	153141	152855	0	0
T2	957376	957287	0	0
T3	444610	444602	0	0
T4	177504	177493	0	0
T13	212257	212247	0	0
T18	4266	4183	0	0
T19	4316	4259	0	0
T20	47656	47600	0	0
T21	99820	99756	0	0
T22	106039	105984	0	0