Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61453175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29645263

1

T1

1232

T2

2596

T3

87673

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13963425	1			T1	457		T2	1087		T3	34394
values[0x0]	37754624	1			T1	1627		T2	3568		T3	121666
values[0x1]	39380389	1			T1	1731		T2	3618		T3	122374

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52628157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38470281

1

T1

1566

T2

3299

T3

110990

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	282320	1			T1	10		T2	28		T3	1069
valid_sources[0x01]	290541	1			T1	21		T2	47		T3	1102
valid_sources[0x02]	281390	1			T1	13		T2	26		T3	1074
valid_sources[0x03]	295103	1			T1	19		T2	15		T3	1016
valid_sources[0x04]	282834	1			T1	17		T2	34		T3	1125
valid_sources[0x05]	750470	1			T1	17		T2	35		T3	1050
valid_sources[0x06]	287905	1			T1	13		T2	12		T3	1155
valid_sources[0x07]	281464	1			T1	14		T2	16		T3	1120
valid_sources[0x08]	281117	1			T1	17		T2	50		T3	1098
valid_sources[0x09]	394946	1			T1	19		T2	64		T3	1056
valid_sources[0x0a]	279480	1			T1	10		T2	41		T3	1130
valid_sources[0x0b]	281483	1			T1	11		T2	18		T3	1040
valid_sources[0x0c]	283827	1			T1	9		T2	24		T3	1136
valid_sources[0x0d]	280560	1			T1	15		T2	19		T3	1069
valid_sources[0x0e]	483233	1			T1	9		T2	56		T3	1052
valid_sources[0x0f]	322293	1			T1	14		T2	37		T3	1023
valid_sources[0x10]	284627	1			T1	19		T2	30		T3	1071
valid_sources[0x11]	281598	1			T1	12		T2	76		T3	1133
valid_sources[0x12]	283264	1			T1	9		T2	55		T3	1059
valid_sources[0x13]	283637	1			T1	13		T2	9		T3	1099
valid_sources[0x14]	307100	1			T1	17		T2	56		T3	1042
valid_sources[0x15]	282249	1			T1	10		T2	14		T3	1143
valid_sources[0x16]	279439	1			T1	7		T2	29		T3	1022
valid_sources[0x17]	322337	1			T1	10		T2	34		T3	1057
valid_sources[0x18]	280598	1			T1	20		T2	42		T3	1154
valid_sources[0x19]	285749	1			T1	12		T2	35		T3	1093
valid_sources[0x1a]	281653	1			T1	14		T2	15		T3	1085
valid_sources[0x1b]	280882	1			T1	15		T2	29		T3	1036
valid_sources[0x1c]	294256	1			T1	24		T2	32		T3	1105
valid_sources[0x1d]	281579	1			T1	14		T2	40		T3	1105
valid_sources[0x1e]	290887	1			T1	14		T2	25		T3	1143
valid_sources[0x1f]	282959	1			T1	8		T2	51		T3	1064
valid_sources[0x20]	288949	1			T1	12		T2	48		T3	1131
valid_sources[0x21]	288792	1			T1	14		T2	18		T3	1096
valid_sources[0x22]	296777	1			T1	18		T2	38		T3	1076
valid_sources[0x23]	284709	1			T1	12		T2	14		T3	1056
valid_sources[0x24]	292112	1			T1	14		T2	36		T3	1081
valid_sources[0x25]	289424	1			T1	16		T2	23		T3	1115
valid_sources[0x26]	281116	1			T1	14		T2	41		T3	1101
valid_sources[0x27]	286054	1			T1	20		T2	32		T3	1120
valid_sources[0x28]	287577	1			T1	12		T2	19		T3	1104
valid_sources[0x29]	282484	1			T1	14		T2	37		T3	1178
valid_sources[0x2a]	284436	1			T1	15		T2	6		T3	1113
valid_sources[0x2b]	284173	1			T1	14		T2	35		T3	1078
valid_sources[0x2c]	283981	1			T1	14		T2	42		T3	1177
valid_sources[0x2d]	283981	1			T1	4		T2	4		T3	1028
valid_sources[0x2e]	281747	1			T1	11		T2	8		T3	1037
valid_sources[0x2f]	283628	1			T1	23		T2	22		T3	1092
valid_sources[0x30]	284034	1			T1	18		T2	11		T3	1061
valid_sources[0x31]	298566	1			T1	15		T2	18		T3	1112
valid_sources[0x32]	283451	1			T1	14		T2	11		T3	1081
valid_sources[0x33]	562132	1			T1	15		T2	19		T3	1112
valid_sources[0x34]	578023	1			T1	18		T2	23		T3	1081
valid_sources[0x35]	849097	1			T1	11		T2	23		T3	1141
valid_sources[0x36]	300314	1			T1	11		T2	21		T3	1054
valid_sources[0x37]	310346	1			T1	8		T2	18		T3	1091
valid_sources[0x38]	764841	1			T1	14		T2	35		T3	987
valid_sources[0x39]	601588	1			T1	17		T2	19		T3	1122
valid_sources[0x3a]	284922	1			T1	15		T2	30		T3	1099
valid_sources[0x3b]	548681	1			T1	17		T2	24		T3	1078
valid_sources[0x3c]	567123	1			T1	17		T2	12		T3	1101
valid_sources[0x3d]	285977	1			T1	17		T2	24		T3	1083
valid_sources[0x3e]	282280	1			T1	25		T2	28		T3	1080
valid_sources[0x3f]	560535	1			T1	10		T2	17		T3	1117
valid_sources[0x40]	284546	1			T1	15		T2	46		T3	1078
valid_sources[0x41]	283698	1			T1	14		T2	31		T3	1097
valid_sources[0x42]	281279	1			T1	14		T2	70		T3	1047
valid_sources[0x43]	316480	1			T1	25		T2	29		T3	1066
valid_sources[0x44]	281481	1			T1	17		T2	30		T3	1101
valid_sources[0x45]	281519	1			T1	17		T2	34		T3	1151
valid_sources[0x46]	279519	1			T1	15		T2	58		T3	1050
valid_sources[0x47]	283785	1			T1	15		T2	48		T3	1102
valid_sources[0x48]	288778	1			T1	22		T2	71		T3	1083
valid_sources[0x49]	280473	1			T1	11		T2	41		T3	1099
valid_sources[0x4a]	277969	1			T1	21		T2	16		T3	1028
valid_sources[0x4b]	283701	1			T1	8		T2	29		T3	1142
valid_sources[0x4c]	751439	1			T1	10		T2	27		T3	1103
valid_sources[0x4d]	296877	1			T1	11		T2	35		T3	1092
valid_sources[0x4e]	284131	1			T1	17		T2	16		T3	1164
valid_sources[0x4f]	767305	1			T1	22		T2	19		T3	1128
valid_sources[0x50]	293620	1			T1	8		T2	49		T3	1136
valid_sources[0x51]	281161	1			T1	16		T2	34		T3	1021
valid_sources[0x52]	281941	1			T1	10		T2	30		T3	1093
valid_sources[0x53]	281963	1			T1	12		T2	12		T3	1066
valid_sources[0x54]	500630	1			T1	15		T2	30		T3	1080
valid_sources[0x55]	284455	1			T1	14		T2	28		T3	1147
valid_sources[0x56]	284739	1			T1	20		T2	57		T3	1075
valid_sources[0x57]	289478	1			T1	16		T2	33		T3	1108
valid_sources[0x58]	283460	1			T1	12		T2	70		T3	1083
valid_sources[0x59]	280861	1			T1	13		T2	52		T3	1067
valid_sources[0x5a]	287468	1			T1	19		T2	18		T3	1048
valid_sources[0x5b]	280580	1			T1	18		T2	30		T3	1121
valid_sources[0x5c]	663765	1			T1	9		T2	46		T3	1078
valid_sources[0x5d]	281134	1			T1	25		T2	17		T3	1091
valid_sources[0x5e]	493955	1			T1	11		T2	39		T3	1103
valid_sources[0x5f]	283578	1			T1	15		T2	27		T3	1103
valid_sources[0x60]	279764	1			T1	20		T2	40		T3	995
valid_sources[0x61]	327319	1			T1	9		T2	41		T3	1085
valid_sources[0x62]	281205	1			T1	26		T2	47		T3	1096
valid_sources[0x63]	284658	1			T1	7		T2	38		T3	1101
valid_sources[0x64]	280266	1			T1	21		T2	27		T3	1103
valid_sources[0x65]	283528	1			T1	20		T2	17		T3	1072
valid_sources[0x66]	280298	1			T1	8		T2	14		T3	1111
valid_sources[0x67]	279844	1			T1	9		T2	30		T3	1095
valid_sources[0x68]	281495	1			T1	8		T2	29		T3	1104
valid_sources[0x69]	682122	1			T1	17		T2	41		T3	1128
valid_sources[0x6a]	283059	1			T1	15		T2	23		T3	1100
valid_sources[0x6b]	288376	1			T1	18		T2	13		T3	1050
valid_sources[0x6c]	280472	1			T1	18		T2	28		T3	1009
valid_sources[0x6d]	298552	1			T1	12		T2	30		T3	1118
valid_sources[0x6e]	294878	1			T1	17		T2	37		T3	1102
valid_sources[0x6f]	527476	1			T1	11		T2	29		T3	1133
valid_sources[0x70]	281837	1			T1	12		T2	47		T3	1067
valid_sources[0x71]	282077	1			T1	15		T2	23		T3	1065
valid_sources[0x72]	281374	1			T1	22		T2	24		T3	1015
valid_sources[0x73]	700463	1			T1	16		T2	63		T3	1072
valid_sources[0x74]	280760	1			T1	10		T2	47		T3	1082
valid_sources[0x75]	283149	1			T1	17		T2	48		T3	1066
valid_sources[0x76]	480885	1			T1	15		T2	38		T3	1007
valid_sources[0x77]	283001	1			T1	12		T2	44		T3	1103
valid_sources[0x78]	280365	1			T1	13		T2	37		T3	1056
valid_sources[0x79]	947240	1			T1	10		T2	20		T3	1078
valid_sources[0x7a]	281607	1			T1	18		T2	21		T3	1086
valid_sources[0x7b]	1141683	1			T1	15		T2	57		T3	1114
valid_sources[0x7c]	1004494	1			T1	24		T2	57		T3	1030
valid_sources[0x7d]	285848	1			T1	29		T2	26		T3	1111
valid_sources[0x7e]	288215	1			T1	22		T2	41		T3	1082
valid_sources[0x7f]	286899	1			T1	19		T2	26		T3	1096
valid_sources[0x80]	287787	1			T1	13		T2	51		T3	1076

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6879579

1

T1

238

T2

549

T3

17227

values[0x0]

all_enables

biggest_size

14397756

1

T1

631

T2

1297

T3

44986

values[0x1]

all_enables

biggest_size

8367928

1

T1

363

T2

750

T3

25460