Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T192,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13289	0	0
DisabledNoTrigBkwd_A	2147483647	786863	0	0
DisabledNoTrigFwd_A	2147483647	1489934714	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13289	0	0
T33	583314	0	0	0
T36	149411	0	0	0
T55	505679	0	0	0
T68	2776	389	0	0
T113	14327	0	0	0
T114	19375	0	0	0
T115	31819	0	0	0
T116	792017	0	0	0
T117	136637	0	0	0
T192	0	1322	0	0
T193	0	393	0	0
T194	0	1114	0	0
T195	4855	1335	0	0
T196	0	539	0	0
T197	0	296	0	0
T198	0	446	0	0
T199	0	590	0	0
T200	0	590	0	0
T201	0	811	0	0
T202	0	428	0	0
T203	0	884	0	0
T204	0	840	0	0
T205	0	645	0	0
T206	0	1072	0	0
T207	4235	778	0	0
T208	0	194	0	0
T209	0	196	0	0
T210	0	427	0	0
T211	23563	0	0	0
T212	189714	0	0	0
T213	610614	0	0	0
T214	300057	0	0	0
T215	566717	0	0	0
T216	184366	0	0	0
T217	116581	0	0	0
T218	186873	0	0	0
T219	194653	0	0	0
T220	346228	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	786863	0	0
T2	203166	100	0	0
T3	688956	650	0	0
T4	1059336	1494	0	0
T5	1739920	3	0	0
T6	198489	0	0	0
T7	500672	563	0	0
T13	0	5435	0	0
T18	261404	108	0	0
T19	913740	334	0	0
T20	1647844	416	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	11544	0	0
T26	0	1914	0	0
T30	0	81	0	0
T47	12056	39	0	0
T48	53221	1	0	0
T49	0	13	0	0
T50	0	236	0	0
T51	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1489934714	0	0
T1	190932	144390	0	0
T2	270888	81913	0	0
T3	918608	86666	0	0
T4	1059336	796221	0	0
T5	1739920	814897	0	0
T6	264652	178036	0	0
T18	261404	137777	0	0
T19	913740	580366	0	0
T20	1647844	837061	0	0
T21	100396	48856	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T198,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675576662	3610	0	0
DisabledNoTrigBkwd_A	675576662	247726	0	0
DisabledNoTrigFwd_A	675576662	296037030	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	3610	0	0
T33	583314	0	0	0
T36	149411	0	0	0
T55	505679	0	0	0
T113	14327	0	0	0
T114	19375	0	0	0
T115	31819	0	0	0
T116	792017	0	0	0
T117	136637	0	0	0
T195	4855	1335	0	0
T198	0	446	0	0
T199	0	590	0	0
T201	0	811	0	0
T202	0	428	0	0
T211	23563	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	247726	0	0
T2	67722	35	0	0
T3	229652	0	0	0
T4	264834	1483	0	0
T5	434980	2	0	0
T6	66163	0	0	0
T7	125168	292	0	0
T13	0	2427	0	0
T18	65351	0	0	0
T19	228435	334	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	4631	0	0
T30	0	46	0	0
T47	0	7	0	0
T48	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	296037030	0	0
T1	47733	33439	0	0
T2	67722	2103	0	0
T3	229652	45105	0	0
T4	264834	2266	0	0
T5	434980	327391	0	0
T6	66163	55409	0	0
T18	65351	62063	0	0
T19	228435	122988	0	0
T20	411961	407125	0	0
T21	25099	14093	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T1,T2,T6
1	1	Covered	T6,T18,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207
1	1	Covered	T6,T18,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T20,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675576662	778	0	0
DisabledNoTrigBkwd_A	675576662	147719	0	0
DisabledNoTrigFwd_A	675576662	416144516	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	778	0	0
T207	4235	778	0	0
T212	189714	0	0	0
T213	610614	0	0	0
T214	300057	0	0	0
T215	566717	0	0	0
T216	184366	0	0	0
T217	116581	0	0	0
T218	186873	0	0	0
T219	194653	0	0	0
T220	346228	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	147719	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	271	0	0
T13	0	1060	0	0
T18	65351	33	0	0
T19	228435	0	0	0
T20	411961	178	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	1870	0	0
T26	0	271	0	0
T47	12056	23	0	0
T48	53221	0	0	0
T49	0	2	0	0
T50	0	130	0	0
T51	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	416144516	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	9748	0	0
T4	264834	264826	0	0
T5	434980	183341	0	0
T6	66163	47952	0	0
T18	65351	9901	0	0
T19	228435	119765	0	0
T20	411961	20228	0	0
T21	25099	10276	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T192,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675576662	6356	0	0
DisabledNoTrigBkwd_A	675576662	167324	0	0
DisabledNoTrigFwd_A	675576662	399532914	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	6356	0	0
T8	112113	0	0	0
T15	666375	0	0	0
T27	44551	0	0	0
T31	838971	0	0	0
T52	58301	0	0	0
T68	2776	389	0	0
T69	122179	0	0	0
T70	84549	0	0	0
T71	52873	0	0	0
T74	20870	0	0	0
T192	0	1322	0	0
T193	0	393	0	0
T196	0	539	0	0
T197	0	296	0	0
T203	0	884	0	0
T204	0	840	0	0
T206	0	1072	0	0
T208	0	194	0	0
T210	0	427	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	167324	0	0
T2	67722	27	0	0
T3	229652	648	0	0
T4	264834	11	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	745	0	0
T18	65351	75	0	0
T19	228435	0	0	0
T20	411961	236	0	0
T21	25099	0	0	0
T25	0	1473	0	0
T47	0	9	0	0
T49	0	5	0	0
T50	0	106	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	399532914	0	0
T1	47733	23585	0	0
T2	67722	2136	0	0
T3	229652	21778	0	0
T4	264834	264303	0	0
T5	434980	46420	0	0
T6	66163	26722	0	0
T18	65351	2816	0	0
T19	228435	226013	0	0
T20	411961	1999	0	0
T21	25099	8748	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T200,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675576662	2545	0	0
DisabledNoTrigBkwd_A	675576662	224094	0	0
DisabledNoTrigFwd_A	675576662	378220254	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	2545	0	0
T33	583314	0	0	0
T36	149411	0	0	0
T55	505679	0	0	0
T94	32687	0	0	0
T113	14327	0	0	0
T114	19375	0	0	0
T194	2015	1114	0	0
T195	4855	0	0	0
T200	0	590	0	0
T205	0	645	0	0
T209	0	196	0	0
T211	23563	0	0	0
T221	168247	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	224094	0	0
T2	67722	38	0	0
T3	229652	2	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1203	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	2	0	0
T21	25099	0	0	0
T25	0	3570	0	0
T26	0	1643	0	0
T30	0	35	0	0
T49	0	6	0	0
T51	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	378220254	0	0
T1	47733	39686	0	0
T2	67722	10005	0	0
T3	229652	10035	0	0
T4	264834	264826	0	0
T5	434980	257745	0	0
T6	66163	47953	0	0
T18	65351	62997	0	0
T19	228435	111600	0	0
T20	411961	407709	0	0
T21	25099	15739	0	0