Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23,T24
1	1	1	Covered	T2,T3,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T19,T4
1	1	1	Covered	T2,T6,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T19
0	1	Covered	T25,T26,T15
1	0	Covered	T25,T27,T15

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T25,T27,T15

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T19
1	0	Covered	T28,T29
1	1	Covered	T25,T26,T15

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T30,T25

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T2,T18,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T19,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T2,T18,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T19

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T18
Phase1St	198	Covered	T2,T3,T18
Phase2St	215	Covered	T2,T3,T18
Phase3St	233	Covered	T2,T3,T18
TerminalSt	249	Covered	T2,T3,T18
TimeoutSt	159	Covered	T2,T6,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T18
IdleSt->TimeoutSt	159	Covered	T2,T6,T19
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T2,T25,T15
Phase0St->Phase1St	198	Covered	T2,T3,T18
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T31,T32,T33
Phase1St->Phase2St	215	Covered	T2,T3,T18
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T23,T34
Phase2St->Phase3St	233	Covered	T2,T3,T18
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T2,T25,T35
Phase3St->TerminalSt	249	Covered	T2,T3,T18
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T3,T19
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T6,T19
TimeoutSt->Phase0St	172	Covered	T25,T26,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T15,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T23,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T25,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1036	0	0
CheckAccumTrig0_A	2147483647	2251	0	0
CheckAccumTrig1_A	2147483647	121	0	0
CheckClr_A	2147483647	1061	0	0
CheckEn_A	2147483647	1194930911	0	0
CheckPhase0_A	2147483647	2572	0	0
CheckPhase1_A	2147483647	2518	0	0
CheckPhase2_A	2147483647	2473	0	0
CheckPhase3_A	2147483647	2423	0	0
CheckTimeout0_A	2147483647	4406	0	0
CheckTimeoutSt1_A	2147483647	572400	0	0
CheckTimeoutSt2_A	2147483647	4039	0	0
CheckTimeoutStTrig_A	2147483647	239	0	0
ErrorStAllEscAsserted_A	2147483647	5039	0	0
ErrorStIsTerminal_A	2147483647	4199	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1036	0	0
T10	187060	273	0	0
T11	0	156	0	0
T12	0	177	0	0
T29	1556624	0	0	0
T37	0	284	0	0
T38	0	146	0	0
T39	3730160	0	0	0
T40	645292	0	0	0
T41	902536	0	0	0
T42	552480	0	0	0
T43	565172	0	0	0
T44	1951884	0	0	0
T45	150324	0	0	0
T46	3460488	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T2	203166	6	0	0
T3	688956	3	0	0
T4	1059336	3	0	0
T5	1739920	2	0	0
T6	198489	0	0	0
T7	500672	2	0	0
T13	0	4	0	0
T18	261404	2	0	0
T19	913740	2	0	0
T20	1647844	3	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	24	0	0
T26	0	5	0	0
T30	0	2	0	0
T47	12056	3	0	0
T48	53221	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121	0	0
T8	224226	0	0	0
T14	720684	0	0	0
T15	666375	3	0	0
T16	124661	0	0	0
T17	537138	1	0	0
T23	0	1	0	0
T25	1753730	4	0	0
T26	1581266	0	0	0
T27	89102	1	0	0
T31	838971	1	0	0
T35	153222	0	0	0
T50	299418	0	0	0
T51	25574	0	0	0
T52	58301	1	0	0
T53	0	4	0	0
T54	0	1	0	0
T55	505679	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	4	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	44320	0	0	0
T68	5552	0	0	0
T69	244358	0	0	0
T70	84549	0	0	0
T71	52873	0	0	0
T72	26951	0	0	0
T73	26603	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1061	0	0
T2	67722	3	0	0
T3	459304	1	0	0
T4	529668	2	0	0
T5	869960	0	0	0
T6	132326	0	0	0
T7	250336	0	0	0
T14	360342	0	0	0
T15	0	20	0	0
T17	0	2	0	0
T18	130702	0	0	0
T19	456870	0	0	0
T20	823922	0	0	0
T21	50198	0	0	0
T22	25395	0	0	0
T25	876865	7	0	0
T26	790633	2	0	0
T27	0	5	0	0
T30	116895	0	0	0
T31	0	33	0	0
T32	0	1	0	0
T35	0	2	0	0
T48	0	1	0	0
T49	25933	3	0	0
T50	149709	0	0	0
T51	12787	1	0	0
T53	0	16	0	0
T54	0	2	0	0
T55	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	122304	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1194930911	0	0
T1	190932	144388	0	0
T2	270888	81912	0	0
T3	918608	85087	0	0
T4	1059336	796088	0	0
T5	1739920	488120	0	0
T6	264652	178033	0	0
T18	261404	137775	0	0
T19	913740	580363	0	0
T20	1647844	434765	0	0
T21	100396	48855	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2572	0	0
T2	203166	5	0	0
T3	688956	3	0	0
T4	1059336	3	0	0
T5	1739920	2	0	0
T6	198489	0	0	0
T7	500672	2	0	0
T13	0	4	0	0
T18	261404	2	0	0
T19	913740	2	0	0
T20	1647844	3	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	31	0	0
T26	0	7	0	0
T30	0	2	0	0
T47	12056	3	0	0
T48	53221	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2518	0	0
T2	203166	5	0	0
T3	688956	3	0	0
T4	1059336	3	0	0
T5	1739920	2	0	0
T6	198489	0	0	0
T7	500672	2	0	0
T13	0	4	0	0
T18	261404	2	0	0
T19	913740	2	0	0
T20	1647844	3	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	31	0	0
T26	0	7	0	0
T30	0	2	0	0
T47	12056	3	0	0
T48	53221	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T2	203166	5	0	0
T3	688956	3	0	0
T4	1059336	3	0	0
T5	1739920	2	0	0
T6	198489	0	0	0
T7	500672	2	0	0
T13	0	4	0	0
T18	261404	2	0	0
T19	913740	2	0	0
T20	1647844	3	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	31	0	0
T26	0	7	0	0
T30	0	2	0	0
T47	12056	3	0	0
T48	53221	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T2	203166	4	0	0
T3	688956	3	0	0
T4	1059336	3	0	0
T5	1739920	2	0	0
T6	198489	0	0	0
T7	500672	2	0	0
T13	0	4	0	0
T18	261404	2	0	0
T19	913740	2	0	0
T20	1647844	3	0	0
T21	100396	0	0	0
T22	25395	0	0	0
T25	0	30	0	0
T26	0	7	0	0
T30	0	2	0	0
T47	12056	3	0	0
T48	53221	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4406	0	0
T2	67722	1	0	0
T3	229652	0	0	0
T4	1059336	7	0	0
T5	1739920	0	0	0
T6	264652	7	0	0
T7	500672	0	0	0
T15	0	42	0	0
T18	261404	0	0	0
T19	913740	162	0	0
T20	1647844	0	0	0
T21	100396	8	0	0
T22	76185	10	0	0
T25	0	91	0	0
T26	0	54	0	0
T27	0	1	0	0
T30	0	2	0	0
T31	0	34	0	0
T35	0	1	0	0
T47	36168	0	0	0
T48	0	6	0	0
T51	0	2	0	0
T52	0	1	0	0
T69	0	9	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	572400	0	0
T2	67722	234	0	0
T3	229652	0	0	0
T4	1059336	699	0	0
T5	1739920	0	0	0
T6	264652	992	0	0
T7	500672	0	0	0
T15	0	7928	0	0
T18	261404	0	0	0
T19	913740	35038	0	0
T20	1647844	0	0	0
T21	100396	1321	0	0
T22	76185	598	0	0
T25	0	8497	0	0
T26	0	4673	0	0
T27	0	18	0	0
T30	0	478	0	0
T31	0	4213	0	0
T35	0	94	0	0
T47	36168	0	0	0
T48	0	562	0	0
T51	0	83	0	0
T52	0	43	0	0
T69	0	1437	0	0
T75	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4039	0	0
T2	67722	1	0	0
T3	229652	0	0	0
T4	1059336	7	0	0
T5	1739920	0	0	0
T6	264652	7	0	0
T7	500672	0	0	0
T15	0	36	0	0
T17	0	3	0	0
T18	261404	0	0	0
T19	913740	161	0	0
T20	1647844	0	0	0
T21	100396	8	0	0
T22	76185	10	0	0
T25	0	81	0	0
T26	0	52	0	0
T30	0	2	0	0
T31	0	27	0	0
T35	0	1	0	0
T47	36168	0	0	0
T48	0	6	0	0
T51	0	2	0	0
T69	0	9	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239	0	0
T8	448452	0	0	0
T14	1441368	0	0	0
T15	0	2	0	0
T23	0	9	0	0
T25	3507460	5	0	0
T26	3162532	2	0	0
T27	178204	0	0	0
T31	0	9	0	0
T33	0	1	0	0
T50	598836	0	0	0
T51	51148	0	0	0
T52	0	1	0	0
T53	0	5	0	0
T57	0	3	0	0
T61	0	1	0	0
T67	88640	0	0	0
T68	11104	0	0	0
T69	488716	0	0	0
T75	0	3	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5039	0	0
T10	187060	1409	0	0
T11	0	734	0	0
T12	0	754	0	0
T29	1556624	0	0	0
T37	0	1436	0	0
T38	0	706	0	0
T39	3730160	0	0	0
T40	645292	0	0	0
T41	902536	0	0	0
T42	552480	0	0	0
T43	565172	0	0	0
T44	1951884	0	0	0
T45	150324	0	0	0
T46	3460488	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4199	0	0
T10	187060	1169	0	0
T11	0	614	0	0
T12	0	634	0	0
T29	1556624	0	0	0
T37	0	1196	0	0
T38	0	586	0	0
T39	3730160	0	0	0
T40	645292	0	0	0
T41	902536	0	0	0
T42	552480	0	0	0
T43	565172	0	0	0
T44	1951884	0	0	0
T45	150324	0	0	0
T46	3460488	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	190932	190720	0	0
T2	270888	270676	0	0
T3	918608	918580	0	0
T4	1059336	1059304	0	0
T5	1739920	1739680	0	0
T6	264652	263984	0	0
T18	261404	261180	0	0
T19	913740	913692	0	0
T20	1647844	1647552	0	0
T21	100396	100104	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	190932	190720	0	0
T2	270888	270676	0	0
T3	918608	918580	0	0
T4	1059336	1059304	0	0
T5	1739920	1739680	0	0
T6	264652	263984	0	0
T18	261404	261180	0	0
T19	913740	913692	0	0
T20	1647844	1647552	0	0
T21	100396	100104	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T6,T18,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T18,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T20,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T21
1	0	1	Covered	T18,T20,T7
1	1	0	Covered	T6,T19,T4
1	1	1	Covered	T6,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T19,T21
0	1	Covered	T25,T31,T52
1	0	Covered	T25,T15,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T15,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T21
1	0	Not Covered
1	1	Covered	T25,T31,T52

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T20,T7
1	Covered	T25,T26,T51

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T20,T7,T47
1	Covered	T18,T49,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T18,T7,T13
1	Covered	T20,T47,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T18,T20,T47
1	Covered	T7,T13,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T18,T7,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T18,T20,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T18,T20,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T47,T49

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T18,T20,T7
Phase1St	198	Covered	T18,T20,T7
Phase2St	215	Covered	T18,T20,T7
Phase3St	233	Covered	T18,T20,T7
TerminalSt	249	Covered	T18,T20,T7
TimeoutSt	159	Covered	T6,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T18,T20,T7
IdleSt->TimeoutSt	159	Covered	T6,T19,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T31,T77
Phase0St->Phase1St	198	Covered	T18,T20,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T34,T89
Phase1St->Phase2St	215	Covered	T18,T20,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T23,T34
Phase2St->Phase3St	233	Covered	T18,T20,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T53,T34,T89
Phase3St->TerminalSt	249	Covered	T18,T20,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T49,T25,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T19,T21
TimeoutSt->Phase0St	172	Covered	T25,T15,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T15,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T77,T54
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T18,T20,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T18,T20,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T89,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T18,T20,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T18,T20,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T23,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T18,T20,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T18,T20,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T53,T34,T89
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T18,T20,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T18,T20,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T49,T51,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T18,T20,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675576662	275	0	0
CheckAccumTrig0_A	675576662	475	0	0
CheckAccumTrig1_A	675576662	26	0	0
CheckClr_A	675576662	243	0	0
CheckEn_A	675401778	341439011	0	0
CheckPhase0_A	675576662	559	0	0
CheckPhase1_A	675576662	551	0	0
CheckPhase2_A	675576662	542	0	0
CheckPhase3_A	675576662	531	0	0
CheckTimeout0_A	675576662	1581	0	0
CheckTimeoutSt1_A	675576662	199270	0	0
CheckTimeoutSt2_A	675576662	1486	0	0
CheckTimeoutStTrig_A	675576662	69	0	0
ErrorStAllEscAsserted_A	675576662	1293	0	0
ErrorStIsTerminal_A	675576662	1083	0	0
EscStateOut_A	675400228	675331794	0	0
u_state_regs_A	675576662	675418211	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	275	0	0
T10	46765	72	0	0
T11	0	34	0	0
T12	0	54	0	0
T29	389156	0	0	0
T37	0	68	0	0
T38	0	47	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	475	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	3	0	0
T26	0	1	0	0
T47	12056	1	0	0
T48	53221	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	26	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T25	876865	2	0	0
T26	790633	0	0	0
T27	44551	0	0	0
T31	0	1	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	243	0	0
T14	360342	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T25	876865	0	0	0
T26	790633	0	0	0
T30	116895	0	0	0
T31	0	17	0	0
T49	25933	1	0	0
T50	149709	0	0	0
T51	12787	1	0	0
T53	0	16	0	0
T54	0	2	0	0
T55	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T75	0	1	0	0
T77	0	4	0	0
T78	122304	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675401778	341439011	0	0
T1	47733	47679	0	0
T2	67722	67668	0	0
T3	229652	9748	0	0
T4	264834	264826	0	0
T5	434980	183341	0	0
T6	66163	47951	0	0
T18	65351	9901	0	0
T19	228435	119764	0	0
T20	411961	20228	0	0
T21	25099	10276	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	559	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	6	0	0
T26	0	1	0	0
T47	12056	1	0	0
T48	53221	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	551	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	6	0	0
T26	0	1	0	0
T47	12056	1	0	0
T48	53221	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	542	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	6	0	0
T26	0	1	0	0
T47	12056	1	0	0
T48	53221	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	531	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	6	0	0
T26	0	1	0	0
T47	12056	1	0	0
T48	53221	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1581	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	2	0	0
T7	125168	0	0	0
T15	0	18	0	0
T18	65351	0	0	0
T19	228435	92	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	2	0	0
T25	0	78	0	0
T26	0	28	0	0
T31	0	21	0	0
T47	12056	0	0	0
T51	0	2	0	0
T52	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	199270	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	274	0	0
T7	125168	0	0	0
T15	0	3593	0	0
T18	65351	0	0	0
T19	228435	21262	0	0
T20	411961	0	0	0
T21	25099	311	0	0
T22	25395	164	0	0
T25	0	6625	0	0
T26	0	2528	0	0
T31	0	2421	0	0
T47	12056	0	0	0
T51	0	83	0	0
T52	0	43	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1486	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	2	0	0
T7	125168	0	0	0
T15	0	17	0	0
T17	0	3	0	0
T18	65351	0	0	0
T19	228435	92	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	2	0	0
T25	0	75	0	0
T26	0	28	0	0
T31	0	13	0	0
T47	12056	0	0	0
T51	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	69	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T23	0	3	0	0
T25	876865	1	0	0
T26	790633	0	0	0
T27	44551	0	0	0
T31	0	7	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0
T75	0	1	0	0
T80	0	1	0	0
T84	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1293	0	0
T10	46765	346	0	0
T11	0	196	0	0
T12	0	186	0	0
T29	389156	0	0	0
T37	0	380	0	0
T38	0	185	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1083	0	0
T10	46765	286	0	0
T11	0	166	0	0
T12	0	156	0	0
T29	389156	0	0	0
T37	0	320	0	0
T38	0	155	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675400228	675331794	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	675418211	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T6,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T2,T19,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T4
1	0	1	Covered	T1,T2,T18
1	1	0	Covered	T6,T19,T22
1	1	1	Covered	T6,T19,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T19,T4
0	1	Covered	T25,T15,T31
1	0	Covered	T25,T27,T15

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T19,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T27,T15

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T4
1	0	Not Covered
1	1	Covered	T25,T15,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T4
1	Covered	T30,T25,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T47
1	Covered	T2,T19,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T4
1	Covered	T19,T13,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T4
1	Covered	T5,T47,T48

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T4,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T19,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T19,T4
Phase1St	198	Covered	T2,T19,T4
Phase2St	215	Covered	T2,T19,T4
Phase3St	233	Covered	T2,T19,T4
TerminalSt	249	Covered	T2,T19,T4
TimeoutSt	159	Covered	T6,T19,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T19,T4
IdleSt->TimeoutSt	159	Covered	T6,T19,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T2,T25,T15
Phase0St->Phase1St	198	Covered	T2,T19,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T36,T34
Phase1St->Phase2St	215	Covered	T2,T19,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T91,T92,T93
Phase2St->Phase3St	233	Covered	T2,T19,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T2,T25,T77
Phase3St->TerminalSt	249	Covered	T2,T19,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T19,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T19,T4
TimeoutSt->Phase0St	172	Covered	T25,T27,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T15,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T19,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T19,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T36,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T19,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T19,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T19,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T25,T77
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T19,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T19,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T48
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T19,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675576662	274	0	0
CheckAccumTrig0_A	675576662	803	0	0
CheckAccumTrig1_A	675576662	51	0	0
CheckClr_A	675576662	381	0	0
CheckEn_A	675401778	225525826	0	0
CheckPhase0_A	675576662	891	0	0
CheckPhase1_A	675576662	868	0	0
CheckPhase2_A	675576662	853	0	0
CheckPhase3_A	675576662	831	0	0
CheckTimeout0_A	675576662	1187	0	0
CheckTimeoutSt1_A	675576662	147701	0	0
CheckTimeoutSt2_A	675576662	1076	0	0
CheckTimeoutStTrig_A	675576662	56	0	0
ErrorStAllEscAsserted_A	675576662	1224	0	0
ErrorStIsTerminal_A	675576662	1014	0	0
EscStateOut_A	675400228	675331794	0	0
u_state_regs_A	675576662	675418211	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	274	0	0
T10	46765	77	0	0
T11	0	44	0	0
T12	0	30	0	0
T29	389156	0	0	0
T37	0	92	0	0
T38	0	31	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	803	0	0
T2	67722	4	0	0
T3	229652	0	0	0
T4	264834	2	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	2	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	9	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	51	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T15	0	1	0	0
T25	876865	2	0	0
T26	790633	0	0	0
T27	44551	1	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	381	0	0
T2	67722	3	0	0
T3	229652	0	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T15	0	10	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	6	0	0
T26	0	2	0	0
T27	0	5	0	0
T31	0	13	0	0
T35	0	1	0	0
T48	0	1	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675401778	225525826	0	0
T1	47733	33439	0	0
T2	67722	2103	0	0
T3	229652	45105	0	0
T4	264834	2266	0	0
T5	434980	614	0	0
T6	66163	55408	0	0
T18	65351	62062	0	0
T19	228435	122987	0	0
T20	411961	407124	0	0
T21	25099	14092	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	891	0	0
T2	67722	3	0	0
T3	229652	0	0	0
T4	264834	2	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	2	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	11	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	868	0	0
T2	67722	3	0	0
T3	229652	0	0	0
T4	264834	2	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	2	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	11	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	853	0	0
T2	67722	3	0	0
T3	229652	0	0	0
T4	264834	2	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	2	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	11	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	831	0	0
T2	67722	2	0	0
T3	229652	0	0	0
T4	264834	2	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	1	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	2	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T25	0	10	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1187	0	0
T4	264834	7	0	0
T5	434980	0	0	0
T6	66163	2	0	0
T7	125168	0	0	0
T15	0	4	0	0
T18	65351	0	0	0
T19	228435	1	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	0	0	0
T25	0	5	0	0
T26	0	17	0	0
T27	0	1	0	0
T30	0	1	0	0
T47	12056	0	0	0
T48	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	147701	0	0
T4	264834	699	0	0
T5	434980	0	0	0
T6	66163	274	0	0
T7	125168	0	0	0
T15	0	507	0	0
T18	65351	0	0	0
T19	228435	214	0	0
T20	411961	0	0	0
T21	25099	312	0	0
T22	25395	0	0	0
T25	0	254	0	0
T26	0	1295	0	0
T27	0	18	0	0
T30	0	239	0	0
T47	12056	0	0	0
T48	0	562	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1076	0	0
T4	264834	7	0	0
T5	434980	0	0	0
T6	66163	2	0	0
T7	125168	0	0	0
T15	0	2	0	0
T18	65351	0	0	0
T19	228435	1	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	0	0	0
T25	0	1	0	0
T26	0	17	0	0
T30	0	1	0	0
T31	0	2	0	0
T47	12056	0	0	0
T48	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	56	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T15	0	1	0	0
T23	0	3	0	0
T25	876865	1	0	0
T26	790633	0	0	0
T27	44551	0	0	0
T31	0	1	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T53	0	1	0	0
T57	0	2	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T87	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1224	0	0
T10	46765	348	0	0
T11	0	176	0	0
T12	0	185	0	0
T29	389156	0	0	0
T37	0	348	0	0
T38	0	167	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1014	0	0
T10	46765	288	0	0
T11	0	146	0	0
T12	0	155	0	0
T29	389156	0	0	0
T37	0	288	0	0
T38	0	137	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675400228	675331794	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	675418211	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T2,T3,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T4
1	0	1	Covered	T2,T3,T18
1	1	0	Covered	T6,T19,T4
1	1	1	Covered	T6,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T19,T21
0	1	Covered	T25,T15,T31
1	0	Covered	T15,T23,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T23,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T21
1	0	Not Covered
1	1	Covered	T25,T15,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T25,T50

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T20,T49,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T4,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T20,T4
1	Covered	T2,T18,T47

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T20,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T18
Phase1St	198	Covered	T2,T3,T18
Phase2St	215	Covered	T2,T3,T18
Phase3St	233	Covered	T2,T3,T18
TerminalSt	249	Covered	T2,T3,T18
TimeoutSt	159	Covered	T6,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T18
IdleSt->TimeoutSt	159	Covered	T6,T19,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T17,T95
Phase0St->Phase1St	198	Covered	T2,T3,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T23,T96
Phase1St->Phase2St	215	Covered	T2,T3,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T96,T95,T97
Phase2St->Phase3St	233	Covered	T2,T3,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T66,T98
Phase3St->TerminalSt	249	Covered	T2,T3,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T49
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T19,T21
TimeoutSt->Phase0St	172	Covered	T25,T15,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T15,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T95,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T23,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T95,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T66,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T49
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675576662	260	0	0
CheckAccumTrig0_A	675576662	504	0	0
CheckAccumTrig1_A	675576662	29	0	0
CheckClr_A	675576662	240	0	0
CheckEn_A	675401778	314722032	0	0
CheckPhase0_A	675576662	589	0	0
CheckPhase1_A	675576662	579	0	0
CheckPhase2_A	675576662	569	0	0
CheckPhase3_A	675576662	562	0	0
CheckTimeout0_A	675576662	584	0	0
CheckTimeoutSt1_A	675576662	87046	0	0
CheckTimeoutSt2_A	675576662	494	0	0
CheckTimeoutStTrig_A	675576662	61	0	0
ErrorStAllEscAsserted_A	675576662	1255	0	0
ErrorStIsTerminal_A	675576662	1045	0	0
EscStateOut_A	675400228	675331794	0	0
u_state_regs_A	675576662	675418211	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	260	0	0
T10	46765	63	0	0
T11	0	41	0	0
T12	0	56	0	0
T29	389156	0	0	0
T37	0	57	0	0
T38	0	43	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	504	0	0
T2	67722	1	0	0
T3	229652	2	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	7	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	29	0	0
T15	666375	1	0	0
T16	124661	0	0	0
T17	537138	0	0	0
T23	0	1	0	0
T28	0	1	0	0
T31	838971	0	0	0
T35	153222	0	0	0
T52	58301	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T63	0	3	0	0
T70	84549	0	0	0
T71	52873	0	0	0
T72	26951	0	0	0
T73	26603	0	0	0
T95	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	240	0	0
T3	229652	1	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T15	0	9	0	0
T17	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	0	0	0
T21	25099	0	0	0
T22	25395	0	0	0
T25	0	1	0	0
T31	0	3	0	0
T32	0	1	0	0
T35	0	1	0	0
T49	0	2	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675401778	314722032	0	0
T1	47733	23585	0	0
T2	67722	2136	0	0
T3	229652	20199	0	0
T4	264834	264170	0	0
T5	434980	46420	0	0
T6	66163	26722	0	0
T18	65351	2816	0	0
T19	228435	226013	0	0
T20	411961	1999	0	0
T21	25099	8748	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	589	0	0
T2	67722	1	0	0
T3	229652	2	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	8	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	579	0	0
T2	67722	1	0	0
T3	229652	2	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	8	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	569	0	0
T2	67722	1	0	0
T3	229652	2	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	8	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	562	0	0
T2	67722	1	0	0
T3	229652	2	0	0
T4	264834	1	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	1	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	8	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	584	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	3	0	0
T7	125168	0	0	0
T15	0	4	0	0
T18	65351	0	0	0
T19	228435	1	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	1	0	0
T25	0	6	0	0
T26	0	5	0	0
T31	0	10	0	0
T47	12056	0	0	0
T69	0	9	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	87046	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	444	0	0
T7	125168	0	0	0
T15	0	675	0	0
T18	65351	0	0	0
T19	228435	332	0	0
T20	411961	0	0	0
T21	25099	353	0	0
T22	25395	53	0	0
T25	0	1463	0	0
T26	0	436	0	0
T31	0	1485	0	0
T47	12056	0	0	0
T69	0	1437	0	0
T75	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	494	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	3	0	0
T7	125168	0	0	0
T15	0	2	0	0
T18	65351	0	0	0
T19	228435	1	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	25395	1	0	0
T25	0	4	0	0
T26	0	5	0	0
T31	0	9	0	0
T47	12056	0	0	0
T69	0	9	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	61	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T15	0	1	0	0
T23	0	2	0	0
T25	876865	2	0	0
T26	790633	0	0	0
T27	44551	0	0	0
T31	0	1	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T53	0	2	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0
T79	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1255	0	0
T10	46765	364	0	0
T11	0	187	0	0
T12	0	189	0	0
T29	389156	0	0	0
T37	0	360	0	0
T38	0	155	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1045	0	0
T10	46765	304	0	0
T11	0	157	0	0
T12	0	159	0	0
T29	389156	0	0	0
T37	0	300	0	0
T38	0	125	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675400228	675331794	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	675418211	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T19
1	0	1	Covered	T18,T13,T25
1	1	0	Covered	T6,T4,T22
1	1	1	Covered	T2,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T21
0	1	Covered	T25,T26,T75
1	0	Covered	T2,T15,T55

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T55

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T21
1	0	Covered	T28,T29
1	1	Covered	T25,T26,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T20,T25,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T3,T13,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T49,T30,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T20,T13
1	Covered	T2,T5,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T20,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T20
Phase1St	198	Covered	T2,T3,T20
Phase2St	215	Covered	T2,T3,T20
Phase3St	233	Covered	T2,T3,T20
TerminalSt	249	Covered	T2,T3,T20
TimeoutSt	159	Covered	T2,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T20
IdleSt->TimeoutSt	159	Covered	T2,T19,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T89,T102,T103
Phase0St->Phase1St	198	Covered	T2,T3,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T75,T54,T34
Phase1St->Phase2St	215	Covered	T2,T3,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T56,T104,T105
Phase2St->Phase3St	233	Covered	T2,T3,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T106,T93
Phase3St->TerminalSt	249	Covered	T2,T3,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T25,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T21
TimeoutSt->Phase0St	172	Covered	T25,T26,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T89,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T75,T54,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T104,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T106,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T26,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675576662	227	0	0
CheckAccumTrig0_A	675576662	469	0	0
CheckAccumTrig1_A	675576662	15	0	0
CheckClr_A	675576662	197	0	0
CheckEn_A	675401778	313244042	0	0
CheckPhase0_A	675576662	533	0	0
CheckPhase1_A	675576662	520	0	0
CheckPhase2_A	675576662	509	0	0
CheckPhase3_A	675576662	499	0	0
CheckTimeout0_A	675576662	1054	0	0
CheckTimeoutSt1_A	675576662	138383	0	0
CheckTimeoutSt2_A	675576662	983	0	0
CheckTimeoutStTrig_A	675576662	53	0	0
ErrorStAllEscAsserted_A	675576662	1267	0	0
ErrorStIsTerminal_A	675576662	1057	0	0
EscStateOut_A	675400228	675331794	0	0
u_state_regs_A	675576662	675418211	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	227	0	0
T10	46765	61	0	0
T11	0	37	0	0
T12	0	37	0	0
T29	389156	0	0	0
T37	0	67	0	0
T38	0	25	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	469	0	0
T2	67722	1	0	0
T3	229652	1	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	15	0	0
T23	0	2	0	0
T28	0	1	0	0
T34	0	1	0	0
T55	505679	1	0	0
T82	36214	0	0	0
T107	0	2	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	14327	0	0	0
T114	19375	0	0	0
T115	31819	0	0	0
T116	792017	0	0	0
T117	136637	0	0	0
T118	401378	0	0	0
T119	355759	0	0	0
T120	3977	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	197	0	0
T5	434980	1	0	0
T7	125168	0	0	0
T13	382056	0	0	0
T17	0	8	0	0
T22	25395	0	0	0
T25	876865	0	0	0
T26	0	2	0	0
T30	116895	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T47	12056	0	0	0
T48	53221	0	0	0
T49	25933	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	3	0	0
T75	0	2	0	0
T78	122304	0	0	0
T82	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675401778	313244042	0	0
T1	47733	39685	0	0
T2	67722	10005	0	0
T3	229652	10035	0	0
T4	264834	264826	0	0
T5	434980	257745	0	0
T6	66163	47952	0	0
T18	65351	62996	0	0
T19	228435	111599	0	0
T20	411961	5414	0	0
T21	25099	15739	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	533	0	0
T2	67722	1	0	0
T3	229652	1	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	6	0	0
T26	0	6	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	520	0	0
T2	67722	1	0	0
T3	229652	1	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	6	0	0
T26	0	6	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	509	0	0
T2	67722	1	0	0
T3	229652	1	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	6	0	0
T26	0	6	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	499	0	0
T2	67722	1	0	0
T3	229652	1	0	0
T4	264834	0	0	0
T5	434980	1	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T13	0	1	0	0
T18	65351	0	0	0
T19	228435	0	0	0
T20	411961	1	0	0
T21	25099	0	0	0
T25	0	6	0	0
T26	0	6	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1054	0	0
T2	67722	1	0	0
T3	229652	0	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T15	0	16	0	0
T18	65351	0	0	0
T19	228435	68	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	0	7	0	0
T25	0	2	0	0
T26	0	4	0	0
T30	0	1	0	0
T31	0	3	0	0
T35	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	138383	0	0
T2	67722	234	0	0
T3	229652	0	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T15	0	3153	0	0
T18	65351	0	0	0
T19	228435	13230	0	0
T20	411961	0	0	0
T21	25099	345	0	0
T22	0	381	0	0
T25	0	155	0	0
T26	0	414	0	0
T30	0	239	0	0
T31	0	307	0	0
T35	0	94	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	983	0	0
T2	67722	1	0	0
T3	229652	0	0	0
T4	264834	0	0	0
T5	434980	0	0	0
T6	66163	0	0	0
T7	125168	0	0	0
T15	0	15	0	0
T18	65351	0	0	0
T19	228435	67	0	0
T20	411961	0	0	0
T21	25099	2	0	0
T22	0	7	0	0
T25	0	1	0	0
T26	0	2	0	0
T30	0	1	0	0
T31	0	3	0	0
T35	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	53	0	0
T8	112113	0	0	0
T14	360342	0	0	0
T23	0	1	0	0
T25	876865	1	0	0
T26	790633	2	0	0
T27	44551	0	0	0
T33	0	1	0	0
T50	149709	0	0	0
T51	12787	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T67	22160	0	0	0
T68	2776	0	0	0
T69	122179	0	0	0
T75	0	2	0	0
T82	0	1	0	0
T84	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1267	0	0
T10	46765	351	0	0
T11	0	175	0	0
T12	0	194	0	0
T29	389156	0	0	0
T37	0	348	0	0
T38	0	199	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	1057	0	0
T10	46765	291	0	0
T11	0	145	0	0
T12	0	164	0	0
T29	389156	0	0	0
T37	0	288	0	0
T38	0	169	0	0
T39	932540	0	0	0
T40	161323	0	0	0
T41	225634	0	0	0
T42	138120	0	0	0
T43	141293	0	0	0
T44	487971	0	0	0
T45	37581	0	0	0
T46	865122	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675400228	675331794	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675576662	675418211	0	0
T1	47733	47680	0	0
T2	67722	67669	0	0
T3	229652	229645	0	0
T4	264834	264826	0	0
T5	434980	434920	0	0
T6	66163	65996	0	0
T18	65351	65295	0	0
T19	228435	228423	0	0
T20	411961	411888	0	0
T21	25099	25026	0	0