Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T192,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14069	0	0
DisabledNoTrigBkwd_A	2147483647	847681	0	0
DisabledNoTrigFwd_A	2147483647	1465443059	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14069	0	0
T7	2106	1279	0	0
T8	18709	0	0	0
T9	766985	0	0	0
T10	39205	0	0	0
T16	126942	0	0	0
T17	353940	0	0	0
T22	58722	0	0	0
T25	202105	0	0	0
T30	0	217	0	0
T38	35101	0	0	0
T69	6028	0	0	0
T82	0	841	0	0
T192	2767	653	0	0
T193	0	652	0	0
T194	0	873	0	0
T195	0	718	0	0
T196	0	694	0	0
T197	0	396	0	0
T198	0	164	0	0
T199	0	922	0	0
T200	0	618	0	0
T201	0	1513	0	0
T202	0	124	0	0
T203	0	528	0	0
T204	0	759	0	0
T205	3522	991	0	0
T206	0	1008	0	0
T207	0	456	0	0
T208	0	663	0	0
T209	12140	0	0	0
T210	109632	0	0	0
T211	26898	0	0	0
T212	19795	0	0	0
T213	20133	0	0	0
T214	95532	0	0	0
T215	34891	0	0	0
T216	906623	0	0	0
T217	615508	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	847681	0	0
T1	409347	5297	0	0
T2	25521	0	0	0
T3	1476388	1253	0	0
T4	451780	50	0	0
T5	141680	54	0	0
T6	1017604	3956	0	0
T7	8424	40	0	0
T8	74836	562	0	0
T9	3067940	3	0	0
T10	156820	47	0	0
T16	126942	0	0	0
T17	0	7672	0	0
T18	0	130	0	0
T20	0	7	0	0
T22	58722	55	0	0
T24	0	53	0	0
T25	0	49	0	0
T38	0	1	0	0
T39	0	384	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1465443059	0	0
T1	545796	275955	0	0
T2	34028	25933	0	0
T3	1476388	397307	0	0
T4	451780	306247	0	0
T5	141680	112043	0	0
T6	1017604	514384	0	0
T7	8424	2556	0	0
T8	74836	34045	0	0
T9	3067940	1117273	0	0
T10	156820	46931	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T201,T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662190782	2916	0	0
DisabledNoTrigBkwd_A	662190782	276685	0	0
DisabledNoTrigFwd_A	662190782	328048057	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	2916	0	0
T7	2106	1279	0	0
T8	18709	0	0	0
T9	766985	0	0	0
T10	39205	0	0	0
T16	126942	0	0	0
T17	353940	0	0	0
T22	58722	0	0	0
T25	202105	0	0	0
T38	35101	0	0	0
T69	6028	0	0	0
T201	0	1513	0	0
T202	0	124	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	276685	0	0
T1	136449	2914	0	0
T2	8507	0	0	0
T3	369097	1	0	0
T4	112945	35	0	0
T5	35420	49	0	0
T6	254401	2205	0	0
T7	2106	40	0	0
T8	18709	2	0	0
T9	766985	0	0	0
T10	39205	18	0	0
T17	0	3651	0	0
T38	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	328048057	0	0
T1	136449	597	0	0
T2	8507	649	0	0
T3	369097	6545	0	0
T4	112945	8129	0	0
T5	35420	9914	0	0
T6	254401	2782	0	0
T7	2106	633	0	0
T8	18709	13199	0	0
T9	766985	3357	0	0
T10	39205	2098	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662190782	991	0	0
DisabledNoTrigBkwd_A	662190782	189119	0	0
DisabledNoTrigFwd_A	662190782	387582529	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	991	0	0
T205	3522	991	0	0
T209	12140	0	0	0
T210	109632	0	0	0
T211	26898	0	0	0
T212	19795	0	0	0
T213	20133	0	0	0
T214	95532	0	0	0
T215	34891	0	0	0
T216	906623	0	0	0
T217	615508	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	189119	0	0
T1	136449	24	0	0
T2	8507	0	0	0
T3	369097	428	0	0
T4	112945	13	0	0
T5	35420	5	0	0
T6	254401	0	0	0
T7	2106	0	0	0
T8	18709	528	0	0
T9	766985	0	0	0
T10	39205	13	0	0
T17	0	237	0	0
T22	0	52	0	0
T24	0	33	0	0
T25	0	49	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	387582529	0	0
T1	136449	136058	0	0
T2	8507	8428	0	0
T3	369097	6561	0	0
T4	112945	83052	0	0
T5	35420	31435	0	0
T6	254401	254395	0	0
T7	2106	637	0	0
T8	18709	6059	0	0
T9	766985	3371	0	0
T10	39205	11095	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T4,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T193,T195
1	1	Covered	T3,T4,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662190782	6527	0	0
DisabledNoTrigBkwd_A	662190782	213561	0	0
DisabledNoTrigFwd_A	662190782	369324794	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	6527	0	0
T41	788482	0	0	0
T70	124032	0	0	0
T73	641331	0	0	0
T74	51648	0	0	0
T80	344216	0	0	0
T81	270698	0	0	0
T82	3221	0	0	0
T83	28408	0	0	0
T192	2767	653	0	0
T193	1785	652	0	0
T195	0	718	0	0
T196	0	694	0	0
T197	0	396	0	0
T203	0	528	0	0
T204	0	759	0	0
T206	0	1008	0	0
T207	0	456	0	0
T208	0	663	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	213561	0	0
T3	369097	824	0	0
T4	112945	2	0	0
T5	35420	0	0	0
T6	254401	1751	0	0
T7	2106	0	0	0
T8	18709	29	0	0
T9	766985	0	0	0
T10	39205	12	0	0
T16	126942	0	0	0
T17	0	147	0	0
T18	0	69	0	0
T22	58722	2	0	0
T24	0	4	0	0
T39	0	384	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	369324794	0	0
T1	136449	136441	0	0
T2	8507	8428	0	0
T3	369097	15111	0	0
T4	112945	107317	0	0
T5	35420	35347	0	0
T6	254401	2812	0	0
T7	2106	641	0	0
T8	18709	593	0	0
T9	766985	766921	0	0
T10	39205	5876	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T30,T194
1	1	Covered	T1,T4,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662190782	3635	0	0
DisabledNoTrigBkwd_A	662190782	168316	0	0
DisabledNoTrigFwd_A	662190782	380487679	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	3635	0	0
T30	0	217	0	0
T42	307675	0	0	0
T70	124032	0	0	0
T71	285429	0	0	0
T72	251755	0	0	0
T82	3221	841	0	0
T83	28408	0	0	0
T84	28615	0	0	0
T85	23940	0	0	0
T112	59388	0	0	0
T194	0	873	0	0
T198	0	164	0	0
T199	0	922	0	0
T200	0	618	0	0
T218	45276	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	168316	0	0
T1	136449	2359	0	0
T2	8507	0	0	0
T3	369097	0	0	0
T4	112945	0	0	0
T5	35420	0	0	0
T6	254401	0	0	0
T7	2106	0	0	0
T8	18709	3	0	0
T9	766985	3	0	0
T10	39205	4	0	0
T17	0	3637	0	0
T18	0	61	0	0
T20	0	7	0	0
T22	0	1	0	0
T24	0	16	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662190782	380487679	0	0
T1	136449	2859	0	0
T2	8507	8428	0	0
T3	369097	369090	0	0
T4	112945	107749	0	0
T5	35420	35347	0	0
T6	254401	254395	0	0
T7	2106	645	0	0
T8	18709	14194	0	0
T9	766985	343624	0	0
T10	39205	27862	0	0