Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 100.00 93.33 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 93.33 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.11 100.00 95.56 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.26 100.00 95.56 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.11 100.00 95.56 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.26 100.00 95.56 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.11 100.00 95.56 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.26 100.00 95.56 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : alert_handler_esc_timer
Line No.TotalCoveredPercent
TOTAL101101100.00
CONT_ASSIGN8511100.00
ALWAYS1348989100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
ALWAYS30533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
169 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
178 1 1
179 1 1
181 1 1
182 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
MISSING_ELSE
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
268 1 1
269 1 1
283 1 1
284 1 1
285 1 1
MISSING_ELSE
292 4 4
295 4 4
305 3 3


Cond Coverage for Module : alert_handler_esc_timer
TotalCoveredPercent
Conditions474493.62
Logical474493.62
Non-Logical00
Event00

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----
-1--2-StatusTests
01CoveredT11,T12,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT14,T15
111CoveredT1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT3,T4,T7
110CoveredT1,T4,T5
111CoveredT1,T2,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T10
01CoveredT16,T17,T18
10CoveredT10,T19,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----
-1--2--3-StatusTests
011CoveredT1,T2,T10
101Not Covered
110Not Covered
111CoveredT10,T19,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T10
10CoveredT21
11CoveredT16,T17,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT4,T5,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT5,T6,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T4

FSM Coverage for Module : alert_handler_esc_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 20 14 70.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
FsmErrorSt 284 Covered T11,T12,T13
IdleSt 181 Covered T1,T2,T3
Phase0St 152 Covered T1,T3,T4
Phase1St 198 Covered T1,T3,T4
Phase2St 215 Covered T1,T3,T4
Phase3St 233 Covered T1,T3,T4
TerminalSt 249 Covered T1,T3,T4
TimeoutSt 159 Covered T1,T2,T10


transitionsLine No.CoveredTests
IdleSt->FsmErrorSt 284 Covered T11,T12,T13
IdleSt->Phase0St 152 Covered T1,T3,T4
IdleSt->TimeoutSt 159 Covered T1,T2,T10
Phase0St->FsmErrorSt 284 Not Covered
Phase0St->IdleSt 194 Covered T4,T17,T23
Phase0St->Phase1St 198 Covered T1,T3,T4
Phase1St->FsmErrorSt 284 Not Covered
Phase1St->IdleSt 211 Covered T1,T17,T24
Phase1St->Phase2St 215 Covered T1,T3,T4
Phase2St->FsmErrorSt 284 Not Covered
Phase2St->IdleSt 229 Covered T17,T25,T18
Phase2St->Phase3St 233 Covered T1,T3,T4
Phase3St->FsmErrorSt 284 Not Covered
Phase3St->IdleSt 245 Covered T17,T26,T18
Phase3St->TerminalSt 249 Covered T1,T3,T4
TerminalSt->FsmErrorSt 284 Not Covered
TerminalSt->IdleSt 261 Covered T1,T3,T5
TimeoutSt->FsmErrorSt 284 Not Covered
TimeoutSt->IdleSt 181 Covered T1,T2,T10
TimeoutSt->Phase0St 172 Covered T10,T16,T17



Branch Coverage for Module : alert_handler_esc_timer
Line No.TotalCoveredPercent
Branches 26 26 100.00
CASE 144 22 22 100.00
IF 283 2 2 100.00
IF 305 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 case (state_q) -2-: 151 if (((accu_trig_i && en_i) && (!clr_i))) -3-: 157 if (((timeout_en_i && (!cnt_ge)) && en_i)) -4-: 171 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i))) -5-: 178 if (timeout_en_i) -6-: 193 if (clr_i) -7-: 197 if (cnt_ge) -8-: 210 if (clr_i) -9-: 214 if (cnt_ge) -10-: 228 if (clr_i) -11-: 232 if (cnt_ge) -12-: 244 if (clr_i) -13-: 248 if (cnt_ge) -14-: 260 if (clr_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
IdleSt 1 - - - - - - - - - - - - Covered T1,T3,T4
IdleSt 0 1 - - - - - - - - - - - Covered T1,T2,T10
IdleSt 0 0 - - - - - - - - - - - Covered T1,T2,T3
TimeoutSt - - 1 - - - - - - - - - - Covered T10,T16,T17
TimeoutSt - - 0 1 - - - - - - - - - Covered T1,T2,T10
TimeoutSt - - 0 0 - - - - - - - - - Covered T1,T2,T10
Phase0St - - - - 1 - - - - - - - - Covered T4,T17,T23
Phase0St - - - - 0 1 - - - - - - - Covered T1,T3,T4
Phase0St - - - - 0 0 - - - - - - - Covered T1,T3,T4
Phase1St - - - - - - 1 - - - - - - Covered T1,T17,T24
Phase1St - - - - - - 0 1 - - - - - Covered T1,T3,T4
Phase1St - - - - - - 0 0 - - - - - Covered T1,T3,T4
Phase2St - - - - - - - - 1 - - - - Covered T17,T25,T18
Phase2St - - - - - - - - 0 1 - - - Covered T1,T3,T4
Phase2St - - - - - - - - 0 0 - - - Covered T1,T3,T4
Phase3St - - - - - - - - - - 1 - - Covered T17,T26,T18
Phase3St - - - - - - - - - - 0 1 - Covered T1,T3,T4
Phase3St - - - - - - - - - - 0 0 - Covered T1,T3,T4
TerminalSt - - - - - - - - - - - - 1 Covered T1,T3,T5
TerminalSt - - - - - - - - - - - - 0 Covered T1,T3,T4
FsmErrorSt - - - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - - - Covered T11,T12,T13


LineNo. Expression -1-: 283 if ((accu_fail_i || cnt_error))

Branches:
-1-StatusTests
1 Covered T11,T12,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 305 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : alert_handler_esc_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccuFailToFsmError_A 2147483647 1193 0 0
CheckAccumTrig0_A 2147483647 2391 0 0
CheckAccumTrig1_A 2147483647 121 0 0
CheckClr_A 2147483647 1145 0 0
CheckEn_A 2147483647 1092161879 0 0
CheckPhase0_A 2147483647 2712 0 0
CheckPhase1_A 2147483647 2666 0 0
CheckPhase2_A 2147483647 2614 0 0
CheckPhase3_A 2147483647 2555 0 0
CheckTimeout0_A 2147483647 6693 0 0
CheckTimeoutSt1_A 2147483647 701357 0 0
CheckTimeoutSt2_A 2147483647 6327 0 0
CheckTimeoutStTrig_A 2147483647 241 0 0
ErrorStAllEscAsserted_A 2147483647 6496 0 0
ErrorStIsTerminal_A 2147483647 5416 0 0
EscStateOut_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


AccuFailToFsmError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1193 0 0
T11 120508 169 0 0
T12 0 272 0 0
T13 0 312 0 0
T27 0 218 0 0
T28 0 222 0 0
T29 17176 0 0 0
T30 3784 0 0 0
T31 890468 0 0 0
T32 494892 0 0 0
T33 113332 0 0 0
T34 126716 0 0 0
T35 116104 0 0 0
T36 1188408 0 0 0
T37 1613908 0 0 0

CheckAccumTrig0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2391 0 0
T1 409347 13 0 0
T2 25521 0 0 0
T3 1476388 3 0 0
T4 451780 3 0 0
T5 141680 2 0 0
T6 1017604 2 0 0
T7 8424 1 0 0
T8 74836 4 0 0
T9 3067940 1 0 0
T10 156820 10 0 0
T16 126942 0 0 0
T17 0 58 0 0
T18 0 7 0 0
T20 0 1 0 0
T22 58722 2 0 0
T24 0 3 0 0
T25 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 1 0 0

CheckAccumTrig1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 121 0 0
T10 39205 1 0 0
T18 419825 0 0 0
T19 74710 1 0 0
T20 72258 1 0 0
T21 0 2 0 0
T24 161004 0 0 0
T26 46163 0 0 0
T39 110386 0 0 0
T40 383283 0 0 0
T42 307675 4 0 0
T43 947336 1 0 0
T44 11289 1 0 0
T45 0 4 0 0
T46 0 2 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 2 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T54 0 1 0 0
T55 0 1 0 0
T56 0 1 0 0
T57 0 1 0 0
T58 0 2 0 0
T59 19066 0 0 0
T60 794660 0 0 0
T61 870798 0 0 0
T62 6727 0 0 0
T63 334099 0 0 0
T64 29110 0 0 0
T65 94950 0 0 0
T66 108145 0 0 0
T67 30540 0 0 0
T68 30941 0 0 0

CheckClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1145 0 0
T1 272898 10 0 0
T2 17014 0 0 0
T3 738194 1 0 0
T4 338835 1 0 0
T5 141680 1 0 0
T6 1017604 0 0 0
T7 8424 0 0 0
T8 74836 0 0 0
T9 3067940 0 0 0
T10 156820 7 0 0
T16 253884 0 0 0
T17 707880 40 0 0
T18 0 17 0 0
T19 0 1 0 0
T22 117444 1 0 0
T24 0 1 0 0
T25 0 1 0 0
T26 0 1 0 0
T38 35101 0 0 0
T42 0 8 0 0
T43 0 4 0 0
T44 0 1 0 0
T62 0 2 0 0
T63 0 3 0 0
T69 0 1 0 0
T70 0 13 0 0
T71 0 2 0 0
T72 0 3 0 0

CheckEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1092161879 0 0
T1 545796 140498 0 0
T2 34028 25930 0 0
T3 1476388 397306 0 0
T4 451780 236882 0 0
T5 141680 104450 0 0
T6 1017604 514384 0 0
T7 8424 2556 0 0
T8 74836 13659 0 0
T9 3067940 1117272 0 0
T10 156820 30183 0 0

CheckPhase0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2712 0 0
T1 409347 13 0 0
T2 25521 0 0 0
T3 1476388 3 0 0
T4 451780 2 0 0
T5 141680 2 0 0
T6 1017604 2 0 0
T7 8424 1 0 0
T8 74836 4 0 0
T9 3067940 1 0 0
T10 156820 11 0 0
T16 126942 1 0 0
T17 0 60 0 0
T18 0 10 0 0
T20 0 1 0 0
T22 58722 3 0 0
T24 0 2 0 0
T25 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0

CheckPhase1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2666 0 0
T1 409347 12 0 0
T2 25521 0 0 0
T3 1476388 3 0 0
T4 451780 2 0 0
T5 141680 2 0 0
T6 1017604 2 0 0
T7 8424 1 0 0
T8 74836 4 0 0
T9 3067940 1 0 0
T10 156820 11 0 0
T16 126942 1 0 0
T17 0 56 0 0
T18 0 10 0 0
T20 0 2 0 0
T22 58722 3 0 0
T24 0 1 0 0
T25 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0

CheckPhase2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2614 0 0
T1 409347 12 0 0
T2 25521 0 0 0
T3 1476388 3 0 0
T4 451780 2 0 0
T5 141680 2 0 0
T6 1017604 2 0 0
T7 8424 1 0 0
T8 74836 4 0 0
T9 3067940 1 0 0
T10 156820 11 0 0
T16 126942 1 0 0
T17 0 51 0 0
T18 0 10 0 0
T20 0 2 0 0
T22 58722 3 0 0
T24 0 1 0 0
T25 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0

CheckPhase3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2555 0 0
T1 409347 12 0 0
T2 25521 0 0 0
T3 1476388 3 0 0
T4 451780 2 0 0
T5 141680 2 0 0
T6 1017604 2 0 0
T7 8424 1 0 0
T8 74836 4 0 0
T9 3067940 1 0 0
T10 156820 11 0 0
T16 126942 1 0 0
T17 0 49 0 0
T18 0 10 0 0
T20 0 2 0 0
T22 58722 3 0 0
T24 0 1 0 0
T25 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0

CheckTimeout0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6693 0 0
T1 136449 1 0 0
T2 8507 1 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 78410 2 0 0
T16 380826 28 0 0
T17 1061820 331 0 0
T18 0 26 0 0
T19 112065 1 0 0
T20 0 2 0 0
T22 176166 2 0 0
T24 241506 0 0 0
T25 606315 0 0 0
T26 92326 2 0 0
T38 105303 0 0 0
T42 0 46 0 0
T43 0 60 0 0
T59 28599 1 0 0
T62 0 2 0 0
T63 0 2 0 0
T64 0 2 0 0
T69 18084 0 0 0
T70 0 19 0 0
T73 0 6 0 0
T74 0 3 0 0

CheckTimeoutSt1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 701357 0 0
T1 136449 17 0 0
T2 8507 60 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 78410 58 0 0
T16 380826 5590 0 0
T17 1061820 20556 0 0
T18 0 3558 0 0
T19 112065 1 0 0
T20 0 142 0 0
T22 176166 19 0 0
T24 241506 0 0 0
T25 606315 0 0 0
T26 92326 299 0 0
T38 105303 0 0 0
T42 0 8928 0 0
T43 0 6165 0 0
T59 28599 141 0 0
T62 0 1029 0 0
T63 0 203 0 0
T64 0 378 0 0
T69 18084 0 0 0
T70 0 1716 0 0
T73 0 818 0 0
T74 0 359 0 0

CheckTimeoutSt2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6327 0 0
T1 136449 1 0 0
T2 8507 1 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 78410 1 0 0
T16 380826 27 0 0
T17 1061820 326 0 0
T18 0 22 0 0
T19 112065 0 0 0
T22 176166 1 0 0
T24 241506 0 0 0
T25 606315 0 0 0
T26 92326 2 0 0
T38 105303 0 0 0
T42 0 41 0 0
T43 0 128 0 0
T59 28599 1 0 0
T63 0 2 0 0
T64 0 5 0 0
T66 0 1 0 0
T67 0 2 0 0
T69 18084 0 0 0
T70 0 16 0 0
T73 0 3 0 0
T74 0 2 0 0

CheckTimeoutStTrig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 241 0 0
T16 126942 1 0 0
T17 707880 1 0 0
T18 0 3 0 0
T19 74710 0 0 0
T20 0 1 0 0
T22 58722 0 0 0
T24 161004 0 0 0
T25 404210 0 0 0
T26 92326 0 0 0
T34 0 1 0 0
T37 0 1 0 0
T38 70202 0 0 0
T39 110386 0 0 0
T42 0 2 0 0
T43 0 2 0 0
T49 0 4 0 0
T59 19066 0 0 0
T62 0 1 0 0
T64 0 1 0 0
T66 0 1 0 0
T68 0 3 0 0
T69 12056 0 0 0
T70 124032 3 0 0
T71 285429 0 0 0
T73 641331 2 0 0
T74 51648 1 0 0
T75 0 1 0 0
T76 0 2 0 0
T77 0 1 0 0
T78 0 2 0 0
T79 0 2 0 0
T80 344216 0 0 0
T81 270698 0 0 0
T82 3221 0 0 0
T83 28408 0 0 0
T84 28615 0 0 0
T85 23940 0 0 0

ErrorStAllEscAsserted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6496 0 0
T11 120508 736 0 0
T12 0 1450 0 0
T13 0 1430 0 0
T27 0 1456 0 0
T28 0 1424 0 0
T29 17176 0 0 0
T30 3784 0 0 0
T31 890468 0 0 0
T32 494892 0 0 0
T33 113332 0 0 0
T34 126716 0 0 0
T35 116104 0 0 0
T36 1188408 0 0 0
T37 1613908 0 0 0

ErrorStIsTerminal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5416 0 0
T11 120508 616 0 0
T12 0 1210 0 0
T13 0 1190 0 0
T27 0 1216 0 0
T28 0 1184 0 0
T29 17176 0 0 0
T30 3784 0 0 0
T31 890468 0 0 0
T32 494892 0 0 0
T33 113332 0 0 0
T34 126716 0 0 0
T35 116104 0 0 0
T36 1188408 0 0 0
T37 1613908 0 0 0

EscStateOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 545796 545764 0 0
T2 34028 33712 0 0
T3 1476388 1476360 0 0
T4 451780 451484 0 0
T5 141680 141388 0 0
T6 1017604 1017580 0 0
T7 8424 8188 0 0
T8 74836 74488 0 0
T9 3067940 3067684 0 0
T10 156820 156544 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 545796 545764 0 0
T2 34028 33712 0 0
T3 1476388 1476360 0 0
T4 451780 451484 0 0
T5 141680 141388 0 0
T6 1017604 1017580 0 0
T7 8424 8188 0 0
T8 74836 74488 0 0
T9 3067940 3067684 0 0
T10 156820 156544 0 0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Line No.TotalCoveredPercent
TOTAL101101100.00
CONT_ASSIGN8511100.00
ALWAYS1348989100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
ALWAYS30533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
169 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
178 1 1
179 1 1
181 1 1
182 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
MISSING_ELSE
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
268 1 1
269 1 1
283 1 1
284 1 1
285 1 1
MISSING_ELSE
292 4 4
295 4 4
305 3 3


Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
TotalCoveredPercent
Conditions454293.33
Logical454293.33
Non-Logical00
Event00

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----
-1--2-StatusTests
01CoveredT11,T12,T13
10CoveredT1,T8,T9
11CoveredT1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--
-1--2-StatusTests
01CoveredT1,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T8,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T4,T7
101Excluded VC_COV_UNR
110Not Covered
111CoveredT1,T8,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-
-1--2--3-StatusTests
011CoveredT1,T8,T10
101CoveredT4,T9,T17
110CoveredT1,T4,T5
111CoveredT16,T22,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------
-1--2-StatusTests
00CoveredT16,T22,T17
01CoveredT17,T18,T73
10CoveredT22,T17,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT16,T22,T17
101Excluded VC_COV_UNR
110Not Covered
111CoveredT22,T17,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----
-1--2-StatusTests
01CoveredT16,T22,T17
10Not Covered
11CoveredT17,T18,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------
-1-StatusTests
0CoveredT1,T8,T9
1CoveredT10,T22,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------
-1-StatusTests
0CoveredT1,T8,T9
1CoveredT1,T17,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------
-1-StatusTests
0CoveredT1,T8,T10
1CoveredT1,T9,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------
-1-StatusTests
0CoveredT1,T9,T10
1CoveredT1,T8,T10

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T10,T22

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 14 14 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
FsmErrorSt 284 Covered T11,T12,T13
IdleSt 181 Covered T1,T2,T3
Phase0St 152 Covered T1,T8,T9
Phase1St 198 Covered T1,T8,T9
Phase2St 215 Covered T1,T8,T9
Phase3St 233 Covered T1,T8,T9
TerminalSt 249 Covered T1,T8,T9
TimeoutSt 159 Covered T16,T22,T17


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->FsmErrorSt 284 Covered T11,T12,T13
IdleSt->Phase0St 152 Covered T1,T8,T9
IdleSt->TimeoutSt 159 Covered T16,T22,T17
Phase0St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt 194 Covered T17,T70,T86
Phase0St->Phase1St 198 Covered T1,T8,T9
Phase1St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt 211 Covered T17,T87,T88
Phase1St->Phase2St 215 Covered T1,T8,T9
Phase2St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt 229 Covered T17,T31,T55
Phase2St->Phase3St 233 Covered T1,T8,T9
Phase3St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt 245 Covered T17,T70,T89
Phase3St->TerminalSt 249 Covered T1,T8,T9
TerminalSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt 261 Covered T1,T10,T22
TimeoutSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt 181 Covered T16,T22,T17
TimeoutSt->Phase0St 172 Covered T22,T17,T18



Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Line No.TotalCoveredPercent
Branches 26 26 100.00
CASE 144 22 22 100.00
IF 283 2 2 100.00
IF 305 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 case (state_q) -2-: 151 if (((accu_trig_i && en_i) && (!clr_i))) -3-: 157 if (((timeout_en_i && (!cnt_ge)) && en_i)) -4-: 171 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i))) -5-: 178 if (timeout_en_i) -6-: 193 if (clr_i) -7-: 197 if (cnt_ge) -8-: 210 if (clr_i) -9-: 214 if (cnt_ge) -10-: 228 if (clr_i) -11-: 232 if (cnt_ge) -12-: 244 if (clr_i) -13-: 248 if (cnt_ge) -14-: 260 if (clr_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
IdleSt 1 - - - - - - - - - - - - Covered T1,T8,T9
IdleSt 0 1 - - - - - - - - - - - Covered T16,T22,T17
IdleSt 0 0 - - - - - - - - - - - Covered T1,T2,T3
TimeoutSt - - 1 - - - - - - - - - - Covered T22,T17,T18
TimeoutSt - - 0 1 - - - - - - - - - Covered T16,T22,T17
TimeoutSt - - 0 0 - - - - - - - - - Covered T16,T22,T17
Phase0St - - - - 1 - - - - - - - - Covered T17,T70,T86
Phase0St - - - - 0 1 - - - - - - - Covered T1,T8,T9
Phase0St - - - - 0 0 - - - - - - - Covered T1,T8,T9
Phase1St - - - - - - 1 - - - - - - Covered T17,T87,T88
Phase1St - - - - - - 0 1 - - - - - Covered T1,T8,T9
Phase1St - - - - - - 0 0 - - - - - Covered T1,T8,T9
Phase2St - - - - - - - - 1 - - - - Covered T17,T31,T55
Phase2St - - - - - - - - 0 1 - - - Covered T1,T8,T9
Phase2St - - - - - - - - 0 0 - - - Covered T1,T8,T9
Phase3St - - - - - - - - - - 1 - - Covered T17,T70,T89
Phase3St - - - - - - - - - - 0 1 - Covered T1,T8,T9
Phase3St - - - - - - - - - - 0 0 - Covered T1,T8,T9
TerminalSt - - - - - - - - - - - - 1 Covered T1,T10,T22
TerminalSt - - - - - - - - - - - - 0 Covered T1,T8,T9
FsmErrorSt - - - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - - - Covered T11,T12,T13


LineNo. Expression -1-: 283 if ((accu_fail_i || cnt_error))

Branches:
-1-StatusTests
1 Covered T11,T12,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 305 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccuFailToFsmError_A 662190782 288 0 0
CheckAccumTrig0_A 662190782 457 0 0
CheckAccumTrig1_A 662190782 33 0 0
CheckClr_A 662190782 198 0 0
CheckEn_A 661822219 289241853 0 0
CheckPhase0_A 662190782 543 0 0
CheckPhase1_A 662190782 537 0 0
CheckPhase2_A 662190782 529 0 0
CheckPhase3_A 662190782 518 0 0
CheckTimeout0_A 662190782 1823 0 0
CheckTimeoutSt1_A 662190782 222416 0 0
CheckTimeoutSt2_A 662190782 1729 0 0
CheckTimeoutStTrig_A 662190782 60 0 0
ErrorStAllEscAsserted_A 662190782 1625 0 0
ErrorStIsTerminal_A 662190782 1355 0 0
EscStateOut_A 661820635 661752236 0 0
u_state_regs_A 662190782 662008565 0 0


AccuFailToFsmError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 288 0 0
T11 30127 35 0 0
T12 0 80 0 0
T13 0 66 0 0
T27 0 50 0 0
T28 0 57 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

CheckAccumTrig0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 457 0 0
T1 136449 3 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 1 0 0
T10 39205 2 0 0
T17 0 17 0 0
T18 0 3 0 0
T20 0 1 0 0
T24 0 1 0 0
T40 0 1 0 0
T41 0 1 0 0

CheckAccumTrig1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 33 0 0
T17 353940 2 0 0
T19 37355 0 0 0
T21 0 1 0 0
T22 58722 1 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T39 110386 0 0 0
T42 0 1 0 0
T50 0 1 0 0
T59 9533 0 0 0
T67 0 1 0 0
T69 6028 0 0 0
T79 0 2 0 0
T90 0 1 0 0
T91 0 1 0 0
T92 0 1 0 0

CheckClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 198 0 0
T1 136449 2 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 1 0 0
T17 0 13 0 0
T18 0 1 0 0
T22 0 1 0 0
T42 0 1 0 0
T43 0 2 0 0
T63 0 1 0 0
T70 0 7 0 0
T73 0 2 0 0

CheckEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661822219 289241853 0 0
T1 136449 2859 0 0
T2 8507 8427 0 0
T3 369097 369089 0 0
T4 112945 107748 0 0
T5 35420 35346 0 0
T6 254401 254395 0 0
T7 2106 645 0 0
T8 18709 597 0 0
T9 766985 343624 0 0
T10 39205 11114 0 0

CheckPhase0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 543 0 0
T1 136449 3 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 1 0 0
T10 39205 2 0 0
T17 0 20 0 0
T18 0 4 0 0
T20 0 1 0 0
T22 0 1 0 0
T24 0 1 0 0
T40 0 1 0 0

CheckPhase1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 537 0 0
T1 136449 3 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 1 0 0
T10 39205 2 0 0
T17 0 19 0 0
T18 0 4 0 0
T20 0 1 0 0
T22 0 1 0 0
T24 0 1 0 0
T40 0 1 0 0

CheckPhase2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 529 0 0
T1 136449 3 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 1 0 0
T10 39205 2 0 0
T17 0 16 0 0
T18 0 4 0 0
T20 0 1 0 0
T22 0 1 0 0
T24 0 1 0 0
T40 0 1 0 0

CheckPhase3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 518 0 0
T1 136449 3 0 0
T2 8507 0 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 1 0 0
T10 39205 2 0 0
T17 0 15 0 0
T18 0 4 0 0
T20 0 1 0 0
T22 0 1 0 0
T24 0 1 0 0
T40 0 1 0 0

CheckTimeout0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1823 0 0
T16 126942 11 0 0
T17 353940 28 0 0
T18 0 8 0 0
T19 37355 0 0 0
T22 58722 2 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 15 0 0
T43 0 58 0 0
T59 9533 0 0 0
T62 0 1 0 0
T69 6028 0 0 0
T70 0 9 0 0
T73 0 2 0 0
T74 0 1 0 0

CheckTimeoutSt1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 222416 0 0
T16 126942 2280 0 0
T17 353940 1875 0 0
T18 0 1197 0 0
T19 37355 0 0 0
T22 58722 19 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 2501 0 0
T43 0 5989 0 0
T59 9533 0 0 0
T62 0 642 0 0
T69 6028 0 0 0
T70 0 669 0 0
T73 0 114 0 0
T74 0 170 0 0

CheckTimeoutSt2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1729 0 0
T16 126942 11 0 0
T17 353940 24 0 0
T18 0 7 0 0
T19 37355 0 0 0
T22 58722 1 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 13 0 0
T43 0 56 0 0
T59 9533 0 0 0
T64 0 1 0 0
T69 6028 0 0 0
T70 0 9 0 0
T73 0 1 0 0
T74 0 1 0 0

CheckTimeoutStTrig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 60 0 0
T17 353940 2 0 0
T18 0 1 0 0
T19 37355 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T39 110386 0 0 0
T42 0 1 0 0
T43 0 2 0 0
T45 0 1 0 0
T46 0 1 0 0
T59 9533 0 0 0
T60 794660 0 0 0
T62 0 1 0 0
T69 6028 0 0 0
T73 0 1 0 0
T77 0 1 0 0
T79 0 1 0 0

ErrorStAllEscAsserted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1625 0 0
T11 30127 190 0 0
T12 0 362 0 0
T13 0 354 0 0
T27 0 364 0 0
T28 0 355 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

ErrorStIsTerminal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1355 0 0
T11 30127 160 0 0
T12 0 302 0 0
T13 0 294 0 0
T27 0 304 0 0
T28 0 295 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

EscStateOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661820635 661752236 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 662008565 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Line No.TotalCoveredPercent
TOTAL101101100.00
CONT_ASSIGN8511100.00
ALWAYS1348989100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
ALWAYS30533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
169 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
178 1 1
179 1 1
181 1 1
182 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
MISSING_ELSE
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
268 1 1
269 1 1
283 1 1
284 1 1
285 1 1
MISSING_ELSE
292 4 4
295 4 4
305 3 3


Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
TotalCoveredPercent
Conditions454395.56
Logical454395.56
Non-Logical00
Event00

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----
-1--2-StatusTests
01CoveredT11,T12,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Not Covered
111CoveredT1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT3,T7,T10
110CoveredT8,T16,T22
111CoveredT1,T2,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T16
01CoveredT73,T70,T43
10CoveredT19,T42,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T16
101Excluded VC_COV_UNR
110Not Covered
111CoveredT19,T42,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T16
10CoveredT21
11CoveredT73,T70,T43

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT7,T8,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT5,T17,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT6,T10,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT3,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T4,T6

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 14 14 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
FsmErrorSt 284 Covered T11,T12,T13
IdleSt 181 Covered T1,T2,T3
Phase0St 152 Covered T1,T3,T4
Phase1St 198 Covered T1,T3,T4
Phase2St 215 Covered T1,T3,T4
Phase3St 233 Covered T1,T3,T4
TerminalSt 249 Covered T1,T3,T4
TimeoutSt 159 Covered T1,T2,T16


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->FsmErrorSt 284 Covered T11,T12,T13
IdleSt->Phase0St 152 Covered T1,T3,T4
IdleSt->TimeoutSt 159 Covered T1,T2,T16
Phase0St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt 194 Covered T17,T45,T93
Phase0St->Phase1St 198 Covered T1,T3,T4
Phase1St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt 211 Covered T1,T17,T94
Phase1St->Phase2St 215 Covered T1,T3,T4
Phase2St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt 229 Covered T25,T18,T49
Phase2St->Phase3St 233 Covered T1,T3,T4
Phase3St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt 245 Covered T17,T26,T18
Phase3St->TerminalSt 249 Covered T1,T3,T4
TerminalSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt 261 Covered T1,T3,T10
TimeoutSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt 181 Covered T1,T2,T16
TimeoutSt->Phase0St 172 Covered T19,T73,T70



Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Line No.TotalCoveredPercent
Branches 26 26 100.00
CASE 144 22 22 100.00
IF 283 2 2 100.00
IF 305 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 case (state_q) -2-: 151 if (((accu_trig_i && en_i) && (!clr_i))) -3-: 157 if (((timeout_en_i && (!cnt_ge)) && en_i)) -4-: 171 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i))) -5-: 178 if (timeout_en_i) -6-: 193 if (clr_i) -7-: 197 if (cnt_ge) -8-: 210 if (clr_i) -9-: 214 if (cnt_ge) -10-: 228 if (clr_i) -11-: 232 if (cnt_ge) -12-: 244 if (clr_i) -13-: 248 if (cnt_ge) -14-: 260 if (clr_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
IdleSt 1 - - - - - - - - - - - - Covered T1,T3,T4
IdleSt 0 1 - - - - - - - - - - - Covered T1,T2,T16
IdleSt 0 0 - - - - - - - - - - - Covered T1,T2,T3
TimeoutSt - - 1 - - - - - - - - - - Covered T19,T73,T70
TimeoutSt - - 0 1 - - - - - - - - - Covered T1,T2,T16
TimeoutSt - - 0 0 - - - - - - - - - Covered T1,T2,T16
Phase0St - - - - 1 - - - - - - - - Covered T17,T45,T93
Phase0St - - - - 0 1 - - - - - - - Covered T1,T3,T4
Phase0St - - - - 0 0 - - - - - - - Covered T1,T3,T4
Phase1St - - - - - - 1 - - - - - - Covered T1,T17,T94
Phase1St - - - - - - 0 1 - - - - - Covered T1,T3,T4
Phase1St - - - - - - 0 0 - - - - - Covered T1,T3,T4
Phase2St - - - - - - - - 1 - - - - Covered T25,T18,T49
Phase2St - - - - - - - - 0 1 - - - Covered T1,T3,T4
Phase2St - - - - - - - - 0 0 - - - Covered T1,T3,T4
Phase3St - - - - - - - - - - 1 - - Covered T17,T26,T18
Phase3St - - - - - - - - - - 0 1 - Covered T1,T3,T4
Phase3St - - - - - - - - - - 0 0 - Covered T1,T3,T4
TerminalSt - - - - - - - - - - - - 1 Covered T1,T3,T10
TerminalSt - - - - - - - - - - - - 0 Covered T1,T3,T4
FsmErrorSt - - - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - - - Covered T11,T12,T13


LineNo. Expression -1-: 283 if ((accu_fail_i || cnt_error))

Branches:
-1-StatusTests
1 Covered T11,T12,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 305 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccuFailToFsmError_A 662190782 334 0 0
CheckAccumTrig0_A 662190782 900 0 0
CheckAccumTrig1_A 662190782 44 0 0
CheckClr_A 662190782 482 0 0
CheckEn_A 661822219 231044858 0 0
CheckPhase0_A 662190782 993 0 0
CheckPhase1_A 662190782 976 0 0
CheckPhase2_A 662190782 949 0 0
CheckPhase3_A 662190782 919 0 0
CheckTimeout0_A 662190782 2004 0 0
CheckTimeoutSt1_A 662190782 185468 0 0
CheckTimeoutSt2_A 662190782 1897 0 0
CheckTimeoutStTrig_A 662190782 61 0 0
ErrorStAllEscAsserted_A 662190782 1587 0 0
ErrorStIsTerminal_A 662190782 1317 0 0
EscStateOut_A 661820635 661752236 0 0
u_state_regs_A 662190782 662008565 0 0


AccuFailToFsmError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 334 0 0
T11 30127 59 0 0
T12 0 71 0 0
T13 0 91 0 0
T27 0 58 0 0
T28 0 55 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

CheckAccumTrig0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 900 0 0
T1 136449 9 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 1 0 0
T7 2106 1 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 20 0 0
T38 0 1 0 0

CheckAccumTrig1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 44 0 0
T18 419825 0 0 0
T19 37355 1 0 0
T20 72258 0 0 0
T24 80502 0 0 0
T26 46163 0 0 0
T39 110386 0 0 0
T40 383283 0 0 0
T42 0 2 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 4 0 0
T46 0 2 0 0
T49 0 2 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T59 9533 0 0 0
T60 794660 0 0 0
T61 870798 0 0 0

CheckClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 482 0 0
T1 136449 8 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 1 0 0
T17 0 13 0 0
T18 0 13 0 0
T19 0 1 0 0
T25 0 1 0 0
T26 0 1 0 0
T69 0 1 0 0
T70 0 1 0 0

CheckEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661822219 231044858 0 0
T1 136449 597 0 0
T2 8507 649 0 0
T3 369097 6545 0 0
T4 112945 8129 0 0
T5 35420 2324 0 0
T6 254401 2782 0 0
T7 2106 633 0 0
T8 18709 11880 0 0
T9 766985 3357 0 0
T10 39205 2098 0 0

CheckPhase0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 993 0 0
T1 136449 9 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 1 0 0
T7 2106 1 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 19 0 0
T38 0 1 0 0

CheckPhase1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 976 0 0
T1 136449 8 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 1 0 0
T7 2106 1 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 16 0 0
T38 0 1 0 0

CheckPhase2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 949 0 0
T1 136449 8 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 1 0 0
T7 2106 1 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 16 0 0
T38 0 1 0 0

CheckPhase3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 919 0 0
T1 136449 8 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 1 0 0
T7 2106 1 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 15 0 0
T38 0 1 0 0

CheckTimeout0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 2004 0 0
T1 136449 1 0 0
T2 8507 1 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 0 0 0
T16 0 10 0 0
T17 0 130 0 0
T18 0 3 0 0
T19 0 1 0 0
T26 0 2 0 0
T59 0 1 0 0
T70 0 4 0 0
T73 0 3 0 0

CheckTimeoutSt1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 185468 0 0
T1 136449 17 0 0
T2 8507 60 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 0 0 0
T16 0 1986 0 0
T17 0 7906 0 0
T18 0 261 0 0
T19 0 1 0 0
T26 0 299 0 0
T59 0 141 0 0
T70 0 323 0 0
T73 0 665 0 0

CheckTimeoutSt2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1897 0 0
T1 136449 1 0 0
T2 8507 1 0 0
T3 369097 0 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 0 0 0
T16 0 10 0 0
T17 0 130 0 0
T18 0 3 0 0
T26 0 2 0 0
T42 0 1 0 0
T59 0 1 0 0
T70 0 3 0 0
T73 0 1 0 0

CheckTimeoutStTrig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 61 0 0
T34 0 1 0 0
T37 0 1 0 0
T43 0 1 0 0
T49 0 2 0 0
T64 0 1 0 0
T70 124032 1 0 0
T71 285429 0 0 0
T73 641331 2 0 0
T74 51648 0 0 0
T75 0 1 0 0
T76 0 2 0 0
T79 0 2 0 0
T80 344216 0 0 0
T81 270698 0 0 0
T82 3221 0 0 0
T83 28408 0 0 0
T84 28615 0 0 0
T85 23940 0 0 0

ErrorStAllEscAsserted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1587 0 0
T11 30127 183 0 0
T12 0 326 0 0
T13 0 357 0 0
T27 0 381 0 0
T28 0 340 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

ErrorStIsTerminal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1317 0 0
T11 30127 153 0 0
T12 0 266 0 0
T13 0 297 0 0
T27 0 321 0 0
T28 0 280 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

EscStateOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661820635 661752236 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 662008565 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Line No.TotalCoveredPercent
TOTAL101101100.00
CONT_ASSIGN8511100.00
ALWAYS1348989100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
ALWAYS30533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
169 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
178 1 1
179 1 1
181 1 1
182 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
MISSING_ELSE
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
268 1 1
269 1 1
283 1 1
284 1 1
285 1 1
MISSING_ELSE
292 4 4
295 4 4
305 3 3


Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
TotalCoveredPercent
Conditions454395.56
Logical454395.56
Non-Logical00
Event00

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----
-1--2-StatusTests
01CoveredT11,T12,T13
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T3,T4
101Excluded VC_COV_UNR
110CoveredT15
111CoveredT1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-
-1--2--3-StatusTests
011CoveredT1,T4,T8
101CoveredT10,T22,T17
110CoveredT4,T5,T16
111CoveredT16,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T18,T20
10CoveredT42,T47,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT16,T17,T18
101Excluded VC_COV_UNR
110Not Covered
111CoveredT42,T47,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10Not Covered
11CoveredT16,T18,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T8
1CoveredT4,T5,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT17,T24,T73

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT10,T16,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T10
1CoveredT1,T3,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT16,T17,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T8,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT1,T3,T5

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 14 14 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
FsmErrorSt 284 Covered T11,T12,T13
IdleSt 181 Covered T1,T2,T3
Phase0St 152 Covered T1,T3,T4
Phase1St 198 Covered T1,T3,T4
Phase2St 215 Covered T1,T3,T4
Phase3St 233 Covered T1,T3,T4
TerminalSt 249 Covered T1,T3,T4
TimeoutSt 159 Covered T16,T17,T18


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->FsmErrorSt 284 Covered T11,T12,T13
IdleSt->Phase0St 152 Covered T1,T3,T4
IdleSt->TimeoutSt 159 Covered T16,T17,T18
Phase0St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt 194 Covered T17,T23,T95
Phase0St->Phase1St 198 Covered T1,T3,T4
Phase1St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt 211 Covered T18,T96,T97
Phase1St->Phase2St 215 Covered T1,T3,T4
Phase2St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt 229 Covered T17,T98,T86
Phase2St->Phase3St 233 Covered T1,T3,T4
Phase3St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt 245 Covered T96,T99,T100
Phase3St->TerminalSt 249 Covered T1,T3,T4
TerminalSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt 261 Covered T5,T10,T17
TimeoutSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt 181 Covered T16,T17,T18
TimeoutSt->Phase0St 172 Covered T16,T18,T20



Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Line No.TotalCoveredPercent
Branches 26 26 100.00
CASE 144 22 22 100.00
IF 283 2 2 100.00
IF 305 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 case (state_q) -2-: 151 if (((accu_trig_i && en_i) && (!clr_i))) -3-: 157 if (((timeout_en_i && (!cnt_ge)) && en_i)) -4-: 171 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i))) -5-: 178 if (timeout_en_i) -6-: 193 if (clr_i) -7-: 197 if (cnt_ge) -8-: 210 if (clr_i) -9-: 214 if (cnt_ge) -10-: 228 if (clr_i) -11-: 232 if (cnt_ge) -12-: 244 if (clr_i) -13-: 248 if (cnt_ge) -14-: 260 if (clr_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
IdleSt 1 - - - - - - - - - - - - Covered T1,T3,T4
IdleSt 0 1 - - - - - - - - - - - Covered T16,T17,T18
IdleSt 0 0 - - - - - - - - - - - Covered T1,T2,T3
TimeoutSt - - 1 - - - - - - - - - - Covered T16,T18,T20
TimeoutSt - - 0 1 - - - - - - - - - Covered T16,T17,T18
TimeoutSt - - 0 0 - - - - - - - - - Covered T16,T17,T18
Phase0St - - - - 1 - - - - - - - - Covered T17,T23,T101
Phase0St - - - - 0 1 - - - - - - - Covered T1,T3,T4
Phase0St - - - - 0 0 - - - - - - - Covered T1,T3,T4
Phase1St - - - - - - 1 - - - - - - Covered T18,T96,T97
Phase1St - - - - - - 0 1 - - - - - Covered T1,T3,T4
Phase1St - - - - - - 0 0 - - - - - Covered T1,T3,T4
Phase2St - - - - - - - - 1 - - - - Covered T17,T98,T86
Phase2St - - - - - - - - 0 1 - - - Covered T1,T3,T4
Phase2St - - - - - - - - 0 0 - - - Covered T1,T3,T4
Phase3St - - - - - - - - - - 1 - - Covered T96,T99,T100
Phase3St - - - - - - - - - - 0 1 - Covered T1,T3,T4
Phase3St - - - - - - - - - - 0 0 - Covered T1,T3,T4
TerminalSt - - - - - - - - - - - - 1 Covered T5,T10,T17
TerminalSt - - - - - - - - - - - - 0 Covered T1,T3,T4
FsmErrorSt - - - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - - - Covered T11,T12,T13


LineNo. Expression -1-: 283 if ((accu_fail_i || cnt_error))

Branches:
-1-StatusTests
1 Covered T11,T12,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 305 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccuFailToFsmError_A 662190782 332 0 0
CheckAccumTrig0_A 662190782 516 0 0
CheckAccumTrig1_A 662190782 22 0 0
CheckClr_A 662190782 245 0 0
CheckEn_A 661822219 306092502 0 0
CheckPhase0_A 662190782 591 0 0
CheckPhase1_A 662190782 580 0 0
CheckPhase2_A 662190782 571 0 0
CheckPhase3_A 662190782 561 0 0
CheckTimeout0_A 662190782 1064 0 0
CheckTimeoutSt1_A 662190782 125431 0 0
CheckTimeoutSt2_A 662190782 979 0 0
CheckTimeoutStTrig_A 662190782 62 0 0
ErrorStAllEscAsserted_A 662190782 1630 0 0
ErrorStIsTerminal_A 662190782 1360 0 0
EscStateOut_A 661820635 661752236 0 0
u_state_regs_A 662190782 662008565 0 0


AccuFailToFsmError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 332 0 0
T11 30127 33 0 0
T12 0 77 0 0
T13 0 83 0 0
T27 0 61 0 0
T28 0 78 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

CheckAccumTrig0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 516 0 0
T1 136449 1 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T17 0 19 0 0
T22 0 1 0 0
T24 0 1 0 0
T25 0 1 0 0

CheckAccumTrig1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 22 0 0
T21 0 1 0 0
T42 307675 1 0 0
T43 947336 0 0 0
T44 11289 0 0 0
T47 0 1 0 0
T48 0 1 0 0
T53 0 1 0 0
T54 0 1 0 0
T55 0 1 0 0
T56 0 1 0 0
T57 0 1 0 0
T58 0 2 0 0
T62 6727 0 0 0
T63 334099 0 0 0
T64 29110 0 0 0
T65 94950 0 0 0
T66 108145 0 0 0
T67 30540 0 0 0
T68 30941 0 0 0

CheckClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 245 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 1 0 0
T16 126942 0 0 0
T17 353940 13 0 0
T18 0 2 0 0
T22 58722 0 0 0
T38 35101 0 0 0
T42 0 6 0 0
T43 0 2 0 0
T44 0 1 0 0
T63 0 2 0 0
T70 0 1 0 0
T71 0 1 0 0

CheckEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661822219 306092502 0 0
T1 136449 601 0 0
T2 8507 8427 0 0
T3 369097 6561 0 0
T4 112945 13689 0 0
T5 35420 31434 0 0
T6 254401 254395 0 0
T7 2106 637 0 0
T8 18709 589 0 0
T9 766985 3371 0 0
T10 39205 11095 0 0

CheckPhase0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 591 0 0
T1 136449 1 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T16 0 1 0 0
T17 0 18 0 0
T22 0 1 0 0
T25 0 1 0 0

CheckPhase1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 580 0 0
T1 136449 1 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T16 0 1 0 0
T17 0 18 0 0
T22 0 1 0 0
T25 0 1 0 0

CheckPhase2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 571 0 0
T1 136449 1 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T16 0 1 0 0
T17 0 16 0 0
T22 0 1 0 0
T25 0 1 0 0

CheckPhase3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 561 0 0
T1 136449 1 0 0
T2 8507 0 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 1 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 2 0 0
T16 0 1 0 0
T17 0 16 0 0
T22 0 1 0 0
T25 0 1 0 0

CheckTimeout0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1064 0 0
T16 126942 3 0 0
T17 353940 171 0 0
T18 0 8 0 0
T19 37355 0 0 0
T20 0 1 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 20 0 0
T59 9533 0 0 0
T62 0 1 0 0
T63 0 2 0 0
T69 6028 0 0 0
T70 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0

CheckTimeoutSt1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 125431 0 0
T16 126942 552 0 0
T17 353940 10420 0 0
T18 0 1171 0 0
T19 37355 0 0 0
T20 0 140 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 4332 0 0
T59 9533 0 0 0
T62 0 387 0 0
T63 0 203 0 0
T69 6028 0 0 0
T70 0 91 0 0
T73 0 39 0 0
T74 0 98 0 0

CheckTimeoutSt2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 979 0 0
T16 126942 2 0 0
T17 353940 171 0 0
T18 0 7 0 0
T19 37355 0 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 17 0 0
T43 0 71 0 0
T59 9533 0 0 0
T63 0 2 0 0
T64 0 2 0 0
T69 6028 0 0 0
T70 0 1 0 0
T73 0 1 0 0
T74 0 1 0 0

CheckTimeoutStTrig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 62 0 0
T16 126942 1 0 0
T17 353940 0 0 0
T18 0 1 0 0
T19 37355 0 0 0
T20 0 1 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T42 0 2 0 0
T49 0 2 0 0
T59 9533 0 0 0
T62 0 1 0 0
T66 0 1 0 0
T68 0 1 0 0
T69 6028 0 0 0
T77 0 1 0 0
T78 0 2 0 0

ErrorStAllEscAsserted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1630 0 0
T11 30127 171 0 0
T12 0 390 0 0
T13 0 365 0 0
T27 0 362 0 0
T28 0 342 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

ErrorStIsTerminal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1360 0 0
T11 30127 141 0 0
T12 0 330 0 0
T13 0 305 0 0
T27 0 302 0 0
T28 0 282 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

EscStateOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661820635 661752236 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 662008565 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Line No.TotalCoveredPercent
TOTAL101101100.00
CONT_ASSIGN8511100.00
ALWAYS1348989100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
ALWAYS30533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
169 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
178 1 1
179 1 1
181 1 1
182 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
MISSING_ELSE
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
268 1 1
269 1 1
283 1 1
284 1 1
285 1 1
MISSING_ELSE
292 4 4
295 4 4
305 3 3


Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
TotalCoveredPercent
Conditions454395.56
Logical454395.56
Non-Logical00
Event00

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----
-1--2-StatusTests
01CoveredT11,T12,T13
10CoveredT3,T4,T6
11CoveredT1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--
-1--2-StatusTests
01CoveredT3,T4,T6
10CoveredT1,T2,T3
11CoveredT3,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT3,T4,T6
101Excluded VC_COV_UNR
110CoveredT14
111CoveredT3,T4,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-
-1--2--3-StatusTests
011CoveredT4,T8,T10
101CoveredT3,T10,T22
110CoveredT1,T4,T5
111CoveredT10,T16,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------
-1--2-StatusTests
00CoveredT10,T16,T17
01CoveredT17,T18,T74
10CoveredT10,T20,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----
-1--2--3-StatusTestsExclude Annotation
011CoveredT10,T16,T17
101Excluded VC_COV_UNR
110Not Covered
111CoveredT10,T20,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----
-1--2-StatusTests
01CoveredT10,T16,T17
10Not Covered
11CoveredT17,T18,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------
-1-StatusTests
0CoveredT3,T6,T8
1CoveredT4,T17,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------
-1-StatusTests
0CoveredT3,T8,T10
1CoveredT6,T22,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------
-1-StatusTests
0CoveredT6,T10,T22
1CoveredT3,T8,T10

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------
-1-StatusTests
0CoveredT3,T6,T8
1CoveredT10,T39,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT6,T8,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT8,T22,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT3,T10,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT3,T4,T6

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 14 14 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
FsmErrorSt 284 Covered T11,T12,T13
IdleSt 181 Covered T1,T2,T3
Phase0St 152 Covered T3,T4,T6
Phase1St 198 Covered T3,T6,T8
Phase2St 215 Covered T3,T6,T8
Phase3St 233 Covered T3,T6,T8
TerminalSt 249 Covered T3,T6,T8
TimeoutSt 159 Covered T10,T16,T17


transitionsLine No.CoveredTestsExclude Annotation
IdleSt->FsmErrorSt 284 Covered T11,T12,T13
IdleSt->Phase0St 152 Covered T3,T4,T6
IdleSt->TimeoutSt 159 Covered T10,T16,T17
Phase0St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt 194 Covered T4,T102,T103
Phase0St->Phase1St 198 Covered T3,T6,T8
Phase1St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt 211 Covered T24,T70,T72
Phase1St->Phase2St 215 Covered T3,T6,T8
Phase2St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt 229 Covered T49,T104,T105
Phase2St->Phase3St 233 Covered T3,T6,T8
Phase3St->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt 245 Covered T70,T92,T106
Phase3St->TerminalSt 249 Covered T3,T6,T8
TerminalSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt 261 Covered T10,T17,T18
TimeoutSt->FsmErrorSt 284 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt 181 Covered T10,T16,T17
TimeoutSt->Phase0St 172 Covered T10,T17,T18



Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Line No.TotalCoveredPercent
Branches 26 26 100.00
CASE 144 22 22 100.00
IF 283 2 2 100.00
IF 305 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 case (state_q) -2-: 151 if (((accu_trig_i && en_i) && (!clr_i))) -3-: 157 if (((timeout_en_i && (!cnt_ge)) && en_i)) -4-: 171 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i))) -5-: 178 if (timeout_en_i) -6-: 193 if (clr_i) -7-: 197 if (cnt_ge) -8-: 210 if (clr_i) -9-: 214 if (cnt_ge) -10-: 228 if (clr_i) -11-: 232 if (cnt_ge) -12-: 244 if (clr_i) -13-: 248 if (cnt_ge) -14-: 260 if (clr_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
IdleSt 1 - - - - - - - - - - - - Covered T3,T4,T6
IdleSt 0 1 - - - - - - - - - - - Covered T10,T16,T17
IdleSt 0 0 - - - - - - - - - - - Covered T1,T2,T3
TimeoutSt - - 1 - - - - - - - - - - Covered T10,T17,T18
TimeoutSt - - 0 1 - - - - - - - - - Covered T10,T16,T17
TimeoutSt - - 0 0 - - - - - - - - - Covered T10,T16,T17
Phase0St - - - - 1 - - - - - - - - Covered T4,T103,T89
Phase0St - - - - 0 1 - - - - - - - Covered T3,T6,T8
Phase0St - - - - 0 0 - - - - - - - Covered T3,T4,T6
Phase1St - - - - - - 1 - - - - - - Covered T24,T70,T72
Phase1St - - - - - - 0 1 - - - - - Covered T3,T6,T8
Phase1St - - - - - - 0 0 - - - - - Covered T3,T6,T8
Phase2St - - - - - - - - 1 - - - - Covered T49,T104,T105
Phase2St - - - - - - - - 0 1 - - - Covered T3,T6,T8
Phase2St - - - - - - - - 0 0 - - - Covered T3,T6,T8
Phase3St - - - - - - - - - - 1 - - Covered T70,T92,T106
Phase3St - - - - - - - - - - 0 1 - Covered T3,T6,T8
Phase3St - - - - - - - - - - 0 0 - Covered T3,T6,T8
TerminalSt - - - - - - - - - - - - 1 Covered T10,T17,T18
TerminalSt - - - - - - - - - - - - 0 Covered T3,T6,T8
FsmErrorSt - - - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - - - Covered T11,T12,T13


LineNo. Expression -1-: 283 if ((accu_fail_i || cnt_error))

Branches:
-1-StatusTests
1 Covered T11,T12,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 305 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AccuFailToFsmError_A 662190782 239 0 0
CheckAccumTrig0_A 662190782 518 0 0
CheckAccumTrig1_A 662190782 22 0 0
CheckClr_A 662190782 220 0 0
CheckEn_A 661822219 265782666 0 0
CheckPhase0_A 662190782 585 0 0
CheckPhase1_A 662190782 573 0 0
CheckPhase2_A 662190782 565 0 0
CheckPhase3_A 662190782 557 0 0
CheckTimeout0_A 662190782 1802 0 0
CheckTimeoutSt1_A 662190782 168042 0 0
CheckTimeoutSt2_A 662190782 1722 0 0
CheckTimeoutStTrig_A 662190782 58 0 0
ErrorStAllEscAsserted_A 662190782 1654 0 0
ErrorStIsTerminal_A 662190782 1384 0 0
EscStateOut_A 661820635 661752236 0 0
u_state_regs_A 662190782 662008565 0 0


AccuFailToFsmError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 239 0 0
T11 30127 42 0 0
T12 0 44 0 0
T13 0 72 0 0
T27 0 49 0 0
T28 0 32 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

CheckAccumTrig0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 518 0 0
T3 369097 1 0 0
T4 112945 1 0 0
T5 35420 0 0 0
T6 254401 1 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 4 0 0
T16 126942 0 0 0
T17 0 2 0 0
T18 0 4 0 0
T22 58722 1 0 0
T24 0 1 0 0
T39 0 1 0 0

CheckAccumTrig1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 22 0 0
T10 39205 1 0 0
T16 126942 0 0 0
T17 353940 0 0 0
T19 37355 0 0 0
T20 0 1 0 0
T21 0 1 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T38 35101 0 0 0
T42 0 1 0 0
T59 9533 0 0 0
T69 6028 0 0 0
T90 0 1 0 0
T92 0 1 0 0
T102 0 2 0 0
T107 0 1 0 0
T108 0 1 0 0
T109 0 1 0 0

CheckClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 220 0 0
T4 112945 1 0 0
T5 35420 0 0 0
T6 254401 0 0 0
T7 2106 0 0 0
T8 18709 0 0 0
T9 766985 0 0 0
T10 39205 4 0 0
T16 126942 0 0 0
T17 353940 1 0 0
T18 0 1 0 0
T22 58722 0 0 0
T24 0 1 0 0
T42 0 1 0 0
T62 0 2 0 0
T70 0 4 0 0
T71 0 1 0 0
T72 0 3 0 0

CheckEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661822219 265782666 0 0
T1 136449 136441 0 0
T2 8507 8427 0 0
T3 369097 15111 0 0
T4 112945 107316 0 0
T5 35420 35346 0 0
T6 254401 2812 0 0
T7 2106 641 0 0
T8 18709 593 0 0
T9 766985 766920 0 0
T10 39205 5876 0 0

CheckPhase0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 585 0 0
T3 369097 1 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 1 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 5 0 0
T16 126942 0 0 0
T17 0 3 0 0
T18 0 6 0 0
T22 58722 1 0 0
T24 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0

CheckPhase1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 573 0 0
T3 369097 1 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 1 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 5 0 0
T16 126942 0 0 0
T17 0 3 0 0
T18 0 6 0 0
T20 0 1 0 0
T22 58722 1 0 0
T39 0 1 0 0
T40 0 1 0 0

CheckPhase2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 565 0 0
T3 369097 1 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 1 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 5 0 0
T16 126942 0 0 0
T17 0 3 0 0
T18 0 6 0 0
T20 0 1 0 0
T22 58722 1 0 0
T39 0 1 0 0
T40 0 1 0 0

CheckPhase3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 557 0 0
T3 369097 1 0 0
T4 112945 0 0 0
T5 35420 0 0 0
T6 254401 1 0 0
T7 2106 0 0 0
T8 18709 1 0 0
T9 766985 0 0 0
T10 39205 5 0 0
T16 126942 0 0 0
T17 0 3 0 0
T18 0 6 0 0
T20 0 1 0 0
T22 58722 1 0 0
T39 0 1 0 0
T40 0 1 0 0

CheckTimeout0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1802 0 0
T10 39205 2 0 0
T16 126942 4 0 0
T17 353940 2 0 0
T18 0 7 0 0
T19 37355 0 0 0
T20 0 1 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T38 35101 0 0 0
T42 0 11 0 0
T43 0 2 0 0
T59 9533 0 0 0
T64 0 2 0 0
T69 6028 0 0 0
T70 0 5 0 0
T74 0 1 0 0

CheckTimeoutSt1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 168042 0 0
T10 39205 58 0 0
T16 126942 772 0 0
T17 353940 355 0 0
T18 0 929 0 0
T19 37355 0 0 0
T20 0 2 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T38 35101 0 0 0
T42 0 2095 0 0
T43 0 176 0 0
T59 9533 0 0 0
T64 0 378 0 0
T69 6028 0 0 0
T70 0 633 0 0
T74 0 91 0 0

CheckTimeoutSt2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1722 0 0
T10 39205 1 0 0
T16 126942 4 0 0
T17 353940 1 0 0
T18 0 5 0 0
T19 37355 0 0 0
T22 58722 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T38 35101 0 0 0
T42 0 10 0 0
T43 0 1 0 0
T59 9533 0 0 0
T64 0 2 0 0
T66 0 1 0 0
T67 0 2 0 0
T69 6028 0 0 0
T70 0 3 0 0

CheckTimeoutStTrig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 58 0 0
T17 353940 1 0 0
T18 0 2 0 0
T19 37355 0 0 0
T24 80502 0 0 0
T25 202105 0 0 0
T26 46163 0 0 0
T38 35101 0 0 0
T39 110386 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T59 9533 0 0 0
T60 794660 0 0 0
T68 0 2 0 0
T69 6028 0 0 0
T70 0 2 0 0
T74 0 1 0 0
T98 0 1 0 0
T110 0 1 0 0
T111 0 1 0 0

ErrorStAllEscAsserted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1654 0 0
T11 30127 192 0 0
T12 0 372 0 0
T13 0 354 0 0
T27 0 349 0 0
T28 0 387 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

ErrorStIsTerminal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 1384 0 0
T11 30127 162 0 0
T12 0 312 0 0
T13 0 294 0 0
T27 0 289 0 0
T28 0 327 0 0
T29 4294 0 0 0
T30 946 0 0 0
T31 222617 0 0 0
T32 123723 0 0 0
T33 28333 0 0 0
T34 31679 0 0 0
T35 29026 0 0 0
T36 297102 0 0 0
T37 403477 0 0 0

EscStateOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 661820635 661752236 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 662190782 662008565 0 0
T1 136449 136441 0 0
T2 8507 8428 0 0
T3 369097 369090 0 0
T4 112945 112871 0 0
T5 35420 35347 0 0
T6 254401 254395 0 0
T7 2106 2047 0 0
T8 18709 18622 0 0
T9 766985 766921 0 0
T10 39205 39136 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%