Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60716401	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29405375

1

T1

2012

T2

138436

T3

2626

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13633270	1			T1	849		T2	56051		T3	1044
values[0x0]	37405352	1			T1	2589		T2	190320		T3	3385
values[0x1]	39083154	1			T1	2639		T2	189405		T3	3485

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51985269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38136507

1

T1

2495

T2

174953

T3

3329

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	313392	1			T2	1755		T3	30		T7	21
valid_sources[0x01]	637312	1			T2	1681		T3	27		T7	18
valid_sources[0x02]	301294	1			T2	1709		T3	20		T7	40
valid_sources[0x03]	299326	1			T2	1731		T3	32		T7	16
valid_sources[0x04]	310263	1			T2	1807		T3	38		T7	11
valid_sources[0x05]	300709	1			T2	1759		T3	21		T7	38
valid_sources[0x06]	294912	1			T2	1703		T3	40		T7	17
valid_sources[0x07]	483234	1			T2	1724		T3	23		T7	13
valid_sources[0x08]	296544	1			T2	1726		T3	35		T7	15
valid_sources[0x09]	309143	1			T2	1771		T3	21		T7	12
valid_sources[0x0a]	756334	1			T2	1694		T3	30		T7	8
valid_sources[0x0b]	293153	1			T2	1721		T3	33		T7	9
valid_sources[0x0c]	293542	1			T2	1648		T3	36		T7	7
valid_sources[0x0d]	295960	1			T2	1692		T3	30		T7	33
valid_sources[0x0e]	315874	1			T2	1700		T3	27		T7	10
valid_sources[0x0f]	290555	1			T2	1682		T3	25		T7	18
valid_sources[0x10]	287451	1			T2	1641		T3	36		T7	6
valid_sources[0x11]	293396	1			T2	1635		T3	17		T7	27
valid_sources[0x12]	289935	1			T2	1737		T3	37		T7	25
valid_sources[0x13]	300815	1			T2	1662		T3	28		T7	5
valid_sources[0x14]	689619	1			T2	1719		T3	29		T7	36
valid_sources[0x15]	538692	1			T2	1722		T3	42		T7	39
valid_sources[0x16]	289661	1			T2	1707		T3	32		T7	18
valid_sources[0x17]	294743	1			T2	1788		T3	43		T7	36
valid_sources[0x18]	287532	1			T2	1660		T3	36		T7	10
valid_sources[0x19]	709509	1			T2	1733		T3	32		T7	24
valid_sources[0x1a]	292385	1			T2	1761		T3	39		T7	8
valid_sources[0x1b]	682042	1			T2	1693		T3	27		T7	22
valid_sources[0x1c]	292794	1			T2	1665		T3	21		T7	18
valid_sources[0x1d]	291268	1			T2	1736		T3	37		T7	30
valid_sources[0x1e]	293408	1			T2	1693		T3	26		T7	3
valid_sources[0x1f]	304690	1			T2	1644		T3	31		T7	14
valid_sources[0x20]	291275	1			T2	1718		T3	26		T7	37
valid_sources[0x21]	506062	1			T2	1734		T3	31		T7	26
valid_sources[0x22]	298360	1			T2	1698		T3	21		T7	30
valid_sources[0x23]	291238	1			T2	1660		T3	29		T7	24
valid_sources[0x24]	290180	1			T2	1662		T3	20		T7	5
valid_sources[0x25]	660714	1			T2	1758		T3	30		T7	23
valid_sources[0x26]	287365	1			T2	1701		T3	34		T7	13
valid_sources[0x27]	303958	1			T2	1718		T3	33		T7	14
valid_sources[0x28]	294526	1			T2	1712		T3	29		T7	9
valid_sources[0x29]	459897	1			T2	1665		T3	28		T7	32
valid_sources[0x2a]	292898	1			T2	1769		T3	32		T7	28
valid_sources[0x2b]	297422	1			T2	1709		T3	25		T7	13
valid_sources[0x2c]	303883	1			T2	1690		T3	31		T7	33
valid_sources[0x2d]	293184	1			T2	1756		T3	21		T7	25
valid_sources[0x2e]	294156	1			T2	1788		T3	30		T7	6
valid_sources[0x2f]	308945	1			T2	1766		T3	22		T7	11
valid_sources[0x30]	291566	1			T2	1692		T3	30		T7	11
valid_sources[0x31]	289084	1			T2	1665		T3	28		T7	29
valid_sources[0x32]	293174	1			T2	1699		T3	42		T7	9
valid_sources[0x33]	296631	1			T2	1703		T3	31		T7	11
valid_sources[0x34]	290802	1			T2	1707		T3	33		T7	11
valid_sources[0x35]	303397	1			T2	1696		T3	29		T7	8
valid_sources[0x36]	687294	1			T2	1639		T3	32		T7	16
valid_sources[0x37]	305397	1			T2	1695		T3	26		T7	17
valid_sources[0x38]	296392	1			T2	1637		T3	25		T7	31
valid_sources[0x39]	304691	1			T2	1662		T3	22		T7	7
valid_sources[0x3a]	793629	1			T2	1742		T3	24		T7	23
valid_sources[0x3b]	292753	1			T2	1748		T3	24		T7	4
valid_sources[0x3c]	298622	1			T2	1713		T3	36		T7	43
valid_sources[0x3d]	300369	1			T2	1648		T3	25		T7	2
valid_sources[0x3e]	299948	1			T2	1711		T3	34		T7	33
valid_sources[0x3f]	298668	1			T2	1678		T3	51		T7	29
valid_sources[0x40]	288910	1			T2	1735		T3	22		T7	18
valid_sources[0x41]	292548	1			T2	1767		T3	41		T7	32
valid_sources[0x42]	301874	1			T2	1757		T3	32		T7	14
valid_sources[0x43]	291804	1			T2	1724		T3	36		T7	9
valid_sources[0x44]	301883	1			T2	1657		T3	42		T7	4
valid_sources[0x45]	295666	1			T2	1708		T3	26		T7	13
valid_sources[0x46]	295311	1			T2	1727		T3	34		T7	11
valid_sources[0x47]	286694	1			T2	1690		T3	26		T7	15
valid_sources[0x48]	624436	1			T2	1697		T3	29		T7	10
valid_sources[0x49]	297401	1			T2	1658		T3	42		T7	15
valid_sources[0x4a]	295003	1			T2	1675		T3	31		T7	13
valid_sources[0x4b]	293549	1			T2	1640		T3	35		T7	14
valid_sources[0x4c]	618670	1			T2	1683		T3	28		T7	20
valid_sources[0x4d]	288832	1			T2	1794		T3	23		T7	12
valid_sources[0x4e]	302479	1			T2	1680		T3	27		T7	2
valid_sources[0x4f]	299781	1			T2	1715		T3	33		T7	26
valid_sources[0x50]	323434	1			T2	1719		T3	31		T7	12
valid_sources[0x51]	295167	1			T2	1661		T3	35		T7	28
valid_sources[0x52]	300271	1			T1	6077		T2	1744		T3	31
valid_sources[0x53]	294031	1			T2	1720		T3	32		T7	14
valid_sources[0x54]	1178859	1			T2	1734		T3	29		T7	3
valid_sources[0x55]	294755	1			T2	1661		T3	33		T7	20
valid_sources[0x56]	300524	1			T2	1755		T3	27		T7	43
valid_sources[0x57]	289020	1			T2	1727		T3	26		T7	9
valid_sources[0x58]	290366	1			T2	1716		T3	34		T7	13
valid_sources[0x59]	288578	1			T2	1641		T3	27		T7	30
valid_sources[0x5a]	296771	1			T2	1751		T3	41		T7	23
valid_sources[0x5b]	615040	1			T2	1741		T3	32		T7	34
valid_sources[0x5c]	296137	1			T2	1643		T3	29		T7	24
valid_sources[0x5d]	314826	1			T2	1727		T3	19		T7	17
valid_sources[0x5e]	291423	1			T2	1712		T3	24		T7	20
valid_sources[0x5f]	290028	1			T2	1633		T3	33		T7	23
valid_sources[0x60]	299286	1			T2	1716		T3	31		T7	24
valid_sources[0x61]	523539	1			T2	1720		T3	30		T7	27
valid_sources[0x62]	298188	1			T2	1659		T3	28		T7	14
valid_sources[0x63]	306897	1			T2	1659		T3	25		T7	13
valid_sources[0x64]	297716	1			T2	1787		T3	19		T7	4
valid_sources[0x65]	293934	1			T2	1787		T3	30		T7	11
valid_sources[0x66]	775744	1			T2	1705		T3	45		T7	19
valid_sources[0x67]	288470	1			T2	1750		T3	32		T7	16
valid_sources[0x68]	308982	1			T2	1744		T3	23		T7	18
valid_sources[0x69]	292690	1			T2	1699		T3	31		T7	9
valid_sources[0x6a]	295331	1			T2	1742		T3	35		T7	31
valid_sources[0x6b]	296424	1			T2	1581		T3	35		T7	16
valid_sources[0x6c]	303659	1			T2	1667		T3	34		T7	41
valid_sources[0x6d]	295841	1			T2	1720		T3	28		T7	8
valid_sources[0x6e]	295326	1			T2	1735		T3	26		T7	25
valid_sources[0x6f]	296103	1			T2	1646		T3	43		T7	38
valid_sources[0x70]	292377	1			T2	1742		T3	33		T7	22
valid_sources[0x71]	321941	1			T2	1599		T3	20		T7	9
valid_sources[0x72]	296575	1			T2	1738		T3	35		T7	23
valid_sources[0x73]	295624	1			T2	1696		T3	31		T7	22
valid_sources[0x74]	292279	1			T2	1692		T3	43		T7	22
valid_sources[0x75]	299227	1			T2	1647		T3	27		T7	28
valid_sources[0x76]	296214	1			T2	1628		T3	35		T7	4
valid_sources[0x77]	738590	1			T2	1676		T3	40		T7	23
valid_sources[0x78]	302299	1			T2	1684		T3	38		T7	33
valid_sources[0x79]	294569	1			T2	1635		T3	30		T7	30
valid_sources[0x7a]	291837	1			T2	1738		T3	31		T7	17
valid_sources[0x7b]	503941	1			T2	1718		T3	31		T7	14
valid_sources[0x7c]	291766	1			T2	1782		T3	39		T7	20
valid_sources[0x7d]	293733	1			T2	1756		T3	37		T7	25
valid_sources[0x7e]	296592	1			T2	1716		T3	23		T7	26
valid_sources[0x7f]	335745	1			T2	1721		T3	30		T7	27
valid_sources[0x80]	295702	1			T2	1767		T3	33		T7	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6791915

1

T1

407

T2

27960

T3

511

values[0x0]

all_enables

biggest_size

14289854

1

T1

997

T2

70860

T3

1360

values[0x1]

all_enables

biggest_size

8323606

1

T1

608

T2

39616

T3

755