Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T202,T203
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11266	0	0
DisabledNoTrigBkwd_A	2147483647	740809	0	0
DisabledNoTrigFwd_A	2147483647	1311407591	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11266	0	0
T9	127731	0	0	0
T10	347620	0	0	0
T13	20967	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T19	105451	0	0	0
T35	1721	540	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0
T82	597062	0	0	0
T92	138715	0	0	0
T199	0	388	0	0
T202	0	749	0	0
T203	0	461	0	0
T204	0	375	0	0
T205	3829	480	0	0
T206	4308	924	0	0
T207	0	813	0	0
T208	0	377	0	0
T209	0	601	0	0
T210	0	449	0	0
T211	0	518	0	0
T212	0	480	0	0
T213	0	610	0	0
T214	0	100	0	0
T215	0	574	0	0
T216	0	491	0	0
T217	0	744	0	0
T218	0	1053	0	0
T219	0	539	0	0
T220	509439	0	0	0
T221	113973	0	0	0
T222	368774	0	0	0
T223	143656	0	0	0
T224	201633	0	0	0
T225	112654	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	740809	0	0
T1	25356	2	0	0
T2	602452	5511	0	0
T3	247136	87	0	0
T4	781432	707	0	0
T5	1180420	1433	0	0
T6	1416296	1361	0	0
T7	172836	17	0	0
T8	0	82	0	0
T9	0	1	0	0
T15	0	2268	0	0
T18	0	27	0	0
T20	229252	18	0	0
T21	81080	16	0	0
T22	56608	26	0	0
T23	150171	9	0	0
T24	0	17	0	0
T30	0	857	0	0
T35	0	3	0	0
T40	0	2478	0	0
T41	0	819	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311407591	0	0
T1	101424	99704	0	0
T2	602452	184667	0	0
T3	247136	111523	0	0
T4	781432	589184	0	0
T5	1180420	1514517	0	0
T6	1416296	1322618	0	0
T7	172836	160132	0	0
T20	229252	90946	0	0
T21	81080	45278	0	0
T22	56608	15811	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T207,T208
1	1	Covered	T2,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	617447457	2250	0	0
DisabledNoTrigBkwd_A	617447457	189283	0	0
DisabledNoTrigFwd_A	617447457	320326875	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	2250	0	0
T13	20967	0	0	0
T82	597062	0	0	0
T92	138715	0	0	0
T205	3829	480	0	0
T207	0	813	0	0
T208	0	377	0	0
T212	0	480	0	0
T214	0	100	0	0
T220	509439	0	0	0
T221	113973	0	0	0
T222	368774	0	0	0
T223	143656	0	0	0
T224	201633	0	0	0
T225	112654	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	189283	0	0
T2	150613	1702	0	0
T3	61784	50	0	0
T4	195358	0	0	0
T5	295105	327	0	0
T6	354074	735	0	0
T7	43209	17	0	0
T8	0	16	0	0
T20	57313	12	0	0
T21	20270	0	0	0
T22	14152	26	0	0
T23	50057	9	0	0
T24	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	320326875	0	0
T1	25356	25269	0	0
T2	150613	12416	0	0
T3	61784	6051	0	0
T4	195358	195353	0	0
T5	295105	231321	0	0
T6	354074	209441	0	0
T7	43209	30703	0	0
T20	57313	3148	0	0
T21	20270	20217	0	0
T22	14152	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T203,T199
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	617447457	3056	0	0
DisabledNoTrigBkwd_A	617447457	177890	0	0
DisabledNoTrigFwd_A	617447457	329538956	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	3056	0	0
T9	127731	0	0	0
T10	347620	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T19	105451	0	0	0
T35	1721	540	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0
T199	0	388	0	0
T203	0	461	0	0
T211	0	518	0	0
T213	0	610	0	0
T219	0	539	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	177890	0	0
T2	150613	625	0	0
T3	61784	22	0	0
T4	195358	707	0	0
T5	295105	82	0	0
T6	354074	186	0	0
T7	43209	0	0	0
T8	0	32	0	0
T15	0	1006	0	0
T20	57313	6	0	0
T21	20270	14	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	329538956	0	0
T1	25356	25269	0	0
T2	150613	148903	0	0
T3	61784	2105	0	0
T4	195358	3844	0	0
T5	295105	266738	0	0
T6	354074	160652	0	0
T7	43209	43143	0	0
T20	57313	3163	0	0
T21	20270	4254	0	0
T22	14152	586	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T210,T215
1	1	Covered	T1,T2,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	617447457	3491	0	0
DisabledNoTrigBkwd_A	617447457	176548	0	0
DisabledNoTrigFwd_A	617447457	330616997	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	3491	0	0
T55	238569	0	0	0
T95	16947	0	0	0
T206	4308	924	0	0
T210	0	449	0	0
T215	0	574	0	0
T216	0	491	0	0
T218	0	1053	0	0
T226	43518	0	0	0
T227	289151	0	0	0
T228	284489	0	0	0
T229	131326	0	0	0
T230	159283	0	0	0
T231	446644	0	0	0
T232	305263	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	176548	0	0
T1	25356	2	0	0
T2	150613	1604	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	51	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T9	0	1	0	0
T15	0	80	0	0
T18	0	27	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	8	0	0
T30	0	17	0	0
T41	0	819	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	330616997	0	0
T1	25356	23897	0	0
T2	150613	11728	0	0
T3	61784	61726	0	0
T4	195358	194915	0	0
T5	295105	287270	0	0
T6	354074	349142	0	0
T7	43209	43143	0	0
T20	57313	48776	0	0
T21	20270	4258	0	0
T22	14152	590	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T204,T209
1	1	Covered	T2,T3,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	617447457	2469	0	0
DisabledNoTrigBkwd_A	617447457	197088	0	0
DisabledNoTrigFwd_A	617447457	330924763	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	2469	0	0
T11	501785	0	0	0
T29	831586	0	0	0
T42	882054	0	0	0
T61	28453	0	0	0
T62	15967	0	0	0
T63	131681	0	0	0
T65	223793	0	0	0
T202	4348	749	0	0
T204	0	375	0	0
T209	0	601	0	0
T217	0	744	0	0
T233	84184	0	0	0
T234	132847	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	197088	0	0
T2	150613	1580	0	0
T3	61784	15	0	0
T4	195358	0	0	0
T5	295105	973	0	0
T6	354074	440	0	0
T7	43209	0	0	0
T8	0	34	0	0
T15	0	1182	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	7	0	0
T30	0	840	0	0
T40	0	2478	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	330924763	0	0
T1	25356	25269	0	0
T2	150613	11620	0	0
T3	61784	41641	0	0
T4	195358	195072	0	0
T5	295105	729188	0	0
T6	354074	603383	0	0
T7	43209	43143	0	0
T20	57313	35859	0	0
T21	20270	16549	0	0
T22	14152	14053	0	0