Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T15
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T20,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T5
0	1	Covered	T2,T8,T18
1	0	Covered	T20,T8,T15

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T20,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T20,T8,T15

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T26
1	1	Covered	T2,T8,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T20,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T20,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T15,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T29,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T22,T30,T31
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T5,T22,T29
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T3,T7
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T20,T5
TimeoutSt->Phase0St	172	Covered	T2,T20,T8

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T28,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T29,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T22,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T22,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	809	0	0
CheckAccumTrig0_A	2147483647	2312	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1116	0	0
CheckEn_A	2147483647	989738918	0	0
CheckPhase0_A	2147483647	2621	0	0
CheckPhase1_A	2147483647	2567	0	0
CheckPhase2_A	2147483647	2502	0	0
CheckPhase3_A	2147483647	2464	0	0
CheckTimeout0_A	2147483647	3596	0	0
CheckTimeoutSt1_A	2147483647	349077	0	0
CheckTimeoutSt2_A	2147483647	3233	0	0
CheckTimeoutStTrig_A	2147483647	240	0	0
ErrorStAllEscAsserted_A	2147483647	4193	0	0
ErrorStIsTerminal_A	2147483647	3473	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	809	0	0
T9	510924	0	0	0
T12	180712	258	0	0
T13	0	118	0	0
T14	0	150	0	0
T16	48556	0	0	0
T17	51520	0	0	0
T18	2051464	0	0	0
T33	0	132	0	0
T34	0	151	0	0
T35	6884	0	0	0
T36	988916	0	0	0
T37	15868	0	0	0
T38	326532	0	0	0
T39	46868	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2312	0	0
T1	25356	1	0	0
T2	602452	11	0	0
T3	247136	12	0	0
T4	781432	1	0	0
T5	1180420	32	0	0
T6	1416296	9	0	0
T7	172836	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T15	0	14	0	0
T18	0	1	0	0
T20	229252	4	0	0
T21	81080	3	0	0
T22	56608	4	0	0
T23	150171	1	0	0
T24	0	3	0	0
T30	0	4	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T8	173120	1	0	0
T12	45178	0	0	0
T15	882108	5	0	0
T16	12139	0	0	0
T18	0	2	0	0
T20	57313	1	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	0	0	0
T25	58610	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	3	0	0
T42	882054	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	121878	0	0	0
T57	41337	0	0	0
T58	84766	0	0	0
T59	8943	0	0	0
T60	72797	0	0	0
T61	28453	0	0	0
T62	15967	0	0	0
T63	131681	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1116	0	0
T2	602452	5	0	0
T3	247136	9	0	0
T4	781432	0	0	0
T5	1180420	21	0	0
T6	1416296	0	0	0
T7	172836	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T15	0	13	0	0
T18	0	3	0	0
T20	229252	3	0	0
T21	81080	1	0	0
T22	56608	3	0	0
T23	200228	0	0	0
T27	0	6	0	0
T28	0	5	0	0
T29	0	8	0	0
T30	0	2	0	0
T42	0	15	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	11	0	0
T66	0	6	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	989738918	0	0
T1	101424	76402	0	0
T2	602452	36676	0	0
T3	247136	75967	0	0
T4	781432	585947	0	0
T5	1180420	1899022	0	0
T6	1416296	1765959	0	0
T7	172836	137132	0	0
T20	229252	90945	0	0
T21	81080	45276	0	0
T22	56608	15810	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2621	0	0
T1	25356	1	0	0
T2	602452	12	0	0
T3	247136	12	0	0
T4	781432	1	0	0
T5	1180420	32	0	0
T6	1416296	10	0	0
T7	172836	2	0	0
T8	0	4	0	0
T9	0	1	0	0
T15	0	15	0	0
T18	0	1	0	0
T20	229252	6	0	0
T21	81080	3	0	0
T22	56608	4	0	0
T23	150171	1	0	0
T24	0	3	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2567	0	0
T1	25356	1	0	0
T2	602452	12	0	0
T3	247136	12	0	0
T4	781432	1	0	0
T5	1180420	31	0	0
T6	1416296	10	0	0
T7	172836	2	0	0
T8	0	4	0	0
T9	0	1	0	0
T15	0	15	0	0
T18	0	1	0	0
T20	229252	6	0	0
T21	81080	3	0	0
T22	56608	4	0	0
T23	150171	1	0	0
T24	0	3	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T1	25356	1	0	0
T2	602452	12	0	0
T3	247136	12	0	0
T4	781432	1	0	0
T5	1180420	31	0	0
T6	1416296	10	0	0
T7	172836	2	0	0
T8	0	4	0	0
T9	0	1	0	0
T15	0	15	0	0
T18	0	1	0	0
T20	229252	6	0	0
T21	81080	3	0	0
T22	56608	3	0	0
T23	150171	1	0	0
T24	0	3	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2464	0	0
T1	25356	1	0	0
T2	602452	12	0	0
T3	247136	12	0	0
T4	781432	1	0	0
T5	1180420	30	0	0
T6	1416296	10	0	0
T7	172836	2	0	0
T8	0	4	0	0
T9	0	1	0	0
T15	0	15	0	0
T18	0	1	0	0
T20	229252	6	0	0
T21	81080	3	0	0
T22	56608	2	0	0
T23	150171	1	0	0
T24	0	3	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3596	0	0
T2	451839	4	0	0
T3	185352	0	0	0
T4	586074	0	0	0
T5	1180420	3	0	0
T6	1416296	1	0	0
T7	129627	0	0	0
T8	86560	5	0	0
T15	0	88	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	229252	6	0	0
T21	81080	2	0	0
T22	56608	0	0	0
T23	200228	0	0	0
T24	42883	18	0	0
T25	29305	1	0	0
T27	0	10	0	0
T28	0	40	0	0
T30	0	1	0	0
T31	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	30	0	0
T56	60939	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349077	0	0
T2	451839	903	0	0
T3	185352	0	0	0
T4	586074	0	0	0
T5	1180420	367	0	0
T6	1416296	400	0	0
T7	129627	0	0	0
T8	86560	600	0	0
T15	882108	9329	0	0
T18	0	117	0	0
T19	0	12	0	0
T20	171939	610	0	0
T21	81080	122	0	0
T22	56608	0	0	0
T23	200228	0	0	0
T24	42883	1346	0	0
T25	29305	115	0	0
T27	0	950	0	0
T28	0	5769	0	0
T30	0	21	0	0
T31	0	74	0	0
T37	0	133	0	0
T40	0	142	0	0
T42	0	9098	0	0
T56	60939	0	0	0
T59	0	226	0	0
T61	0	216	0	0
T68	0	57	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3233	0	0
T2	301226	3	0	0
T3	123568	0	0	0
T4	390716	0	0	0
T5	1180420	3	0	0
T6	1416296	0	0	0
T7	86418	0	0	0
T8	173120	3	0	0
T15	882108	82	0	0
T19	0	1	0	0
T20	171939	4	0	0
T21	81080	2	0	0
T22	56608	0	0	0
T23	200228	0	0	0
T24	85766	18	0	0
T25	58610	1	0	0
T27	0	2	0	0
T28	0	41	0	0
T31	0	3	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	39	0	0
T56	121878	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T66	0	1	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	240	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	86560	1	0	0
T10	347620	0	0	0
T18	512866	1	0	0
T19	105451	0	0	0
T20	57313	0	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T27	996321	6	0	0
T28	0	1	0	0
T30	905330	0	0	0
T32	0	3	0	0
T40	468972	0	0	0
T41	137279	0	0	0
T42	0	5	0	0
T45	0	3	0	0
T48	0	2	0	0
T51	0	4	0	0
T61	0	1	0	0
T64	186991	0	0	0
T68	15541	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	314592	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4193	0	0
T9	510924	0	0	0
T12	180712	1350	0	0
T13	0	695	0	0
T14	0	711	0	0
T16	48556	0	0	0
T17	51520	0	0	0
T18	2051464	0	0	0
T33	0	700	0	0
T34	0	737	0	0
T35	6884	0	0	0
T36	988916	0	0	0
T37	15868	0	0	0
T38	326532	0	0	0
T39	46868	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3473	0	0
T9	510924	0	0	0
T12	180712	1110	0	0
T13	0	575	0	0
T14	0	591	0	0
T16	48556	0	0	0
T17	51520	0	0	0
T18	2051464	0	0	0
T33	0	580	0	0
T34	0	617	0	0
T35	6884	0	0	0
T36	988916	0	0	0
T37	15868	0	0	0
T38	326532	0	0	0
T39	46868	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	101076	0	0
T2	602452	602372	0	0
T3	247136	246904	0	0
T4	781432	781412	0	0
T5	1180420	1180156	0	0
T6	1416296	1416256	0	0
T7	172836	172572	0	0
T20	229252	229000	0	0
T21	81080	80868	0	0
T22	56608	56212	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	101076	0	0
T2	602452	602372	0	0
T3	247136	246904	0	0
T4	781432	781412	0	0
T5	1180420	1180156	0	0
T6	1416296	1416256	0	0
T7	172836	172572	0	0
T20	229252	229000	0	0
T21	81080	80868	0	0
T22	56608	56212	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T20
1	0	1	Covered	T5,T6,T35
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T2,T20,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T5
0	1	Covered	T2,T27,T42
1	0	Covered	T8,T18,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T20,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T18,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Not Covered
1	1	Covered	T2,T27,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T5,T6,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T2,T20,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T2,T20,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T51,T81,T82
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T83,T84
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T85,T86,T82
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T47,T49
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T20,T5,T24
TimeoutSt->Phase0St	172	Covered	T2,T8,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T8,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T82,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T83,T84
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T85,T86,T82
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T47,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	617447457	206	0	0
CheckAccumTrig0_A	617447457	560	0	0
CheckAccumTrig1_A	617447457	24	0	0
CheckClr_A	617447457	290	0	0
CheckEn_A	617321313	247940431	0	0
CheckPhase0_A	617447457	622	0	0
CheckPhase1_A	617447457	603	0	0
CheckPhase2_A	617447457	592	0	0
CheckPhase3_A	617447457	580	0	0
CheckTimeout0_A	617447457	1040	0	0
CheckTimeoutSt1_A	617447457	95213	0	0
CheckTimeoutSt2_A	617447457	959	0	0
CheckTimeoutStTrig_A	617447457	56	0	0
ErrorStAllEscAsserted_A	617447457	1055	0	0
ErrorStIsTerminal_A	617447457	875	0	0
EscStateOut_A	617320191	617252920	0	0
u_state_regs_A	617447457	617303461	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	206	0	0
T9	127731	0	0	0
T12	45178	63	0	0
T13	0	39	0	0
T14	0	41	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	27	0	0
T34	0	36	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	560	0	0
T2	150613	3	0	0
T3	61784	10	0	0
T4	195358	1	0	0
T5	295105	5	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T9	0	1	0	0
T15	0	5	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	24	0	0
T8	86560	1	0	0
T12	45178	0	0	0
T15	882108	0	0	0
T16	12139	0	0	0
T18	0	1	0	0
T25	29305	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	60939	0	0	0
T57	41337	0	0	0
T58	84766	0	0	0
T59	8943	0	0	0
T60	72797	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	290	0	0
T2	150613	2	0	0
T3	61784	9	0	0
T4	195358	0	0	0
T5	295105	2	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T15	0	2	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	8	0	0
T42	0	3	0	0
T65	0	9	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617321313	247940431	0	0
T1	25356	25268	0	0
T2	150613	8491	0	0
T3	61784	2105	0	0
T4	195358	608	0	0
T5	295105	262692	0	0
T6	354074	618143	0	0
T7	43209	43142	0	0
T20	57313	3163	0	0
T21	20270	4254	0	0
T22	14152	586	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	622	0	0
T2	150613	4	0	0
T3	61784	10	0	0
T4	195358	1	0	0
T5	295105	5	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	5	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	603	0	0
T2	150613	4	0	0
T3	61784	10	0	0
T4	195358	1	0	0
T5	295105	5	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	5	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	592	0	0
T2	150613	4	0	0
T3	61784	10	0	0
T4	195358	1	0	0
T5	295105	5	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	5	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	580	0	0
T2	150613	4	0	0
T3	61784	10	0	0
T4	195358	1	0	0
T5	295105	5	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	5	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1040	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	2	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	13	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	57313	2	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	8	0	0
T27	0	1	0	0
T59	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	95213	0	0
T2	150613	241	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	236	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	14	0	0
T15	0	1624	0	0
T19	0	12	0	0
T20	57313	308	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	582	0	0
T27	0	165	0	0
T42	0	3318	0	0
T59	0	114	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	959	0	0
T5	295105	2	0	0
T6	354074	0	0	0
T8	86560	0	0	0
T15	0	13	0	0
T19	0	1	0	0
T20	57313	2	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	8	0	0
T25	29305	0	0	0
T28	0	2	0	0
T42	0	13	0	0
T56	60939	0	0	0
T59	0	1	0	0
T67	0	4	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	56	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T20	57313	0	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T27	0	1	0	0
T32	0	2	0	0
T42	0	3	0	0
T45	0	1	0	0
T51	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1055	0	0
T9	127731	0	0	0
T12	45178	324	0	0
T13	0	175	0	0
T14	0	192	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	171	0	0
T34	0	193	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	875	0	0
T9	127731	0	0	0
T12	45178	264	0	0
T13	0	145	0	0
T14	0	162	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	141	0	0
T34	0	163	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617320191	617252920	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	617303461	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T20
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T20

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T20
1	0	1	Covered	T5,T6,T10
1	1	0	Covered	T2,T3,T20
1	1	1	Covered	T2,T20,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T8,T27,T28
1	0	Covered	T42,T47,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T20,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T47,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T21
1	0	Not Covered
1	1	Covered	T8,T27,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T5,T15,T41

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T5,T8,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T5,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T5,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T5
Phase1St	198	Covered	T1,T2,T5
Phase2St	215	Covered	T1,T2,T5
Phase3St	233	Covered	T1,T2,T5
TerminalSt	249	Covered	T1,T2,T5
TimeoutSt	159	Covered	T2,T20,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T5
IdleSt->TimeoutSt	159	Covered	T2,T20,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T88,T89,T90
Phase0St->Phase1St	198	Covered	T1,T2,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T66,T88,T91
Phase1St->Phase2St	215	Covered	T1,T2,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T66,T92,T93
Phase2St->Phase3St	233	Covered	T1,T2,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T42,T88,T93
Phase3St->TerminalSt	249	Covered	T1,T2,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T5,T8
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T20,T21
TimeoutSt->Phase0St	172	Covered	T8,T27,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T27,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T90,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T66,T88,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T66,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T88,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	617447457	183	0	0
CheckAccumTrig0_A	617447457	456	0	0
CheckAccumTrig1_A	617447457	21	0	0
CheckClr_A	617447457	204	0	0
CheckEn_A	617321313	248336263	0	0
CheckPhase0_A	617447457	533	0	0
CheckPhase1_A	617447457	521	0	0
CheckPhase2_A	617447457	510	0	0
CheckPhase3_A	617447457	503	0	0
CheckTimeout0_A	617447457	693	0	0
CheckTimeoutSt1_A	617447457	73840	0	0
CheckTimeoutSt2_A	617447457	605	0	0
CheckTimeoutStTrig_A	617447457	65	0	0
ErrorStAllEscAsserted_A	617447457	1019	0	0
ErrorStIsTerminal_A	617447457	839	0	0
EscStateOut_A	617320191	617252920	0	0
u_state_regs_A	617447457	617303461	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	183	0	0
T9	127731	0	0	0
T12	45178	52	0	0
T13	0	27	0	0
T14	0	35	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	25	0	0
T34	0	44	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	456	0	0
T1	25356	1	0	0
T2	150613	3	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	9	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	1	0	0
T30	0	2	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	21	0	0
T28	239500	0	0	0
T42	882054	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T61	28453	0	0	0
T62	15967	0	0	0
T63	131681	0	0	0
T66	755676	0	0	0
T67	628881	0	0	0
T69	11122	0	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	715671	0	0	0
T100	848428	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	204	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	6	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T20	57313	0	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T27	0	4	0	0
T28	0	1	0	0
T42	0	5	0	0
T65	0	2	0	0
T66	0	5	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617321313	248336263	0	0
T1	25356	598	0	0
T2	150613	11728	0	0
T3	61784	61725	0	0
T4	195358	194914	0	0
T5	295105	675827	0	0
T6	354074	349141	0	0
T7	43209	43142	0	0
T20	57313	48775	0	0
T21	20270	4258	0	0
T22	14152	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	533	0	0
T1	25356	1	0	0
T2	150613	3	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	9	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	521	0	0
T1	25356	1	0	0
T2	150613	3	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	9	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	510	0	0
T1	25356	1	0	0
T2	150613	3	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	9	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	503	0	0
T1	25356	1	0	0
T2	150613	3	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	9	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T24	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	693	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	4	0	0
T20	57313	1	0	0
T21	20270	2	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T25	0	1	0	0
T27	0	5	0	0
T31	0	1	0	0
T42	0	17	0	0
T61	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	73840	0	0
T2	150613	132	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T8	0	63	0	0
T15	0	405	0	0
T20	57313	128	0	0
T21	20270	122	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T25	0	115	0	0
T27	0	5	0	0
T31	0	74	0	0
T42	0	3353	0	0
T61	0	164	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	605	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T15	0	4	0	0
T20	57313	1	0	0
T21	20270	2	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T25	0	1	0	0
T31	0	1	0	0
T42	0	16	0	0
T61	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	65	0	0
T8	86560	1	0	0
T12	45178	0	0	0
T15	882108	0	0	0
T16	12139	0	0	0
T25	29305	0	0	0
T27	0	5	0	0
T28	0	1	0	0
T48	0	2	0	0
T51	0	2	0	0
T56	60939	0	0	0
T57	41337	0	0	0
T58	84766	0	0	0
T59	8943	0	0	0
T60	72797	0	0	0
T71	0	1	0	0
T78	0	1	0	0
T94	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1019	0	0
T9	127731	0	0	0
T12	45178	353	0	0
T13	0	167	0	0
T14	0	158	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	154	0	0
T34	0	187	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	839	0	0
T9	127731	0	0	0
T12	45178	293	0	0
T13	0	137	0	0
T14	0	128	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	124	0	0
T34	0	157	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617320191	617252920	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	617303461	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T20
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T20
1	0	1	Covered	T5,T6,T15
1	1	0	Covered	T1,T2,T20
1	1	1	Covered	T2,T20,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T6
0	1	Covered	T20,T6,T15
1	0	Covered	T42,T103,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T20,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T103,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T6
1	0	Not Covered
1	1	Covered	T20,T6,T15

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T2,T15,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T2,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T3,T6,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T20,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T6,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T20,T6,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T20
Phase1St	198	Covered	T2,T3,T20
Phase2St	215	Covered	T2,T3,T20
Phase3St	233	Covered	T2,T3,T20
TerminalSt	249	Covered	T2,T3,T20
TimeoutSt	159	Covered	T2,T20,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T2,T20,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T104
Phase0St->Phase1St	198	Covered	T2,T3,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T47,T85,T87
Phase1St->Phase2St	215	Covered	T2,T3,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T105,T106,T107
Phase2St->Phase3St	233	Covered	T2,T3,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T108,T82
Phase3St->TerminalSt	249	Covered	T2,T3,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T20,T24
TimeoutSt->Phase0St	172	Covered	T20,T6,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T6,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T20,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T20,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T47,T85,T87
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T105,T106,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T20,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T108,T82
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	617447457	216	0	0
CheckAccumTrig0_A	617447457	483	0	0
CheckAccumTrig1_A	617447457	18	0	0
CheckClr_A	617447457	204	0	0
CheckEn_A	617321313	265306610	0	0
CheckPhase0_A	617447457	551	0	0
CheckPhase1_A	617447457	545	0	0
CheckPhase2_A	617447457	535	0	0
CheckPhase3_A	617447457	529	0	0
CheckTimeout0_A	617447457	822	0	0
CheckTimeoutSt1_A	617447457	78614	0	0
CheckTimeoutSt2_A	617447457	751	0	0
CheckTimeoutStTrig_A	617447457	52	0	0
ErrorStAllEscAsserted_A	617447457	1111	0	0
ErrorStIsTerminal_A	617447457	931	0	0
EscStateOut_A	617320191	617252920	0	0
u_state_regs_A	617447457	617303461	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	216	0	0
T9	127731	0	0	0
T12	45178	71	0	0
T13	0	31	0	0
T14	0	33	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	34	0	0
T34	0	47	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	483	0	0
T2	150613	3	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	4	0	0
T6	354074	2	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	6	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	1	0	0
T30	0	2	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	18	0	0
T28	239500	0	0	0
T42	882054	1	0	0
T48	0	1	0	0
T61	28453	0	0	0
T62	15967	0	0	0
T63	131681	0	0	0
T66	755676	0	0	0
T67	628881	0	0	0
T69	11122	0	0	0
T85	0	1	0	0
T97	0	1	0	0
T99	715671	0	0	0
T100	848428	0	0	0
T103	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	204	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	3	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T15	0	3	0	0
T20	57313	0	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T42	0	7	0	0
T66	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617321313	265306610	0	0
T1	25356	25268	0	0
T2	150613	10281	0	0
T3	61784	6086	0	0
T4	195358	195072	0	0
T5	295105	729182	0	0
T6	354074	589236	0	0
T7	43209	43142	0	0
T20	57313	35859	0	0
T21	20270	16548	0	0
T22	14152	14052	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	551	0	0
T2	150613	3	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	4	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	7	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	545	0	0
T2	150613	3	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	4	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	7	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	535	0	0
T2	150613	3	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	4	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	7	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	529	0	0
T2	150613	3	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	4	0	0
T6	354074	3	0	0
T7	43209	0	0	0
T8	0	1	0	0
T15	0	7	0	0
T20	57313	1	0	0
T21	20270	1	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	822	0	0
T2	150613	2	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	1	0	0
T7	43209	0	0	0
T15	0	5	0	0
T20	57313	2	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	6	0	0
T27	0	4	0	0
T28	0	40	0	0
T40	0	1	0	0
T42	0	13	0	0
T61	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	78614	0	0
T2	150613	530	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	400	0	0
T7	43209	0	0	0
T15	0	432	0	0
T20	57313	174	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	490	0	0
T27	0	705	0	0
T28	0	5769	0	0
T40	0	142	0	0
T42	0	2427	0	0
T61	0	52	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	751	0	0
T2	150613	2	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T7	43209	0	0	0
T15	0	4	0	0
T20	57313	1	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	0	6	0	0
T27	0	2	0	0
T28	0	39	0	0
T40	0	1	0	0
T42	0	9	0	0
T70	0	1	0	0
T116	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	52	0	0
T5	295105	0	0	0
T6	354074	1	0	0
T8	86560	0	0	0
T15	0	1	0	0
T20	57313	1	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	0	0	0
T25	29305	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T32	0	1	0	0
T42	0	3	0	0
T56	60939	0	0	0
T61	0	1	0	0
T71	0	1	0	0
T117	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1111	0	0
T9	127731	0	0	0
T12	45178	349	0	0
T13	0	192	0	0
T14	0	188	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	198	0	0
T34	0	184	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	931	0	0
T9	127731	0	0	0
T12	45178	289	0	0
T13	0	162	0	0
T14	0	158	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	168	0	0
T34	0	154	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617320191	617252920	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	617303461	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T5,T6,T36
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T20,T5,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T24,T8
0	1	Covered	T18,T42,T61
1	0	Covered	T20,T15,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T24,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T15,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T26
1	1	Covered	T18,T42,T61

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T7,T20,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T20
1	Covered	T2,T3,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T5,T6,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T7,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T7,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T20,T5,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T20,T5,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T27,T28
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T28,T47
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T22,T30,T31
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T22,T118
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T7,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T24,T8
TimeoutSt->Phase0St	172	Covered	T20,T15,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T15,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T24,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T24,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T28,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T28,T47
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T22,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T22,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T7,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	617447457	204	0	0
CheckAccumTrig0_A	617447457	813	0	0
CheckAccumTrig1_A	617447457	55	0	0
CheckClr_A	617447457	418	0	0
CheckEn_A	617321313	228155614	0	0
CheckPhase0_A	617447457	915	0	0
CheckPhase1_A	617447457	898	0	0
CheckPhase2_A	617447457	865	0	0
CheckPhase3_A	617447457	852	0	0
CheckTimeout0_A	617447457	1041	0	0
CheckTimeoutSt1_A	617447457	101410	0	0
CheckTimeoutSt2_A	617447457	918	0	0
CheckTimeoutStTrig_A	617447457	67	0	0
ErrorStAllEscAsserted_A	617447457	1008	0	0
ErrorStIsTerminal_A	617447457	828	0	0
EscStateOut_A	617320191	617252920	0	0
u_state_regs_A	617447457	617303461	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	204	0	0
T9	127731	0	0	0
T12	45178	72	0	0
T13	0	21	0	0
T14	0	41	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	46	0	0
T34	0	24	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	813	0	0
T2	150613	2	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	14	0	0
T6	354074	4	0	0
T7	43209	2	0	0
T8	0	1	0	0
T20	57313	3	0	0
T21	20270	0	0	0
T22	14152	4	0	0
T23	50057	1	0	0
T24	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	55	0	0
T5	295105	0	0	0
T6	354074	0	0	0
T8	86560	0	0	0
T15	0	5	0	0
T18	0	1	0	0
T20	57313	1	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	0	0	0
T25	29305	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T56	60939	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	418	0	0
T2	150613	1	0	0
T3	61784	0	0	0
T4	195358	0	0	0
T5	295105	10	0	0
T6	354074	0	0	0
T7	43209	1	0	0
T15	0	8	0	0
T18	0	2	0	0
T20	57313	3	0	0
T21	20270	0	0	0
T22	14152	3	0	0
T23	50057	0	0	0
T30	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617321313	228155614	0	0
T1	25356	25268	0	0
T2	150613	6176	0	0
T3	61784	6051	0	0
T4	195358	195353	0	0
T5	295105	231321	0	0
T6	354074	209439	0	0
T7	43209	7706	0	0
T20	57313	3148	0	0
T21	20270	20216	0	0
T22	14152	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	915	0	0
T2	150613	2	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	14	0	0
T6	354074	4	0	0
T7	43209	2	0	0
T8	0	1	0	0
T20	57313	4	0	0
T21	20270	0	0	0
T22	14152	4	0	0
T23	50057	1	0	0
T24	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	898	0	0
T2	150613	2	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	13	0	0
T6	354074	4	0	0
T7	43209	2	0	0
T8	0	1	0	0
T20	57313	4	0	0
T21	20270	0	0	0
T22	14152	4	0	0
T23	50057	1	0	0
T24	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	865	0	0
T2	150613	2	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	13	0	0
T6	354074	4	0	0
T7	43209	2	0	0
T8	0	1	0	0
T20	57313	4	0	0
T21	20270	0	0	0
T22	14152	3	0	0
T23	50057	1	0	0
T24	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	852	0	0
T2	150613	2	0	0
T3	61784	1	0	0
T4	195358	0	0	0
T5	295105	12	0	0
T6	354074	4	0	0
T7	43209	2	0	0
T8	0	1	0	0
T20	57313	4	0	0
T21	20270	0	0	0
T22	14152	2	0	0
T23	50057	1	0	0
T24	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1041	0	0
T5	295105	1	0	0
T6	354074	0	0	0
T8	86560	3	0	0
T15	0	66	0	0
T18	0	2	0	0
T20	57313	1	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	4	0	0
T25	29305	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T56	60939	0	0	0
T59	0	1	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	101410	0	0
T5	295105	131	0	0
T6	354074	0	0	0
T8	86560	523	0	0
T15	882108	6868	0	0
T18	0	117	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	274	0	0
T25	29305	0	0	0
T27	0	75	0	0
T30	0	21	0	0
T37	0	133	0	0
T56	60939	0	0	0
T59	0	112	0	0
T68	0	57	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	918	0	0
T5	295105	1	0	0
T6	354074	0	0	0
T8	86560	3	0	0
T15	882108	61	0	0
T21	20270	0	0	0
T22	14152	0	0	0
T23	50057	0	0	0
T24	42883	4	0	0
T25	29305	0	0	0
T31	0	2	0	0
T37	0	1	0	0
T42	0	1	0	0
T56	60939	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	67	0	0
T10	347620	0	0	0
T18	512866	1	0	0
T19	105451	0	0	0
T27	996321	0	0	0
T30	905330	0	0	0
T32	0	1	0	0
T40	468972	0	0	0
T41	137279	0	0	0
T42	0	2	0	0
T45	0	2	0	0
T61	0	1	0	0
T64	186991	0	0	0
T68	15541	0	0	0
T70	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T80	314592	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	1008	0	0
T9	127731	0	0	0
T12	45178	324	0	0
T13	0	161	0	0
T14	0	173	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	177	0	0
T34	0	173	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	828	0	0
T9	127731	0	0	0
T12	45178	264	0	0
T13	0	131	0	0
T14	0	143	0	0
T16	12139	0	0	0
T17	12880	0	0	0
T18	512866	0	0	0
T33	0	147	0	0
T34	0	143	0	0
T35	1721	0	0	0
T36	247229	0	0	0
T37	3967	0	0	0
T38	81633	0	0	0
T39	11717	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617320191	617252920	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617447457	617303461	0	0
T1	25356	25269	0	0
T2	150613	150593	0	0
T3	61784	61726	0	0
T4	195358	195353	0	0
T5	295105	295039	0	0
T6	354074	354064	0	0
T7	43209	43143	0	0
T20	57313	57250	0	0
T21	20270	20217	0	0
T22	14152	14053	0	0