Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T194,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12378	0	0
DisabledNoTrigBkwd_A	2147483647	785476	0	0
DisabledNoTrigFwd_A	2147483647	1351848086	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12378	0	0
T75	438790	0	0	0
T82	483492	0	0	0
T95	44182	0	0	0
T193	4287	1130	0	0
T194	1151	356	0	0
T195	1875	801	0	0
T196	3009	807	0	0
T197	3836	636	0	0
T198	0	345	0	0
T199	0	270	0	0
T200	0	647	0	0
T201	0	300	0	0
T202	0	287	0	0
T203	0	402	0	0
T204	0	474	0	0
T205	0	436	0	0
T206	0	870	0	0
T207	0	202	0	0
T208	0	705	0	0
T209	0	1224	0	0
T210	0	1168	0	0
T211	0	413	0	0
T212	0	905	0	0
T213	393575	0	0	0
T214	47731	0	0	0
T215	56337	0	0	0
T216	275643	0	0	0
T217	6889	0	0	0
T218	51894	0	0	0
T219	67252	0	0	0
T220	21669	0	0	0
T221	344898	0	0	0
T222	875903	0	0	0
T223	33594	0	0	0
T224	420254	0	0	0
T225	54881	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	785476	0	0
T1	315402	495	0	0
T2	43944	19	0	0
T3	62140	0	0	0
T4	282064	0	0	0
T5	35264	0	0	0
T6	594148	1163	0	0
T7	1209492	8421	0	0
T8	562012	15	0	0
T9	2342364	8724	0	0
T10	910236	88	0	0
T14	0	15465	0	0
T16	87034	23	0	0
T17	0	8	0	0
T18	0	224	0	0
T28	0	4336	0	0
T29	0	12178	0	0
T32	0	260	0	0
T33	0	532	0	0
T34	0	777	0	0
T35	0	4329	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1351848086	0	0
T1	420536	223047	0	0
T2	43944	22249	0	0
T3	62140	26864	0	0
T4	282064	237909	0	0
T5	35264	25746	0	0
T6	594148	149915	0	0
T7	1209492	339135	0	0
T8	562012	559305	0	0
T9	2342364	646878	0	0
T10	910236	262313	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T205,T209
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	649666724	2461	0	0
DisabledNoTrigBkwd_A	649666724	224285	0	0
DisabledNoTrigFwd_A	649666724	327382018	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	2461	0	0
T82	483492	0	0	0
T195	1875	801	0	0
T196	3009	0	0	0
T205	0	436	0	0
T209	0	1224	0	0
T219	67252	0	0	0
T220	21669	0	0	0
T221	344898	0	0	0
T222	875903	0	0	0
T223	33594	0	0	0
T224	420254	0	0	0
T225	54881	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	224285	0	0
T1	105134	10	0	0
T2	10986	9	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	5578	0	0
T8	140503	0	0	0
T9	585591	4	0	0
T10	227559	25	0	0
T14	0	8876	0	0
T17	0	8	0	0
T33	0	531	0	0
T34	0	776	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	327382018	0	0
T1	105134	9892	0	0
T2	10986	6648	0	0
T3	15535	12871	0	0
T4	70516	31335	0	0
T5	8816	5666	0	0
T6	148537	582	0	0
T7	302373	8869	0	0
T8	140503	131427	0	0
T9	585591	584908	0	0
T10	227559	11030	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T199,T200
1	1	Covered	T2,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	649666724	2249	0	0
DisabledNoTrigBkwd_A	649666724	160504	0	0
DisabledNoTrigFwd_A	649666724	352054918	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	2249	0	0
T75	438790	0	0	0
T95	44182	0	0	0
T193	4287	1130	0	0
T194	1151	0	0	0
T199	0	270	0	0
T200	0	647	0	0
T207	0	202	0	0
T213	393575	0	0	0
T214	47731	0	0	0
T215	56337	0	0	0
T216	275643	0	0	0
T217	6889	0	0	0
T218	51894	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	160504	0	0
T2	10986	10	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	312	0	0
T7	302373	2	0	0
T8	140503	1	0	0
T9	585591	2565	0	0
T10	227559	63	0	0
T14	0	2520	0	0
T16	87034	2	0	0
T28	0	3	0	0
T35	0	2406	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	352054918	0	0
T1	105134	105047	0	0
T2	10986	4106	0	0
T3	15535	1705	0	0
T4	70516	65692	0	0
T5	8816	5670	0	0
T6	148537	586	0	0
T7	302373	301662	0	0
T8	140503	107438	0	0
T9	585591	9968	0	0
T10	227559	2603	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T211,T212
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	649666724	1954	0	0
DisabledNoTrigBkwd_A	649666724	216535	0	0
DisabledNoTrigFwd_A	649666724	331293445	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1954	0	0
T45	130835	0	0	0
T161	305640	0	0	0
T197	3836	636	0	0
T211	0	413	0	0
T212	0	905	0	0
T226	629591	0	0	0
T227	511695	0	0	0
T228	21666	0	0	0
T229	149683	0	0	0
T230	209494	0	0	0
T231	26892	0	0	0
T232	27192	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	216535	0	0
T1	105134	483	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	850	0	0
T7	302373	1632	0	0
T8	140503	14	0	0
T9	585591	3109	0	0
T10	227559	0	0	0
T14	0	4060	0	0
T16	0	21	0	0
T29	0	2491	0	0
T32	0	74	0	0
T35	0	1923	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	331293445	0	0
T1	105134	98144	0	0
T2	10986	10901	0	0
T3	15535	590	0	0
T4	70516	70441	0	0
T5	8816	5684	0	0
T6	148537	590	0	0
T7	302373	8760	0	0
T8	140503	196283	0	0
T9	585591	29379	0	0
T10	227559	21215	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T196,T198
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	649666724	5714	0	0
DisabledNoTrigBkwd_A	649666724	184152	0	0
DisabledNoTrigFwd_A	649666724	341117705	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	5714	0	0
T70	9001	0	0	0
T75	438790	0	0	0
T194	1151	356	0	0
T196	0	807	0	0
T198	0	345	0	0
T201	0	300	0	0
T202	0	287	0	0
T203	0	402	0	0
T204	0	474	0	0
T206	0	870	0	0
T208	0	705	0	0
T210	0	1168	0	0
T216	275643	0	0	0
T217	6889	0	0	0
T218	51894	0	0	0
T233	185947	0	0	0
T234	8990	0	0	0
T235	116911	0	0	0
T236	103285	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	184152	0	0
T1	105134	2	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1209	0	0
T8	140503	0	0	0
T9	585591	3046	0	0
T10	227559	0	0	0
T14	0	9	0	0
T18	0	224	0	0
T28	0	4333	0	0
T29	0	9687	0	0
T32	0	186	0	0
T33	0	1	0	0
T34	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	341117705	0	0
T1	105134	9964	0	0
T2	10986	594	0	0
T3	15535	11698	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148157	0	0
T7	302373	19844	0	0
T8	140503	124157	0	0
T9	585591	22623	0	0
T10	227559	227465	0	0