Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T10,T14
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T7,T9

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T9

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T1,T3,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T6
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T7,T17,T18
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T19,T20
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T8,T17,T21
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T22,T20,T23
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T9,T16
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T5
TimeoutSt->Phase0St	172	Covered	T1,T3,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T17,T18
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T19,T20
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T17,T21
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T20,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1293	0	0
CheckAccumTrig0_A	2147483647	2245	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1103	0	0
CheckEn_A	2147483647	1039478318	0	0
CheckPhase0_A	2147483647	2559	0	0
CheckPhase1_A	2147483647	2523	0	0
CheckPhase2_A	2147483647	2463	0	0
CheckPhase3_A	2147483647	2415	0	0
CheckTimeout0_A	2147483647	6099	0	0
CheckTimeoutSt1_A	2147483647	610506	0	0
CheckTimeoutSt2_A	2147483647	5731	0	0
CheckTimeoutStTrig_A	2147483647	259	0	0
ErrorStAllEscAsserted_A	2147483647	6376	0	0
ErrorStIsTerminal_A	2147483647	5296	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293	0	0
T11	254084	264	0	0
T12	0	262	0	0
T13	0	165	0	0
T17	258772	0	0	0
T24	0	301	0	0
T25	0	301	0	0
T26	211644	0	0	0
T27	3914800	0	0	0
T28	481956	0	0	0
T29	1654120	0	0	0
T30	255456	0	0	0
T31	70648	0	0	0
T32	725444	0	0	0
T33	1294132	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T1	105134	1	0	0
T2	32958	2	0	0
T3	46605	0	0	0
T4	211548	0	0	0
T5	26448	0	0	0
T6	445611	3	0	0
T7	1209492	3	0	0
T8	562012	3	0	0
T9	2342364	4	0	0
T10	910236	2	0	0
T14	427819	9	0	0
T16	261102	4	0	0
T17	0	5	0	0
T18	0	14	0	0
T22	0	14	0	0
T28	0	2	0	0
T29	0	4	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	14558	1	0	0
T35	430528	2	0	0
T36	51696	0	0	0
T37	1291	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	604746	1	0	0
T8	281006	0	0	0
T9	1171182	1	0	0
T10	455118	0	0	0
T14	427819	0	0	0
T16	87034	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	809666	2	0	0
T34	14558	1	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T38	247598	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	166749	0	0	0
T53	141834	0	0	0
T54	45574	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1103	0	0
T1	315402	7	0	0
T2	32958	0	0	0
T3	46605	0	0	0
T4	211548	0	0	0
T5	26448	0	0	0
T6	445611	1	0	0
T7	1209492	1	0	0
T8	562012	1	0	0
T9	2342364	2	0	0
T10	910236	0	0	0
T14	427819	6	0	0
T16	87034	2	0	0
T17	0	6	0	0
T18	0	15	0	0
T21	0	2	0	0
T22	0	13	0	0
T29	0	2	0	0
T33	0	1	0	0
T34	14558	5	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T38	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1039478318	0	0
T1	420536	223045	0	0
T2	43944	12662	0	0
T3	62140	26862	0	0
T4	282064	237906	0	0
T5	35264	25745	0	0
T6	594148	149915	0	0
T7	1209492	322708	0	0
T8	562012	453877	0	0
T9	2342364	627486	0	0
T10	910236	262312	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T1	315402	9	0	0
T2	43944	3	0	0
T3	62140	1	0	0
T4	282064	0	0	0
T5	35264	1	0	0
T6	594148	3	0	0
T7	1209492	3	0	0
T8	562012	3	0	0
T9	2342364	5	0	0
T10	910236	2	0	0
T14	0	14	0	0
T16	87034	4	0	0
T17	0	5	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	5	0	0
T35	0	2	0	0
T36	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2523	0	0
T1	315402	9	0	0
T2	43944	3	0	0
T3	62140	1	0	0
T4	282064	0	0	0
T5	35264	1	0	0
T6	594148	2	0	0
T7	1209492	3	0	0
T8	562012	3	0	0
T9	2342364	5	0	0
T10	910236	2	0	0
T14	0	14	0	0
T16	87034	4	0	0
T17	0	5	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	2	0	0
T36	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2463	0	0
T1	315402	9	0	0
T2	43944	3	0	0
T3	62140	1	0	0
T4	282064	0	0	0
T5	35264	1	0	0
T6	594148	2	0	0
T7	1209492	3	0	0
T8	562012	2	0	0
T9	2342364	5	0	0
T10	910236	2	0	0
T14	0	14	0	0
T16	87034	4	0	0
T17	0	4	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	2	0	0
T36	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2415	0	0
T1	315402	9	0	0
T2	43944	3	0	0
T3	62140	1	0	0
T4	282064	0	0	0
T5	35264	1	0	0
T6	594148	2	0	0
T7	1209492	3	0	0
T8	562012	2	0	0
T9	2342364	5	0	0
T10	910236	2	0	0
T14	0	14	0	0
T16	87034	4	0	0
T17	0	4	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	2	0	0
T36	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6099	0	0
T1	210268	12	0	0
T2	21972	1	0	0
T3	62140	9	0	0
T4	282064	0	0	0
T5	35264	2	0	0
T6	594148	0	0	0
T7	1209492	3	0	0
T8	562012	0	0	0
T9	2342364	4	0	0
T10	910236	0	0	0
T14	0	65	0	0
T16	174068	1	0	0
T17	0	1	0	0
T18	0	8	0	0
T19	0	3	0	0
T22	0	8	0	0
T29	0	4	0	0
T31	0	4	0	0
T34	29116	6	0	0
T36	0	4	0	0
T38	0	4	0	0
T57	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	610506	0	0
T1	210268	689	0	0
T2	21972	552	0	0
T3	62140	937	0	0
T4	282064	0	0	0
T5	35264	173	0	0
T6	594148	0	0	0
T7	1209492	434	0	0
T8	562012	0	0	0
T9	2342364	245	0	0
T10	910236	0	0	0
T14	0	8926	0	0
T16	174068	164	0	0
T17	0	77	0	0
T18	0	825	0	0
T19	0	713	0	0
T22	0	1879	0	0
T29	0	365	0	0
T31	0	487	0	0
T34	29116	162	0	0
T36	0	613	0	0
T38	0	1007	0	0
T57	0	109	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5731	0	0
T1	210268	4	0	0
T2	21972	0	0	0
T3	46605	8	0	0
T4	211548	0	0	0
T5	26448	1	0	0
T6	445611	0	0	0
T7	1209492	2	0	0
T8	562012	0	0	0
T9	2342364	3	0	0
T10	910236	0	0	0
T14	427819	60	0	0
T16	174068	1	0	0
T18	0	7	0	0
T19	0	9	0	0
T20	0	9	0	0
T22	0	4	0	0
T29	0	3	0	0
T31	0	3	0	0
T34	29116	1	0	0
T35	430528	0	0	0
T36	51696	3	0	0
T37	1291	0	0	0
T38	0	6	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	4	0	0
T62	0	2	0	0
T63	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	31070	1	0	0
T4	141032	0	0	0
T5	17632	1	0	0
T6	297074	0	0	0
T7	604746	0	0	0
T8	281006	0	0	0
T9	1171182	0	0	0
T10	455118	0	0	0
T11	63521	0	0	0
T14	427819	4	0	0
T16	87034	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	2	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T31	0	1	0	0
T34	29116	4	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T41	0	3	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	17786	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6376	0	0
T11	254084	1457	0	0
T12	0	1379	0	0
T13	0	663	0	0
T17	258772	0	0	0
T24	0	1433	0	0
T25	0	1444	0	0
T26	211644	0	0	0
T27	3914800	0	0	0
T28	481956	0	0	0
T29	1654120	0	0	0
T30	255456	0	0	0
T31	70648	0	0	0
T32	725444	0	0	0
T33	1294132	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5296	0	0
T11	254084	1217	0	0
T12	0	1139	0	0
T13	0	543	0	0
T17	258772	0	0	0
T24	0	1193	0	0
T25	0	1204	0	0
T26	211644	0	0	0
T27	3914800	0	0	0
T28	481956	0	0	0
T29	1654120	0	0	0
T30	255456	0	0	0
T31	70648	0	0	0
T32	725444	0	0	0
T33	1294132	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	420536	420188	0	0
T2	43944	43604	0	0
T3	62140	61896	0	0
T4	282064	281764	0	0
T5	35264	34904	0	0
T6	594148	594112	0	0
T7	1209492	1209468	0	0
T8	562012	561988	0	0
T9	2342364	2342336	0	0
T10	910236	909860	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	420536	420188	0	0
T2	43944	43604	0	0
T3	62140	61896	0	0
T4	282064	281764	0	0
T5	35264	34904	0	0
T6	594148	594112	0	0
T7	1209492	1209468	0	0
T8	562012	561988	0	0
T9	2342364	2342336	0	0
T10	910236	909860	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T14,T26
1	1	0	Covered	T3,T7,T9
1	1	1	Covered	T1,T3,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T34,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T34,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T1,T5,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T7,T14,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T34,T17,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T9,T34
1	Covered	T1,T2,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T7,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T5
Phase1St	198	Covered	T1,T2,T5
Phase2St	215	Covered	T1,T2,T5
Phase3St	233	Covered	T1,T2,T5
TerminalSt	249	Covered	T1,T2,T5
TimeoutSt	159	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T6,T7
IdleSt->TimeoutSt	159	Covered	T1,T3,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T22,T73
Phase0St->Phase1St	198	Covered	T1,T2,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T20,T44
Phase1St->Phase2St	215	Covered	T1,T2,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T21,T74
Phase2St->Phase3St	233	Covered	T1,T2,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T75,T76,T77
Phase3St->TerminalSt	249	Covered	T1,T2,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T9,T34
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T34
TimeoutSt->Phase0St	172	Covered	T1,T5,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T22,T68
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T20,T44
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T21,T74
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T75,T76,T77
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	649666724	330	0	0
CheckAccumTrig0_A	649666724	765	0	0
CheckAccumTrig1_A	649666724	44	0	0
CheckClr_A	649666724	385	0	0
CheckEn_A	649450110	256099304	0	0
CheckPhase0_A	649666724	849	0	0
CheckPhase1_A	649666724	836	0	0
CheckPhase2_A	649666724	814	0	0
CheckPhase3_A	649666724	801	0	0
CheckTimeout0_A	649666724	1470	0	0
CheckTimeoutSt1_A	649666724	149542	0	0
CheckTimeoutSt2_A	649666724	1362	0	0
CheckTimeoutStTrig_A	649666724	63	0	0
ErrorStAllEscAsserted_A	649666724	1590	0	0
ErrorStIsTerminal_A	649666724	1320	0	0
EscStateOut_A	649448350	649382636	0	0
u_state_regs_A	649666724	649485939	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	330	0	0
T11	63521	59	0	0
T12	0	66	0	0
T13	0	36	0	0
T17	64693	0	0	0
T24	0	97	0	0
T25	0	72	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	765	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	2	0	0
T16	87034	0	0	0
T17	0	5	0	0
T18	0	4	0	0
T22	0	9	0	0
T33	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	44	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	385	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T17	0	6	0	0
T18	0	3	0	0
T21	0	1	0	0
T22	0	5	0	0
T33	0	1	0	0
T34	0	1	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649450110	256099304	0	0
T1	105134	9892	0	0
T2	10986	582	0	0
T3	15535	12870	0	0
T4	70516	31335	0	0
T5	8816	5666	0	0
T6	148537	582	0	0
T7	302373	8869	0	0
T8	140503	131427	0	0
T9	585591	584908	0	0
T10	227559	11030	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	849	0	0
T1	105134	2	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	2	0	0
T17	0	5	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	836	0	0
T1	105134	2	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	2	0	0
T17	0	5	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	814	0	0
T1	105134	2	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	2	0	0
T17	0	4	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	801	0	0
T1	105134	2	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	2	0	0
T17	0	4	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1470	0	0
T1	105134	3	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	6	0	0
T17	0	1	0	0
T22	0	1	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	3	0	0
T38	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	149542	0	0
T1	105134	388	0	0
T2	10986	0	0	0
T3	15535	96	0	0
T4	70516	0	0	0
T5	8816	70	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	881	0	0
T17	0	77	0	0
T22	0	1	0	0
T31	0	112	0	0
T34	0	80	0	0
T36	0	516	0	0
T38	0	537	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1362	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	6	0	0
T19	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T36	0	3	0	0
T38	0	3	0	0
T57	0	1	0	0
T60	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	63	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T19	0	1	0	0
T41	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1590	0	0
T11	63521	376	0	0
T12	0	335	0	0
T13	0	156	0	0
T17	64693	0	0	0
T24	0	368	0	0
T25	0	355	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1320	0	0
T11	63521	316	0	0
T12	0	275	0	0
T13	0	126	0	0
T17	64693	0	0	0
T24	0	308	0	0
T25	0	295	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649448350	649382636	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	649485939	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T8,T10,T14
1	1	0	Covered	T7,T9,T36
1	1	1	Covered	T3,T5,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T9
0	1	Covered	T34,T14,T31
1	0	Covered	T7,T9,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T9,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Not Covered
1	1	Covered	T34,T14,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T7,T8,T34

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T9,T10,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T6,T14,T35

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T8,T9
1	Covered	T2,T14,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T34,T14,T35

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T10,T34

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T7
Phase1St	198	Covered	T2,T6,T8
Phase2St	215	Covered	T2,T6,T8
Phase3St	233	Covered	T2,T6,T8
TerminalSt	249	Covered	T2,T6,T8
TimeoutSt	159	Covered	T3,T5,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T6,T8
IdleSt->TimeoutSt	159	Covered	T3,T5,T7
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T7,T18,T22
Phase0St->Phase1St	198	Covered	T2,T6,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T20,T78
Phase1St->Phase2St	215	Covered	T2,T6,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T79,T80
Phase2St->Phase3St	233	Covered	T2,T6,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T22,T20,T23
Phase3St->TerminalSt	249	Covered	T2,T6,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T34,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T9
TimeoutSt->Phase0St	172	Covered	T7,T9,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T9,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T9
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T9
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T18,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T20,T78
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T79,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T20,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T34,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	649666724	310	0	0
CheckAccumTrig0_A	649666724	480	0	0
CheckAccumTrig1_A	649666724	23	0	0
CheckClr_A	649666724	236	0	0
CheckEn_A	649450110	259159813	0	0
CheckPhase0_A	649666724	576	0	0
CheckPhase1_A	649666724	566	0	0
CheckPhase2_A	649666724	555	0	0
CheckPhase3_A	649666724	541	0	0
CheckTimeout0_A	649666724	2313	0	0
CheckTimeoutSt1_A	649666724	220279	0	0
CheckTimeoutSt2_A	649666724	2205	0	0
CheckTimeoutStTrig_A	649666724	84	0	0
ErrorStAllEscAsserted_A	649666724	1630	0	0
ErrorStIsTerminal_A	649666724	1360	0	0
EscStateOut_A	649448350	649382636	0	0
u_state_regs_A	649666724	649485939	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	310	0	0
T11	63521	69	0	0
T12	0	51	0	0
T13	0	44	0	0
T17	64693	0	0	0
T24	0	75	0	0
T25	0	71	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	480	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	1	0	0
T10	227559	1	0	0
T14	0	5	0	0
T16	87034	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	23	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	427819	0	0	0
T16	87034	0	0	0
T20	0	3	0	0
T34	14558	0	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	236	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	427819	6	0	0
T16	87034	0	0	0
T18	0	1	0	0
T22	0	5	0	0
T34	14558	1	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T38	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649450110	259159813	0	0
T1	105134	105046	0	0
T2	10986	586	0	0
T3	15535	1705	0	0
T4	70516	65691	0	0
T5	8816	5670	0	0
T6	148537	586	0	0
T7	302373	301662	0	0
T8	140503	2010	0	0
T9	585591	9968	0	0
T10	227559	2603	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	576	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	2	0	0
T10	227559	1	0	0
T14	0	9	0	0
T16	87034	1	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	566	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	2	0	0
T10	227559	1	0	0
T14	0	9	0	0
T16	87034	1	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	555	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	2	0	0
T10	227559	1	0	0
T14	0	9	0	0
T16	87034	1	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	541	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	2	0	0
T10	227559	1	0	0
T14	0	9	0	0
T16	87034	1	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	2313	0	0
T3	15535	5	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	4	0	0
T10	227559	0	0	0
T14	0	4	0	0
T16	87034	0	0	0
T18	0	2	0	0
T22	0	5	0	0
T29	0	1	0	0
T31	0	1	0	0
T34	14558	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	220279	0	0
T3	15535	605	0	0
T4	70516	0	0	0
T5	8816	103	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	245	0	0
T10	227559	0	0	0
T14	0	112	0	0
T16	87034	0	0	0
T18	0	231	0	0
T22	0	1718	0	0
T29	0	253	0	0
T31	0	91	0	0
T34	14558	12	0	0
T38	0	470	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	2205	0	0
T3	15535	5	0	0
T4	70516	0	0	0
T5	8816	1	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	3	0	0
T10	227559	0	0	0
T16	87034	0	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	8	0	0
T22	0	3	0	0
T29	0	1	0	0
T34	14558	0	0	0
T38	0	3	0	0
T61	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	84	0	0
T11	63521	0	0	0
T14	427819	4	0	0
T18	0	1	0	0
T22	0	2	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T31	0	1	0	0
T34	14558	2	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T41	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T72	17786	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1630	0	0
T11	63521	367	0	0
T12	0	338	0	0
T13	0	178	0	0
T17	64693	0	0	0
T24	0	367	0	0
T25	0	380	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1360	0	0
T11	63521	307	0	0
T12	0	278	0	0
T13	0	148	0	0
T17	64693	0	0	0
T24	0	307	0	0
T25	0	320	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649448350	649382636	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	649485939	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T7
1	0	1	Covered	T8,T10,T35
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T3,T7,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T3,T34,T20
1	0	Covered	T22,T42,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T42,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T16
1	0	Not Covered
1	1	Covered	T3,T34,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T7,T16,T34

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T9,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T8,T16,T32

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T3,T6,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T6
Phase1St	198	Covered	T1,T3,T6
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T3,T7,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T6,T7
IdleSt->TimeoutSt	159	Covered	T3,T7,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T73,T81,T48
Phase0St->Phase1St	198	Covered	T1,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T44,T82,T76
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T8,T19,T20
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T42,T83
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T16,T34
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T16,T14
TimeoutSt->Phase0St	172	Covered	T3,T34,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T34,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T48,T80
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T44,T82,T76
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T19,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T42,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	649666724	296	0	0
CheckAccumTrig0_A	649666724	497	0	0
CheckAccumTrig1_A	649666724	18	0	0
CheckClr_A	649666724	237	0	0
CheckEn_A	649450110	265605376	0	0
CheckPhase0_A	649666724	547	0	0
CheckPhase1_A	649666724	539	0	0
CheckPhase2_A	649666724	529	0	0
CheckPhase3_A	649666724	519	0	0
CheckTimeout0_A	649666724	700	0	0
CheckTimeoutSt1_A	649666724	76911	0	0
CheckTimeoutSt2_A	649666724	642	0	0
CheckTimeoutStTrig_A	649666724	40	0	0
ErrorStAllEscAsserted_A	649666724	1551	0	0
ErrorStIsTerminal_A	649666724	1281	0	0
EscStateOut_A	649448350	649382636	0	0
u_state_regs_A	649666724	649485939	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	296	0	0
T11	63521	46	0	0
T12	0	61	0	0
T13	0	40	0	0
T17	64693	0	0	0
T24	0	57	0	0
T25	0	92	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	497	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	2	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	1	0	0
T16	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	18	0	0
T22	809666	1	0	0
T38	247598	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	166749	0	0	0
T53	141834	0	0	0
T54	45574	0	0	0
T55	83982	0	0	0
T56	318677	0	0	0
T57	81659	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	294264	0	0	0
T90	279193	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	237	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	1	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T16	0	2	0	0
T18	0	3	0	0
T21	0	1	0	0
T22	0	2	0	0
T29	0	1	0	0
T34	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649450110	265605376	0	0
T1	105134	98143	0	0
T2	10986	10900	0	0
T3	15535	590	0	0
T4	70516	70440	0	0
T5	8816	5684	0	0
T6	148537	590	0	0
T7	302373	8760	0	0
T8	140503	196283	0	0
T9	585591	29379	0	0
T10	227559	21215	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	547	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	2	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	1	0	0
T16	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	539	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	2	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	1	0	0
T16	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	529	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	1	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	1	0	0
T16	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	519	0	0
T1	105134	1	0	0
T2	10986	0	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	1	0	0
T7	302373	1	0	0
T8	140503	1	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	1	0	0
T16	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	700	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	46	0	0
T16	87034	1	0	0
T18	0	5	0	0
T22	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T34	14558	2	0	0
T57	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	76911	0	0
T3	15535	29	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	217	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	6516	0	0
T16	87034	164	0	0
T18	0	447	0	0
T22	0	160	0	0
T29	0	107	0	0
T31	0	284	0	0
T34	14558	70	0	0
T57	0	107	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	642	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	427819	46	0	0
T16	87034	1	0	0
T18	0	5	0	0
T19	0	1	0	0
T22	0	1	0	0
T29	0	2	0	0
T31	0	2	0	0
T34	14558	0	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0
T57	0	1	0	0
T61	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	40	0	0
T3	15535	1	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T16	87034	0	0	0
T20	0	3	0	0
T34	14558	2	0	0
T41	0	1	0	0
T68	0	1	0	0
T71	0	1	0	0
T85	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1551	0	0
T11	63521	343	0	0
T12	0	348	0	0
T13	0	165	0	0
T17	64693	0	0	0
T24	0	353	0	0
T25	0	342	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1281	0	0
T11	63521	283	0	0
T12	0	288	0	0
T13	0	135	0	0
T17	64693	0	0	0
T24	0	293	0	0
T25	0	282	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649448350	649382636	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	649485939	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T9,T34

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T26,T28
1	1	0	Covered	T3,T16,T36
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T36
1	0	Covered	T29,T57,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T57,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T1,T2,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T36,T29,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T9,T34
1	Covered	T1,T2,T33

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T7,T29,T32

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T9,T34,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T34,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T34,T36

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T32,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T7,T9,T34
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T41,T48,T94
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T95,T96,T97
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T65,T68
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T76,T98,T99
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T34,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T7
TimeoutSt->Phase0St	172	Covered	T1,T2,T36

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T9,T34
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T41,T48,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T95,T96,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T65,T68
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T76,T98,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T34,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	649666724	357	0	0
CheckAccumTrig0_A	649666724	503	0	0
CheckAccumTrig1_A	649666724	21	0	0
CheckClr_A	649666724	245	0	0
CheckEn_A	649450110	258613825	0	0
CheckPhase0_A	649666724	587	0	0
CheckPhase1_A	649666724	582	0	0
CheckPhase2_A	649666724	565	0	0
CheckPhase3_A	649666724	554	0	0
CheckTimeout0_A	649666724	1616	0	0
CheckTimeoutSt1_A	649666724	163774	0	0
CheckTimeoutSt2_A	649666724	1522	0	0
CheckTimeoutStTrig_A	649666724	72	0	0
ErrorStAllEscAsserted_A	649666724	1605	0	0
ErrorStIsTerminal_A	649666724	1335	0	0
EscStateOut_A	649448350	649382636	0	0
u_state_regs_A	649666724	649485939	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	357	0	0
T11	63521	90	0	0
T12	0	84	0	0
T13	0	45	0	0
T17	64693	0	0	0
T24	0	72	0	0
T25	0	66	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	503	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	427819	1	0	0
T16	87034	0	0	0
T18	0	10	0	0
T22	0	5	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	14558	1	0	0
T35	430528	0	0	0
T36	51696	0	0	0
T37	1291	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	21	0	0
T17	64693	0	0	0
T18	257231	0	0	0
T22	809666	0	0	0
T29	413530	1	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	166749	0	0	0
T57	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	5439	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	245	0	0
T1	105134	5	0	0
T2	10986	0	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T18	0	8	0	0
T22	0	1	0	0
T29	0	1	0	0
T34	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T61	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649450110	258613825	0	0
T1	105134	9964	0	0
T2	10986	594	0	0
T3	15535	11697	0	0
T4	70516	70440	0	0
T5	8816	8725	0	0
T6	148537	148157	0	0
T7	302373	3417	0	0
T8	140503	124157	0	0
T9	585591	3231	0	0
T10	227559	227464	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	587	0	0
T1	105134	6	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	582	0	0
T1	105134	6	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	565	0	0
T1	105134	6	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	554	0	0
T1	105134	6	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	1	0	0
T10	227559	0	0	0
T14	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1616	0	0
T1	105134	9	0	0
T2	10986	1	0	0
T3	15535	2	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	9	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T36	0	1	0	0
T57	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	163774	0	0
T1	105134	301	0	0
T2	10986	552	0	0
T3	15535	207	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	217	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	1417	0	0
T18	0	147	0	0
T19	0	713	0	0
T29	0	5	0	0
T36	0	97	0	0
T57	0	2	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1522	0	0
T1	105134	3	0	0
T2	10986	0	0	0
T3	15535	2	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	1	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	8	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	72	0	0
T1	105134	6	0	0
T2	10986	1	0	0
T3	15535	0	0	0
T4	70516	0	0	0
T5	8816	0	0	0
T6	148537	0	0	0
T7	302373	0	0	0
T8	140503	0	0	0
T9	585591	0	0	0
T10	227559	0	0	0
T14	0	1	0	0
T20	0	3	0	0
T36	0	1	0	0
T41	0	1	0	0
T61	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1605	0	0
T11	63521	371	0	0
T12	0	358	0	0
T13	0	164	0	0
T17	64693	0	0	0
T24	0	345	0	0
T25	0	367	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	1335	0	0
T11	63521	311	0	0
T12	0	298	0	0
T13	0	134	0	0
T17	64693	0	0	0
T24	0	285	0	0
T25	0	307	0	0
T26	52911	0	0	0
T27	978700	0	0	0
T28	120489	0	0	0
T29	413530	0	0	0
T30	63864	0	0	0
T31	17662	0	0	0
T32	181361	0	0	0
T33	323533	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649448350	649382636	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649666724	649485939	0	0
T1	105134	105047	0	0
T2	10986	10901	0	0
T3	15535	15474	0	0
T4	70516	70441	0	0
T5	8816	8726	0	0
T6	148537	148528	0	0
T7	302373	302367	0	0
T8	140503	140497	0	0
T9	585591	585584	0	0
T10	227559	227465	0	0