Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67211819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32720419

1

T1

792

T2

2904

T3

1715

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15068783	1			T1	276		T2	1965		T3	652
values[0x0]	41256792	1			T1	1084		T2	3193		T3	2220
values[0x1]	43606663	1			T1	1064		T2	3190		T3	2168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57243352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42688886

1

T1

998

T2

3605

T3

2095

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	320445	1			T1	8		T2	22		T3	16
valid_sources[0x01]	337971	1			T1	16		T2	30		T3	17
valid_sources[0x02]	344875	1			T1	8		T2	25		T3	18
valid_sources[0x03]	317623	1			T1	22		T2	23		T3	33
valid_sources[0x04]	660450	1			T1	5		T2	42		T3	18
valid_sources[0x05]	701118	1			T1	15		T2	6		T3	8
valid_sources[0x06]	340340	1			T1	17		T2	16		T3	10
valid_sources[0x07]	324925	1			T1	17		T2	15		T3	23
valid_sources[0x08]	326575	1			T1	25		T2	35		T3	20
valid_sources[0x09]	318824	1			T1	10		T2	39		T3	33
valid_sources[0x0a]	339515	1			T1	19		T2	33		T3	17
valid_sources[0x0b]	326089	1			T1	1		T2	34		T3	24
valid_sources[0x0c]	326377	1			T1	6		T3	17		T4	301
valid_sources[0x0d]	873335	1			T1	12		T2	25		T3	17
valid_sources[0x0e]	333795	1			T1	15		T2	9		T3	8
valid_sources[0x0f]	338279	1			T1	10		T2	34		T3	18
valid_sources[0x10]	331512	1			T1	13		T2	66		T3	27
valid_sources[0x11]	329180	1			T1	5		T2	20		T3	28
valid_sources[0x12]	700704	1			T1	17		T2	19		T3	22
valid_sources[0x13]	320471	1			T2	8		T3	19		T4	305
valid_sources[0x14]	325926	1			T1	9		T2	15		T3	11
valid_sources[0x15]	360550	1			T1	15		T2	66		T3	22
valid_sources[0x16]	324574	1			T1	15		T2	30		T3	19
valid_sources[0x17]	328102	1			T2	90		T3	12		T4	273
valid_sources[0x18]	340198	1			T1	9		T3	37		T4	303
valid_sources[0x19]	328948	1			T1	14		T2	23		T3	25
valid_sources[0x1a]	327003	1			T1	10		T2	31		T3	33
valid_sources[0x1b]	326292	1			T2	76		T3	22		T4	279
valid_sources[0x1c]	339241	1			T1	15		T2	20		T3	18
valid_sources[0x1d]	326072	1			T1	5		T2	47		T3	13
valid_sources[0x1e]	331647	1			T1	9		T2	3		T3	21
valid_sources[0x1f]	341889	1			T1	11		T2	25		T3	19
valid_sources[0x20]	322945	1			T1	3		T2	64		T3	18
valid_sources[0x21]	405432	1			T1	11		T2	22		T3	26
valid_sources[0x22]	372756	1			T1	16		T2	23		T3	13
valid_sources[0x23]	319763	1			T1	11		T2	22		T3	16
valid_sources[0x24]	734201	1			T1	19		T2	11		T3	14
valid_sources[0x25]	331492	1			T1	5		T2	18		T3	16
valid_sources[0x26]	333085	1			T1	8		T2	2		T3	19
valid_sources[0x27]	347486	1			T1	6		T3	22		T4	271
valid_sources[0x28]	323504	1			T1	2		T3	13		T4	257
valid_sources[0x29]	334532	1			T1	5		T2	30		T3	28
valid_sources[0x2a]	345892	1			T1	1		T2	11		T3	24
valid_sources[0x2b]	328326	1			T1	7		T3	28		T4	311
valid_sources[0x2c]	603085	1			T1	10		T2	26		T3	16
valid_sources[0x2d]	333622	1			T1	19		T2	26		T3	21
valid_sources[0x2e]	782052	1			T1	1		T2	24		T3	20
valid_sources[0x2f]	334434	1			T1	5		T2	11		T3	12
valid_sources[0x30]	327924	1			T1	5		T2	52		T3	23
valid_sources[0x31]	325726	1			T1	15		T2	38		T3	22
valid_sources[0x32]	327059	1			T1	17		T2	100		T3	25
valid_sources[0x33]	325181	1			T1	20		T2	6		T3	15
valid_sources[0x34]	329096	1			T1	10		T2	53		T3	23
valid_sources[0x35]	344085	1			T1	2		T2	4		T3	13
valid_sources[0x36]	321661	1			T1	5		T2	5		T3	26
valid_sources[0x37]	324319	1			T1	12		T2	53		T3	21
valid_sources[0x38]	323304	1			T1	13		T2	10		T3	23
valid_sources[0x39]	326172	1			T1	14		T2	93		T3	12
valid_sources[0x3a]	318128	1			T1	9		T2	34		T3	21
valid_sources[0x3b]	744909	1			T1	15		T3	19		T4	264
valid_sources[0x3c]	329013	1			T1	8		T2	11		T3	20
valid_sources[0x3d]	340092	1			T1	9		T2	46		T3	18
valid_sources[0x3e]	334751	1			T1	8		T2	37		T3	16
valid_sources[0x3f]	330354	1			T1	5		T2	16		T3	23
valid_sources[0x40]	335540	1			T1	6		T2	71		T3	25
valid_sources[0x41]	319980	1			T1	12		T2	45		T3	21
valid_sources[0x42]	327755	1			T1	10		T2	78		T3	19
valid_sources[0x43]	327541	1			T2	68		T3	30		T4	272
valid_sources[0x44]	523309	1			T1	13		T2	5		T3	23
valid_sources[0x45]	332524	1			T1	2		T2	96		T3	17
valid_sources[0x46]	332618	1			T1	11		T3	26		T4	295
valid_sources[0x47]	364350	1			T1	6		T2	54		T3	21
valid_sources[0x48]	330297	1			T1	6		T2	12		T3	9
valid_sources[0x49]	326988	1			T1	5		T2	6		T3	35
valid_sources[0x4a]	327583	1			T1	6		T2	23		T3	19
valid_sources[0x4b]	372976	1			T2	95		T3	19		T4	322
valid_sources[0x4c]	332394	1			T1	2		T2	37		T3	14
valid_sources[0x4d]	328005	1			T1	3		T2	34		T3	16
valid_sources[0x4e]	324865	1			T1	4		T3	10		T4	333
valid_sources[0x4f]	339625	1			T1	5		T2	1		T3	18
valid_sources[0x50]	337346	1			T2	2		T3	17		T4	298
valid_sources[0x51]	327036	1			T1	7		T2	14		T3	25
valid_sources[0x52]	326752	1			T1	8		T2	48		T3	31
valid_sources[0x53]	343361	1			T1	9		T2	52		T3	26
valid_sources[0x54]	711914	1			T1	8		T2	129		T3	11
valid_sources[0x55]	322994	1			T1	3		T3	18		T4	258
valid_sources[0x56]	567071	1			T1	7		T2	57		T3	19
valid_sources[0x57]	325508	1			T1	8		T3	27		T4	260
valid_sources[0x58]	659886	1			T1	21		T2	88		T3	22
valid_sources[0x59]	320803	1			T1	10		T2	32		T3	22
valid_sources[0x5a]	328616	1			T1	16		T2	20		T3	15
valid_sources[0x5b]	327298	1			T1	2		T2	3		T3	16
valid_sources[0x5c]	337967	1			T1	1		T2	16		T3	13
valid_sources[0x5d]	895430	1			T1	1		T2	15		T3	21
valid_sources[0x5e]	328179	1			T1	10		T3	16		T4	279
valid_sources[0x5f]	333206	1			T1	6		T2	66		T3	23
valid_sources[0x60]	327703	1			T1	5		T2	74		T3	16
valid_sources[0x61]	334903	1			T1	5		T2	16		T3	12
valid_sources[0x62]	331774	1			T1	21		T2	55		T3	16
valid_sources[0x63]	578903	1			T1	12		T2	118		T3	21
valid_sources[0x64]	326784	1			T2	1		T3	21		T4	276
valid_sources[0x65]	324929	1			T1	14		T2	27		T3	22
valid_sources[0x66]	359881	1			T1	7		T2	58		T3	25
valid_sources[0x67]	338781	1			T1	36		T2	54		T3	17
valid_sources[0x68]	720995	1			T1	4		T2	30		T3	15
valid_sources[0x69]	330857	1			T1	11		T2	37		T3	23
valid_sources[0x6a]	325481	1			T1	10		T2	35		T3	20
valid_sources[0x6b]	636808	1			T1	4		T2	87		T3	14
valid_sources[0x6c]	614555	1			T2	66		T3	18		T4	299
valid_sources[0x6d]	336563	1			T1	10		T2	34		T3	27
valid_sources[0x6e]	321702	1			T1	8		T2	60		T3	18
valid_sources[0x6f]	320014	1			T1	6		T2	37		T3	10
valid_sources[0x70]	336007	1			T1	15		T2	41		T3	14
valid_sources[0x71]	330754	1			T1	9		T2	11		T3	10
valid_sources[0x72]	339383	1			T2	48		T3	20		T4	271
valid_sources[0x73]	369422	1			T1	12		T2	26		T3	26
valid_sources[0x74]	327555	1			T1	6		T2	61		T3	22
valid_sources[0x75]	370744	1			T1	7		T2	21		T3	15
valid_sources[0x76]	321149	1			T1	10		T2	5		T3	19
valid_sources[0x77]	620752	1			T1	3		T3	18		T4	274
valid_sources[0x78]	323371	1			T2	39		T3	16		T4	288
valid_sources[0x79]	329518	1			T1	9		T2	9		T3	15
valid_sources[0x7a]	322294	1			T1	19		T2	5		T3	24
valid_sources[0x7b]	649108	1			T1	12		T2	49		T3	16
valid_sources[0x7c]	342998	1			T1	7		T2	67		T3	18
valid_sources[0x7d]	575840	1			T1	8		T2	31		T3	24
valid_sources[0x7e]	320298	1			T1	1		T2	24		T3	21
valid_sources[0x7f]	332183	1			T1	1		T2	24		T3	17
valid_sources[0x80]	372504	1			T1	9		T2	20		T3	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7536055

1

T1

146

T2

992

T3

337

values[0x0]

all_enables

biggest_size

15870020

1

T1

415

T2

1193

T3

857

values[0x1]

all_enables

biggest_size

9314344

1

T1

231

T2

719

T3

521