Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T195,T43
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T27

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14601	0	0
DisabledNoTrigBkwd_A	2147483647	830096	0	0
DisabledNoTrigFwd_A	2147483647	1465210224	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14601	0	0
T9	896870	0	0	0
T21	0	516	0	0
T34	128869	0	0	0
T43	0	747	0	0
T46	1179	463	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0
T87	24443	0	0	0
T92	557507	0	0	0
T195	1196	438	0	0
T196	0	1129	0	0
T197	0	983	0	0
T198	0	206	0	0
T199	4746	1220	0	0
T200	0	731	0	0
T201	0	186	0	0
T202	0	892	0	0
T203	0	612	0	0
T204	0	243	0	0
T205	0	1100	0	0
T206	0	1034	0	0
T207	0	557	0	0
T208	0	1113	0	0
T209	0	506	0	0
T210	0	793	0	0
T211	0	1132	0	0
T212	19481	0	0	0
T213	604879	0	0	0
T214	6855	0	0	0
T215	14284	0	0	0
T216	29220	0	0	0
T217	137116	0	0	0
T218	250626	0	0	0
T219	970621	0	0	0
T220	278492	0	0	0
T221	10695	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	830096	0	0
T2	186260	26	0	0
T3	108140	0	0	0
T4	2574704	401	0	0
T5	1046928	495	0	0
T6	396812	0	0	0
T7	1648946	1199	0	0
T8	0	22	0	0
T14	0	39	0	0
T15	0	9860	0	0
T16	0	3263	0	0
T17	0	212	0	0
T20	450756	107	0	0
T21	16016	6	0	0
T22	87796	0	0	0
T23	0	3359	0	0
T24	0	411	0	0
T25	0	98	0	0
T27	772828	238	0	0
T28	143496	44	0	0
T29	481856	1	0	0
T35	0	23	0	0
T64	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1465210224	0	0
T1	92096	70989	0	0
T2	372520	228763	0	0
T3	216280	68272	0	0
T4	2574704	1998251	0	0
T5	1046928	785718	0	0
T6	396812	109294	0	0
T20	450756	345036	0	0
T27	772828	582552	0	0
T28	143496	76242	0	0
T29	481856	374372	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T27

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T196,T201
1	1	Covered	T3,T4,T27

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T29,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667945598	3084	0	0
DisabledNoTrigBkwd_A	667945598	275576	0	0
DisabledNoTrigFwd_A	667945598	302214448	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	3084	0	0
T9	896870	0	0	0
T34	128869	0	0	0
T46	1179	463	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0
T196	0	1129	0	0
T201	0	186	0	0
T204	0	243	0	0
T207	0	557	0	0
T209	0	506	0	0
T212	19481	0	0	0
T213	604879	0	0	0
T214	6855	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	275576	0	0
T4	643676	370	0	0
T5	261732	495	0	0
T6	99203	0	0	0
T7	824473	3	0	0
T14	0	13	0	0
T15	0	2481	0	0
T20	112689	107	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	746	0	0
T24	0	158	0	0
T25	0	40	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	302214448	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	8836	0	0
T4	643676	243971	0	0
T5	261732	2079	0	0
T6	99203	3405	0	0
T20	112689	7269	0	0
T27	193207	192143	0	0
T28	35874	35787	0	0
T29	120464	13145	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T200,T202
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T28,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667945598	3455	0	0
DisabledNoTrigBkwd_A	667945598	171406	0	0
DisabledNoTrigFwd_A	667945598	391326474	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	3455	0	0
T87	24443	0	0	0
T92	557507	0	0	0
T199	4746	1220	0	0
T200	0	731	0	0
T202	0	892	0	0
T203	0	612	0	0
T215	14284	0	0	0
T216	29220	0	0	0
T217	137116	0	0	0
T218	250626	0	0	0
T219	970621	0	0	0
T220	278492	0	0	0
T221	10695	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	171406	0	0
T4	643676	26	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T8	0	16	0	0
T14	0	1	0	0
T16	0	1812	0	0
T17	0	212	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	107	0	0
T25	0	21	0	0
T27	193207	0	0	0
T28	35874	17	0	0
T29	120464	0	0	0
T35	0	12	0	0
T64	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	391326474	0	0
T1	23024	2091	0	0
T2	93130	85991	0	0
T3	54070	53971	0	0
T4	643676	524400	0	0
T5	261732	261723	0	0
T6	99203	3411	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	2332	0	0
T29	120464	120409	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T205,T208
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T28

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667945598	2651	0	0
DisabledNoTrigBkwd_A	667945598	183515	0	0
DisabledNoTrigFwd_A	667945598	387678785	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	2651	0	0
T32	366738	0	0	0
T37	263770	0	0	0
T69	314044	0	0	0
T72	366021	0	0	0
T186	140934	0	0	0
T187	39561	0	0	0
T188	123645	0	0	0
T189	365724	0	0	0
T190	12237	0	0	0
T195	1196	438	0	0
T205	0	1100	0	0
T208	0	1113	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	183515	0	0
T2	93130	5	0	0
T3	54070	0	0	0
T4	643676	5	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1190	0	0
T14	0	25	0	0
T15	0	1961	0	0
T16	0	11	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	2080	0	0
T24	0	253	0	0
T25	0	37	0	0
T27	193207	0	0	0
T28	35874	27	0	0
T29	120464	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	387678785	0	0
T1	23024	22966	0	0
T2	93130	18978	0	0
T3	54070	2723	0	0
T4	643676	620403	0	0
T5	261732	260193	0	0
T6	99203	3422	0	0
T20	112689	112589	0	0
T27	193207	192085	0	0
T28	35874	2336	0	0
T29	120464	120409	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T43,T197
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T27,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667945598	5411	0	0
DisabledNoTrigBkwd_A	667945598	199599	0	0
DisabledNoTrigFwd_A	667945598	383990517	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	5411	0	0
T7	824473	0	0	0
T14	81745	0	0	0
T15	495247	0	0	0
T16	373686	0	0	0
T21	4004	516	0	0
T22	43898	0	0	0
T23	843939	0	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T43	0	747	0	0
T63	8931	0	0	0
T197	0	983	0	0
T198	0	206	0	0
T206	0	1034	0	0
T210	0	793	0	0
T211	0	1132	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	199599	0	0
T2	93130	21	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	6	0	0
T8	0	6	0	0
T15	0	5418	0	0
T16	0	1440	0	0
T20	112689	0	0	0
T21	4004	6	0	0
T23	0	426	0	0
T27	193207	238	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	11	0	0
T64	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	383990517	0	0
T1	23024	22966	0	0
T2	93130	30756	0	0
T3	54070	2742	0	0
T4	643676	609477	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	5177	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0