Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T27

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T27,T5
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T28,T23
1	0	Covered	T4,T23,T15

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T23,T15

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T30,T31
1	1	Covered	T2,T28,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T27
1	Covered	T4,T7,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T28
1	Covered	T4,T29,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T27
1	Covered	T2,T28,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T27
1	Covered	T4,T28,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T27

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T27
Phase1St	198	Covered	T2,T4,T27
Phase2St	215	Covered	T2,T4,T27
Phase3St	233	Covered	T2,T4,T27
TerminalSt	249	Covered	T2,T4,T27
TimeoutSt	159	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T27
IdleSt->TimeoutSt	159	Covered	T2,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T32,T33,T34
Phase0St->Phase1St	198	Covered	T2,T4,T27
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T35,T18,T36
Phase1St->Phase2St	215	Covered	T2,T4,T27
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T23,T37,T38
Phase2St->Phase3St	233	Covered	T2,T4,T27
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T39,T32,T40
Phase3St->TerminalSt	249	Covered	T2,T4,T27
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T4,T28
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T3,T4
TimeoutSt->Phase0St	172	Covered	T2,T4,T28

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T27
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T27
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T18,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T27
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T27
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T32,T40
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T27
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1187	0	0
CheckAccumTrig0_A	2147483647	2487	0	0
CheckAccumTrig1_A	2147483647	133	0	0
CheckClr_A	2147483647	1215	0	0
CheckEn_A	2147483647	1138960019	0	0
CheckPhase0_A	2147483647	2883	0	0
CheckPhase1_A	2147483647	2834	0	0
CheckPhase2_A	2147483647	2783	0	0
CheckPhase3_A	2147483647	2727	0	0
CheckTimeout0_A	2147483647	5635	0	0
CheckTimeoutSt1_A	2147483647	564412	0	0
CheckTimeoutSt2_A	2147483647	5174	0	0
CheckTimeoutStTrig_A	2147483647	318	0	0
ErrorStAllEscAsserted_A	2147483647	6540	0	0
ErrorStIsTerminal_A	2147483647	5460	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1187	0	0
T9	3587480	0	0	0
T11	193232	259	0	0
T12	0	248	0	0
T13	0	156	0	0
T41	0	267	0	0
T42	0	257	0	0
T43	6164	0	0	0
T44	1509072	0	0	0
T45	207132	0	0	0
T46	4716	0	0	0
T47	465360	0	0	0
T48	54692	0	0	0
T49	79464	0	0	0
T50	38744	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T2	186260	5	0	0
T3	108140	0	0	0
T4	2574704	8	0	0
T5	1046928	1	0	0
T6	396812	0	0	0
T7	1648946	3	0	0
T8	0	3	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	6	0	0
T20	450756	1	0	0
T21	16016	1	0	0
T22	87796	0	0	0
T23	0	19	0	0
T24	0	3	0	0
T25	0	3	0	0
T27	772828	1	0	0
T28	143496	3	0	0
T29	481856	1	0	0
T35	0	8	0	0
T51	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T8	269950	0	0	0
T10	0	1	0	0
T14	81745	0	0	0
T15	990494	2	0	0
T16	747372	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	843939	1	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T30	0	2	0	0
T33	0	2	0	0
T35	185046	0	0	0
T40	0	1	0	0
T44	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	5	0	0
T62	0	1	0	0
T63	17862	0	0	0
T64	27476	0	0	0
T65	38729	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1215	0	0
T2	93130	5	0	0
T3	54070	0	0	0
T4	1931028	6	0	0
T5	785196	0	0	0
T6	297609	0	0	0
T7	1648946	0	0	0
T8	134975	1	0	0
T14	81745	0	0	0
T15	495247	1	0	0
T16	373686	0	0	0
T18	0	1	0	0
T19	0	5	0	0
T20	338067	0	0	0
T21	12012	0	0	0
T22	87796	0	0	0
T23	843939	18	0	0
T24	234082	1	0	0
T25	44047	0	0	0
T27	579621	0	0	0
T28	107622	5	0	0
T29	361392	0	0	0
T32	0	1	0	0
T35	0	7	0	0
T36	0	8	0	0
T39	0	2	0	0
T51	0	8	0	0
T52	0	12	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T66	0	1	0	0
T67	0	16	0	0
T68	0	4	0	0
T69	0	10	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138960019	0	0
T1	92096	70986	0	0
T2	372520	110585	0	0
T3	216280	68271	0	0
T4	2574704	1841297	0	0
T5	1046928	785718	0	0
T6	396812	109289	0	0
T20	450756	340334	0	0
T27	772828	582549	0	0
T28	143496	76240	0	0
T29	481856	374369	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2883	0	0
T2	279390	8	0	0
T3	162210	0	0	0
T4	2574704	9	0	0
T5	1046928	1	0	0
T6	396812	0	0	0
T7	824473	3	0	0
T8	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	3	0	0
T20	450756	1	0	0
T21	16016	1	0	0
T22	43898	0	0	0
T23	0	33	0	0
T24	0	3	0	0
T25	0	3	0	0
T27	772828	1	0	0
T28	143496	7	0	0
T29	481856	1	0	0
T35	0	1	0	0
T64	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2834	0	0
T2	279390	8	0	0
T3	162210	0	0	0
T4	2574704	9	0	0
T5	1046928	1	0	0
T6	396812	0	0	0
T7	824473	3	0	0
T8	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	3	0	0
T20	450756	1	0	0
T21	16016	1	0	0
T22	43898	0	0	0
T23	0	33	0	0
T24	0	3	0	0
T25	0	3	0	0
T27	772828	1	0	0
T28	143496	7	0	0
T29	481856	1	0	0
T35	0	1	0	0
T64	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2783	0	0
T2	279390	8	0	0
T3	162210	0	0	0
T4	2574704	9	0	0
T5	1046928	1	0	0
T6	396812	0	0	0
T7	824473	3	0	0
T8	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	3	0	0
T20	450756	1	0	0
T21	16016	1	0	0
T22	43898	0	0	0
T23	0	32	0	0
T24	0	3	0	0
T25	0	3	0	0
T27	772828	1	0	0
T28	143496	7	0	0
T29	481856	1	0	0
T35	0	1	0	0
T64	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2727	0	0
T2	279390	8	0	0
T3	162210	0	0	0
T4	2574704	9	0	0
T5	1046928	1	0	0
T6	396812	0	0	0
T7	824473	3	0	0
T8	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	3	0	0
T20	450756	1	0	0
T21	16016	1	0	0
T22	43898	0	0	0
T23	0	32	0	0
T24	0	3	0	0
T25	0	3	0	0
T27	772828	1	0	0
T28	143496	7	0	0
T29	481856	1	0	0
T35	0	1	0	0
T64	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5635	0	0
T2	186260	6	0	0
T3	216280	12	0	0
T4	2574704	18	0	0
T5	1046928	0	0	0
T6	396812	0	0	0
T14	0	2	0	0
T15	0	4	0	0
T16	0	5	0	0
T20	450756	0	0	0
T21	16016	0	0	0
T22	87796	0	0	0
T23	0	22	0	0
T25	0	1	0	0
T27	772828	0	0	0
T28	143496	5	0	0
T29	481856	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T51	0	4	0	0
T52	0	21	0	0
T64	0	1	0	0
T67	0	24	0	0
T69	0	6	0	0
T70	0	11	0	0
T71	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	564412	0	0
T2	186260	1087	0	0
T3	216280	1879	0	0
T4	2574704	1942	0	0
T5	1046928	0	0	0
T6	396812	0	0	0
T14	0	416	0	0
T15	0	144	0	0
T16	0	305	0	0
T20	450756	0	0	0
T21	16016	0	0	0
T22	87796	0	0	0
T23	0	4264	0	0
T25	0	62	0	0
T27	772828	0	0	0
T28	143496	671	0	0
T29	481856	0	0	0
T35	0	610	0	0
T36	0	246	0	0
T51	0	451	0	0
T52	0	3472	0	0
T64	0	254	0	0
T67	0	3253	0	0
T69	0	412	0	0
T70	0	549	0	0
T71	0	894	0	0
T72	0	199	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5174	0	0
T2	93130	3	0	0
T3	162210	12	0	0
T4	2574704	17	0	0
T5	1046928	0	0	0
T6	396812	0	0	0
T7	824473	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T20	450756	0	0	0
T21	16016	0	0	0
T22	131694	0	0	0
T23	0	8	0	0
T25	0	1	0	0
T27	772828	0	0	0
T28	143496	1	0	0
T29	481856	0	0	0
T35	0	5	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	3	0	0
T51	0	3	0	0
T52	0	11	0	0
T53	0	1	0	0
T67	0	25	0	0
T69	0	10	0	0
T70	0	11	0	0
T71	0	11	0	0
T72	0	2	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	318	0	0
T2	186260	3	0	0
T3	108140	0	0	0
T4	1287352	0	0	0
T5	523464	0	0	0
T6	198406	0	0	0
T8	269950	0	0	0
T10	0	5	0	0
T14	163490	1	0	0
T15	990494	0	0	0
T16	747372	0	0	0
T20	225378	0	0	0
T21	8008	0	0	0
T23	1687878	11	0	0
T24	468164	0	0	0
T25	88094	0	0	0
T27	386414	0	0	0
T28	71748	4	0	0
T29	240928	0	0	0
T35	185046	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T44	0	1	0	0
T52	0	9	0	0
T53	0	1	0	0
T56	0	3	0	0
T63	17862	0	0	0
T64	27476	1	0	0
T67	0	2	0	0
T69	0	2	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6540	0	0
T9	3587480	0	0	0
T11	193232	1454	0	0
T12	0	1454	0	0
T13	0	733	0	0
T41	0	1494	0	0
T42	0	1405	0	0
T43	6164	0	0	0
T44	1509072	0	0	0
T45	207132	0	0	0
T46	4716	0	0	0
T47	465360	0	0	0
T48	54692	0	0	0
T49	79464	0	0	0
T50	38744	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5460	0	0
T9	3587480	0	0	0
T11	193232	1214	0	0
T12	0	1214	0	0
T13	0	613	0	0
T41	0	1254	0	0
T42	0	1165	0	0
T43	6164	0	0	0
T44	1509072	0	0	0
T45	207132	0	0	0
T46	4716	0	0	0
T47	465360	0	0	0
T48	54692	0	0	0
T49	79464	0	0	0
T50	38744	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	92096	91864	0	0
T2	372520	372152	0	0
T3	216280	215884	0	0
T4	2574704	2572764	0	0
T5	1046928	1046892	0	0
T6	396812	396224	0	0
T20	450756	450356	0	0
T27	772828	772588	0	0
T28	143496	143148	0	0
T29	481856	481636	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	92096	91864	0	0
T2	372520	372152	0	0
T3	216280	215884	0	0
T4	2574704	2572764	0	0
T5	1046928	1046892	0	0
T6	396812	396224	0	0
T20	450756	450356	0	0
T27	772828	772588	0	0
T28	143496	143148	0	0
T29	481856	481636	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T29
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T29

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T29,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T29
1	0	1	Covered	T27,T5,T23
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T3,T4,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T23
0	1	Covered	T23,T35,T52
1	0	Covered	T23,T52,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T52,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T23
1	0	Not Covered
1	1	Covered	T23,T35,T52

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T29,T5
1	Covered	T4,T23,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T20,T23
1	Covered	T4,T29,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T29,T5
1	Covered	T25,T14,T63

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T29,T5
1	Covered	T20,T23,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T29,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T29,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T29,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T29,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T29,T5
Phase1St	198	Covered	T4,T29,T5
Phase2St	215	Covered	T4,T29,T5
Phase3St	233	Covered	T4,T29,T5
TerminalSt	249	Covered	T4,T29,T5
TimeoutSt	159	Covered	T3,T4,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T29,T5
IdleSt->TimeoutSt	159	Covered	T3,T4,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T80,T81
Phase0St->Phase1St	198	Covered	T4,T29,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T36,T10,T59
Phase1St->Phase2St	215	Covered	T4,T29,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T37,T38,T54
Phase2St->Phase3St	233	Covered	T4,T29,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T39,T32,T40
Phase3St->TerminalSt	249	Covered	T4,T29,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T23,T24
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T23
TimeoutSt->Phase0St	172	Covered	T23,T35,T52

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T29,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T35,T52
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T80,T81
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T29,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T29,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T10,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T29,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T29,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T38,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T29,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T29,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T32,T40
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T29,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T29,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T23,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T29,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667945598	317	0	0
CheckAccumTrig0_A	667945598	906	0	0
CheckAccumTrig1_A	667945598	60	0	0
CheckClr_A	667945598	462	0	0
CheckEn_A	667757859	222013629	0	0
CheckPhase0_A	667945598	1048	0	0
CheckPhase1_A	667945598	1029	0	0
CheckPhase2_A	667945598	1006	0	0
CheckPhase3_A	667945598	980	0	0
CheckTimeout0_A	667945598	1784	0	0
CheckTimeoutSt1_A	667945598	177219	0	0
CheckTimeoutSt2_A	667945598	1626	0	0
CheckTimeoutStTrig_A	667945598	95	0	0
ErrorStAllEscAsserted_A	667945598	1622	0	0
ErrorStIsTerminal_A	667945598	1352	0	0
EscStateOut_A	667756087	667680786	0	0
u_state_regs_A	667945598	667755110	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	317	0	0
T9	896870	0	0	0
T11	48308	61	0	0
T12	0	86	0	0
T13	0	32	0	0
T41	0	70	0	0
T42	0	68	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	906	0	0
T4	643676	5	0	0
T5	261732	1	0	0
T6	99203	0	0	0
T7	824473	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	112689	1	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	7	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	60	0	0
T8	134975	0	0	0
T10	0	1	0	0
T14	81745	0	0	0
T15	495247	0	0	0
T16	373686	0	0	0
T23	843939	1	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T33	0	2	0	0
T35	92523	0	0	0
T40	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	4	0	0
T63	8931	0	0	0
T64	13738	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	462	0	0
T4	643676	4	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	5	0	0
T24	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T51	0	1	0	0
T52	0	11	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667757859	222013629	0	0
T1	23024	22965	0	0
T2	93130	93037	0	0
T3	54070	8836	0	0
T4	643676	243968	0	0
T5	261732	2079	0	0
T6	99203	3404	0	0
T20	112689	2570	0	0
T27	193207	192142	0	0
T28	35874	35786	0	0
T29	120464	13145	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1048	0	0
T4	643676	5	0	0
T5	261732	1	0	0
T6	99203	0	0	0
T7	824473	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	112689	1	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	10	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1029	0	0
T4	643676	5	0	0
T5	261732	1	0	0
T6	99203	0	0	0
T7	824473	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	112689	1	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	10	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1006	0	0
T4	643676	5	0	0
T5	261732	1	0	0
T6	99203	0	0	0
T7	824473	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	112689	1	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	10	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	980	0	0
T4	643676	5	0	0
T5	261732	1	0	0
T6	99203	0	0	0
T7	824473	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	112689	1	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	10	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1784	0	0
T3	54070	5	0	0
T4	643676	9	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T15	0	1	0	0
T16	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	4	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	2	0	0
T51	0	2	0	0
T52	0	21	0	0
T70	0	5	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	177219	0	0
T3	54070	755	0	0
T4	643676	967	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T15	0	134	0	0
T16	0	218	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	333	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	124	0	0
T51	0	248	0	0
T52	0	3472	0	0
T70	0	257	0	0
T71	0	95	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1626	0	0
T3	54070	5	0	0
T4	643676	9	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T15	0	1	0	0
T16	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	1	0	0
T51	0	2	0	0
T52	0	11	0	0
T70	0	5	0	0
T71	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	95	0	0
T8	134975	0	0	0
T10	0	2	0	0
T14	81745	0	0	0
T15	495247	0	0	0
T16	373686	0	0	0
T23	843939	2	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T35	92523	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T52	0	9	0	0
T53	0	1	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1622	0	0
T9	896870	0	0	0
T11	48308	344	0	0
T12	0	388	0	0
T13	0	159	0	0
T41	0	370	0	0
T42	0	361	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1352	0	0
T9	896870	0	0	0
T11	48308	284	0	0
T12	0	328	0	0
T13	0	129	0	0
T41	0	310	0	0
T42	0	301	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667756087	667680786	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	667755110	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T28

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T27,T23,T24
1	1	0	Covered	T4,T23,T25
1	1	1	Covered	T2,T3,T28

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T28
0	1	Covered	T2,T28,T23
1	0	Covered	T15,T69,T77

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T69,T77

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T28
1	0	Not Covered
1	1	Covered	T2,T28,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T28
1	Covered	T7,T24,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T28
1	Covered	T23,T25,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T28,T7
1	Covered	T2,T28,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T28,T7
1	Covered	T4,T28,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T28,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T28,T23,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T28,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T28
Phase1St	198	Covered	T2,T4,T28
Phase2St	215	Covered	T2,T4,T28
Phase3St	233	Covered	T2,T4,T28
TerminalSt	249	Covered	T2,T4,T28
TimeoutSt	159	Covered	T2,T3,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T28
IdleSt->TimeoutSt	159	Covered	T2,T3,T28
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T61,T82
Phase0St->Phase1St	198	Covered	T2,T4,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T35,T18,T36
Phase1St->Phase2St	215	Covered	T2,T4,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T40,T83,T84
Phase2St->Phase3St	233	Covered	T2,T4,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T85,T83,T86
Phase3St->TerminalSt	249	Covered	T2,T4,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T28
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T35
TimeoutSt->Phase0St	172	Covered	T2,T28,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T28
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T28,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T35
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T82,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T28
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T18,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T28
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T83,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T85,T83,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667945598	285	0	0
CheckAccumTrig0_A	667945598	504	0	0
CheckAccumTrig1_A	667945598	20	0	0
CheckClr_A	667945598	224	0	0
CheckEn_A	667757859	314714708	0	0
CheckPhase0_A	667945598	579	0	0
CheckPhase1_A	667945598	571	0	0
CheckPhase2_A	667945598	566	0	0
CheckPhase3_A	667945598	559	0	0
CheckTimeout0_A	667945598	1505	0	0
CheckTimeoutSt1_A	667945598	155872	0	0
CheckTimeoutSt2_A	667945598	1418	0	0
CheckTimeoutStTrig_A	667945598	64	0	0
ErrorStAllEscAsserted_A	667945598	1656	0	0
ErrorStIsTerminal_A	667945598	1386	0	0
EscStateOut_A	667756087	667680786	0	0
u_state_regs_A	667945598	667755110	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	285	0	0
T9	896870	0	0	0
T11	48308	75	0	0
T12	0	41	0	0
T13	0	48	0	0
T41	0	51	0	0
T42	0	70	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	504	0	0
T2	93130	4	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	5	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	20	0	0
T8	134975	0	0	0
T15	495247	2	0	0
T16	373686	0	0	0
T17	192313	0	0	0
T18	783270	0	0	0
T19	431210	0	0	0
T30	0	1	0	0
T35	92523	0	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T65	38729	0	0	0
T69	0	2	0	0
T77	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	224	0	0
T2	93130	5	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	3	0	0
T36	0	5	0	0
T67	0	4	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667757859	314714708	0	0
T1	23024	22965	0	0
T2	93130	11405	0	0
T3	54070	2723	0	0
T4	643676	620397	0	0
T5	261732	260193	0	0
T6	99203	3421	0	0
T20	112689	112588	0	0
T27	193207	192084	0	0
T28	35874	2336	0	0
T29	120464	120408	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	579	0	0
T2	93130	6	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	4	0	0
T29	120464	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	571	0	0
T2	93130	6	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	4	0	0
T29	120464	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	566	0	0
T2	93130	6	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	4	0	0
T29	120464	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	559	0	0
T2	93130	6	0	0
T3	54070	0	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	4	0	0
T29	120464	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1505	0	0
T2	93130	5	0	0
T3	54070	3	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	1	0	0
T27	193207	0	0	0
T28	35874	1	0	0
T29	120464	0	0	0
T35	0	1	0	0
T67	0	14	0	0
T70	0	1	0	0
T71	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	155872	0	0
T2	93130	355	0	0
T3	54070	466	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T14	0	187	0	0
T15	0	10	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	86	0	0
T27	193207	0	0	0
T28	35874	324	0	0
T29	120464	0	0	0
T35	0	99	0	0
T67	0	2069	0	0
T70	0	42	0	0
T71	0	470	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1418	0	0
T2	93130	3	0	0
T3	54070	3	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T53	0	1	0	0
T67	0	12	0	0
T69	0	4	0	0
T70	0	1	0	0
T71	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	64	0	0
T2	93130	2	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T10	0	2	0	0
T14	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	1	0	0
T27	193207	0	0	0
T28	35874	1	0	0
T29	120464	0	0	0
T67	0	2	0	0
T69	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1656	0	0
T9	896870	0	0	0
T11	48308	371	0	0
T12	0	389	0	0
T13	0	169	0	0
T41	0	385	0	0
T42	0	342	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1386	0	0
T9	896870	0	0	0
T11	48308	311	0	0
T12	0	329	0	0
T13	0	139	0	0
T41	0	325	0	0
T42	0	282	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667756087	667680786	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	667755110	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T27
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T27

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T27,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T27,T21,T7
1	1	0	Covered	T4,T28,T23
1	1	1	Covered	T3,T23,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T14
0	1	Covered	T23,T14,T16
1	0	Covered	T15,T67,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T23,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T67,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T23,T14
1	0	Not Covered
1	1	Covered	T23,T14,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T27,T7
1	Covered	T21,T35,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T7
1	Covered	T27,T23,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T27,T21
1	Covered	T7,T23,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T27,T21,T7
1	Covered	T2,T23,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T21,T23,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T27,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T27,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T27,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T27,T21
Phase1St	198	Covered	T2,T27,T21
Phase2St	215	Covered	T2,T27,T21
Phase3St	233	Covered	T2,T27,T21
TerminalSt	249	Covered	T2,T27,T21
TimeoutSt	159	Covered	T3,T23,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T27,T21
IdleSt->TimeoutSt	159	Covered	T3,T23,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T10,T59,T94
Phase0St->Phase1St	198	Covered	T2,T27,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T66,T36,T44
Phase1St->Phase2St	215	Covered	T2,T27,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T44,T95
Phase2St->Phase3St	233	Covered	T2,T27,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T19,T96,T97
Phase3St->TerminalSt	249	Covered	T2,T27,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T23,T8,T35
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T23,T51
TimeoutSt->Phase0St	172	Covered	T23,T14,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T14,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T51
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T10,T59,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T27,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T27,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T66,T36,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T27,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T27,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T44,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T27,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T27,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T96,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T27,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T27,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T8,T35
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T27,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667945598	302	0	0
CheckAccumTrig0_A	667945598	541	0	0
CheckAccumTrig1_A	667945598	22	0	0
CheckClr_A	667945598	264	0	0
CheckEn_A	667757859	298626797	0	0
CheckPhase0_A	667945598	628	0	0
CheckPhase1_A	667945598	616	0	0
CheckPhase2_A	667945598	599	0	0
CheckPhase3_A	667945598	588	0	0
CheckTimeout0_A	667945598	1193	0	0
CheckTimeoutSt1_A	667945598	123217	0	0
CheckTimeoutSt2_A	667945598	1088	0	0
CheckTimeoutStTrig_A	667945598	81	0	0
ErrorStAllEscAsserted_A	667945598	1608	0	0
ErrorStIsTerminal_A	667945598	1338	0	0
EscStateOut_A	667756087	667680786	0	0
u_state_regs_A	667945598	667755110	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	302	0	0
T9	896870	0	0	0
T11	48308	61	0	0
T12	0	60	0	0
T13	0	27	0	0
T41	0	84	0	0
T42	0	70	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	541	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	112689	0	0	0
T21	4004	1	0	0
T23	0	4	0	0
T27	193207	1	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	3	0	0
T64	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	22	0	0
T8	134975	0	0	0
T15	495247	1	0	0
T16	373686	0	0	0
T17	192313	0	0	0
T18	783270	0	0	0
T19	431210	0	0	0
T31	0	1	0	0
T35	92523	0	0	0
T44	0	1	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T65	38729	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T82	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	264	0	0
T8	134975	1	0	0
T14	81745	0	0	0
T15	495247	0	0	0
T16	373686	0	0	0
T19	0	3	0	0
T23	843939	3	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T35	92523	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T51	0	3	0	0
T52	0	1	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T66	0	1	0	0
T67	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667757859	298626797	0	0
T1	23024	22965	0	0
T2	93130	3101	0	0
T3	54070	2742	0	0
T4	643676	609472	0	0
T5	261732	261723	0	0
T6	99203	99054	0	0
T20	112689	112588	0	0
T27	193207	5177	0	0
T28	35874	35786	0	0
T29	120464	120408	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	628	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	1	0	0
T23	0	6	0	0
T27	193207	1	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T64	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	616	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	1	0	0
T23	0	6	0	0
T27	193207	1	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T64	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	599	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	1	0	0
T23	0	5	0	0
T27	193207	1	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T64	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	588	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	1	0	0
T23	0	5	0	0
T27	193207	1	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T64	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1193	0	0
T3	54070	4	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	4	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T36	0	4	0	0
T51	0	1	0	0
T67	0	10	0	0
T69	0	6	0	0
T70	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	123217	0	0
T3	54070	658	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T14	0	229	0	0
T16	0	26	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	2048	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T36	0	246	0	0
T51	0	202	0	0
T67	0	1184	0	0
T69	0	412	0	0
T70	0	250	0	0
T72	0	199	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1088	0	0
T3	54070	4	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	2	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T33	0	10	0	0
T36	0	4	0	0
T37	0	1	0	0
T51	0	1	0	0
T67	0	6	0	0
T69	0	6	0	0
T70	0	5	0	0
T72	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	81	0	0
T8	134975	0	0	0
T10	0	1	0	0
T14	81745	1	0	0
T15	495247	0	0	0
T16	373686	1	0	0
T23	843939	2	0	0
T24	234082	0	0	0
T25	44047	0	0	0
T35	92523	0	0	0
T56	0	1	0	0
T63	8931	0	0	0
T64	13738	0	0	0
T67	0	2	0	0
T75	0	10	0	0
T95	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1608	0	0
T9	896870	0	0	0
T11	48308	354	0	0
T12	0	337	0	0
T13	0	197	0	0
T41	0	391	0	0
T42	0	329	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1338	0	0
T9	896870	0	0	0
T11	48308	294	0	0
T12	0	277	0	0
T13	0	167	0	0
T41	0	331	0	0
T42	0	269	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667756087	667680786	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	667755110	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T28

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T23

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T28
1	0	1	Covered	T1,T24,T8
1	1	0	Covered	T3,T4,T28
1	1	1	Covered	T2,T4,T28

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T28
0	1	Covered	T2,T28,T23
1	0	Covered	T4,T16,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T16,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T28
1	0	Covered	T30,T31
1	1	Covered	T2,T28,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T28
1	Covered	T4,T16,T104

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T28
1	Covered	T4,T23,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T28,T23
1	Covered	T2,T23,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T23
1	Covered	T28,T23,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T28,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T28

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T28
Phase1St	198	Covered	T2,T4,T28
Phase2St	215	Covered	T2,T4,T28
Phase3St	233	Covered	T2,T4,T28
TerminalSt	249	Covered	T2,T4,T28
TimeoutSt	159	Covered	T2,T4,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T23,T25
IdleSt->TimeoutSt	159	Covered	T2,T4,T28
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T33,T34
Phase0St->Phase1St	198	Covered	T2,T4,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T69,T105,T106
Phase1St->Phase2St	215	Covered	T2,T4,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T37,T107,T96
Phase2St->Phase3St	233	Covered	T2,T4,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T58,T108,T109
Phase3St->TerminalSt	249	Covered	T2,T4,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T28,T23
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T28,T23
TimeoutSt->Phase0St	172	Covered	T2,T4,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T23
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T28,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T28
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T69,T105,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T28
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T107,T96
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T58,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T28,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667945598	283	0	0
CheckAccumTrig0_A	667945598	536	0	0
CheckAccumTrig1_A	667945598	31	0	0
CheckClr_A	667945598	265	0	0
CheckEn_A	667757859	303604885	0	0
CheckPhase0_A	667945598	628	0	0
CheckPhase1_A	667945598	618	0	0
CheckPhase2_A	667945598	612	0	0
CheckPhase3_A	667945598	600	0	0
CheckTimeout0_A	667945598	1153	0	0
CheckTimeoutSt1_A	667945598	108104	0	0
CheckTimeoutSt2_A	667945598	1042	0	0
CheckTimeoutStTrig_A	667945598	78	0	0
ErrorStAllEscAsserted_A	667945598	1654	0	0
ErrorStIsTerminal_A	667945598	1384	0	0
EscStateOut_A	667756087	667680786	0	0
u_state_regs_A	667945598	667755110	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	283	0	0
T9	896870	0	0	0
T11	48308	62	0	0
T12	0	61	0	0
T13	0	49	0	0
T41	0	62	0	0
T42	0	49	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	536	0	0
T4	643676	2	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	3	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T35	0	1	0	0
T51	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	31	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T27	193207	0	0	0
T28	35874	0	0	0
T29	120464	0	0	0
T30	0	1	0	0
T44	0	2	0	0
T51	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T61	0	5	0	0
T62	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	265	0	0
T4	643676	1	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T19	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	9	0	0
T27	193207	0	0	0
T28	35874	2	0	0
T29	120464	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T51	0	4	0	0
T67	0	7	0	0
T68	0	3	0	0
T69	0	8	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667757859	303604885	0	0
T1	23024	2091	0	0
T2	93130	3042	0	0
T3	54070	53970	0	0
T4	643676	367460	0	0
T5	261732	261723	0	0
T6	99203	3410	0	0
T20	112689	112588	0	0
T27	193207	193146	0	0
T28	35874	2332	0	0
T29	120464	120408	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	628	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	3	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	11	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	1	0	0
T64	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	618	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	3	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	11	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	1	0	0
T64	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	612	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	3	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	11	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	1	0	0
T64	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	600	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	3	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	11	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T35	0	1	0	0
T64	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1153	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	9	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T16	0	2	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	13	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	4	0	0
T29	120464	0	0	0
T35	0	3	0	0
T51	0	1	0	0
T64	0	1	0	0
T71	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	108104	0	0
T2	93130	732	0	0
T3	54070	0	0	0
T4	643676	975	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T16	0	61	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	1797	0	0
T25	0	62	0	0
T27	193207	0	0	0
T28	35874	347	0	0
T29	120464	0	0	0
T35	0	387	0	0
T51	0	1	0	0
T64	0	254	0	0
T71	0	329	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1042	0	0
T4	643676	8	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T7	824473	0	0	0
T16	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T22	43898	0	0	0
T23	0	5	0	0
T25	0	1	0	0
T27	193207	0	0	0
T28	35874	1	0	0
T29	120464	0	0	0
T35	0	3	0	0
T39	0	1	0	0
T67	0	7	0	0
T71	0	4	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	78	0	0
T2	93130	1	0	0
T3	54070	0	0	0
T4	643676	0	0	0
T5	261732	0	0	0
T6	99203	0	0	0
T10	0	1	0	0
T20	112689	0	0	0
T21	4004	0	0	0
T23	0	8	0	0
T27	193207	0	0	0
T28	35874	3	0	0
T29	120464	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	3	0	0
T64	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1654	0	0
T9	896870	0	0	0
T11	48308	385	0	0
T12	0	340	0	0
T13	0	208	0	0
T41	0	348	0	0
T42	0	373	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	1384	0	0
T9	896870	0	0	0
T11	48308	325	0	0
T12	0	280	0	0
T13	0	178	0	0
T41	0	288	0	0
T42	0	313	0	0
T43	1541	0	0	0
T44	377268	0	0	0
T45	51783	0	0	0
T46	1179	0	0	0
T47	116340	0	0	0
T48	13673	0	0	0
T49	19866	0	0	0
T50	9686	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667756087	667680786	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667945598	667755110	0	0
T1	23024	22966	0	0
T2	93130	93038	0	0
T3	54070	53971	0	0
T4	643676	643191	0	0
T5	261732	261723	0	0
T6	99203	99056	0	0
T20	112689	112589	0	0
T27	193207	193147	0	0
T28	35874	35787	0	0
T29	120464	120409	0	0