Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63922268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30901741

1

T1

99850

T2

275

T3

1553

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14325033	1			T1	38979		T2	108		T3	644
values[0x0]	39333686	1			T1	137812		T2	452		T3	1993
values[0x1]	41165290	1			T1	137632		T2	386		T3	1935

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54687617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40136392

1

T1

125824

T2

362

T3

1940

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	308934	1			T1	1142		T2	1		T3	18
valid_sources[0x01]	310220	1			T1	1260		T2	5		T3	10
valid_sources[0x02]	330592	1			T1	1301		T2	5		T3	17
valid_sources[0x03]	638459	1			T1	1217		T2	6		T3	14
valid_sources[0x04]	554730	1			T1	1157		T2	2		T3	19
valid_sources[0x05]	322625	1			T1	1241		T2	4		T3	20
valid_sources[0x06]	312858	1			T1	1186		T2	5		T3	14
valid_sources[0x07]	322677	1			T1	1240		T2	3		T3	12
valid_sources[0x08]	315854	1			T1	1223		T2	4		T3	19
valid_sources[0x09]	319144	1			T1	1284		T2	2		T3	25
valid_sources[0x0a]	741912	1			T1	1185		T2	5		T3	22
valid_sources[0x0b]	316591	1			T1	1195		T2	6		T3	16
valid_sources[0x0c]	315853	1			T1	1236		T2	4		T3	23
valid_sources[0x0d]	307467	1			T1	1261		T2	3		T3	9
valid_sources[0x0e]	323889	1			T1	1196		T2	3		T3	21
valid_sources[0x0f]	344374	1			T1	1289		T2	4		T3	19
valid_sources[0x10]	315684	1			T1	1292		T2	8		T3	17
valid_sources[0x11]	985757	1			T1	1260		T2	1		T3	17
valid_sources[0x12]	309872	1			T1	1254		T2	3		T3	13
valid_sources[0x13]	317082	1			T1	1202		T2	5		T3	19
valid_sources[0x14]	316177	1			T1	1238		T2	4		T3	22
valid_sources[0x15]	324616	1			T1	1207		T2	1		T3	17
valid_sources[0x16]	319515	1			T1	1254		T2	5		T3	15
valid_sources[0x17]	315171	1			T1	1307		T2	2		T3	15
valid_sources[0x18]	722436	1			T1	1157		T2	4		T3	13
valid_sources[0x19]	306258	1			T1	1216		T2	6		T3	20
valid_sources[0x1a]	305780	1			T1	1167		T2	5		T3	13
valid_sources[0x1b]	309260	1			T1	1289		T2	2		T3	18
valid_sources[0x1c]	312799	1			T1	1239		T2	4		T3	26
valid_sources[0x1d]	306090	1			T1	1255		T2	2		T3	19
valid_sources[0x1e]	320424	1			T1	1204		T2	3		T3	20
valid_sources[0x1f]	315738	1			T1	1136		T2	6		T3	17
valid_sources[0x20]	307323	1			T1	1287		T2	4		T3	13
valid_sources[0x21]	315504	1			T1	1371		T2	4		T3	8
valid_sources[0x22]	533449	1			T1	1257		T2	5		T3	26
valid_sources[0x23]	311745	1			T1	1258		T2	3		T3	18
valid_sources[0x24]	597488	1			T1	1255		T2	2		T3	17
valid_sources[0x25]	314517	1			T1	1208		T2	5		T3	14
valid_sources[0x26]	311303	1			T1	1198		T2	2		T3	29
valid_sources[0x27]	312872	1			T1	1298		T2	6		T3	27
valid_sources[0x28]	320934	1			T1	1175		T2	6		T3	15
valid_sources[0x29]	316230	1			T1	1292		T2	2		T3	17
valid_sources[0x2a]	311354	1			T1	1191		T2	5		T3	15
valid_sources[0x2b]	326906	1			T1	1196		T2	4		T3	20
valid_sources[0x2c]	316385	1			T1	1214		T2	8		T3	18
valid_sources[0x2d]	311432	1			T1	1276		T2	3		T3	18
valid_sources[0x2e]	310755	1			T1	1175		T2	4		T3	22
valid_sources[0x2f]	723510	1			T1	1261		T2	2		T3	25
valid_sources[0x30]	307446	1			T1	1263		T2	4		T3	31
valid_sources[0x31]	322554	1			T1	1167		T2	2		T3	18
valid_sources[0x32]	311390	1			T1	1148		T3	14		T7	1002
valid_sources[0x33]	314998	1			T1	1282		T3	13		T7	1026
valid_sources[0x34]	309921	1			T1	1229		T2	2		T3	15
valid_sources[0x35]	312235	1			T1	1227		T2	3		T3	19
valid_sources[0x36]	343347	1			T1	1198		T2	2		T3	20
valid_sources[0x37]	316817	1			T1	1238		T2	1		T3	16
valid_sources[0x38]	355352	1			T1	1195		T2	4		T3	14
valid_sources[0x39]	315663	1			T1	1185		T2	4		T3	30
valid_sources[0x3a]	324216	1			T1	1330		T2	2		T3	22
valid_sources[0x3b]	327724	1			T1	1185		T2	2		T3	23
valid_sources[0x3c]	312275	1			T1	1207		T2	2		T3	16
valid_sources[0x3d]	310667	1			T1	1234		T3	22		T7	1012
valid_sources[0x3e]	319905	1			T1	1216		T2	4		T3	20
valid_sources[0x3f]	314649	1			T1	1104		T2	3		T3	20
valid_sources[0x40]	325248	1			T1	1196		T2	4		T3	17
valid_sources[0x41]	654579	1			T1	1253		T2	6		T3	28
valid_sources[0x42]	311832	1			T1	1181		T2	3		T3	25
valid_sources[0x43]	316615	1			T1	1242		T2	3		T3	18
valid_sources[0x44]	314129	1			T1	1247		T2	8		T3	17
valid_sources[0x45]	315995	1			T1	1174		T2	3		T3	17
valid_sources[0x46]	328044	1			T1	1202		T2	3		T3	18
valid_sources[0x47]	307687	1			T1	1211		T2	4		T3	20
valid_sources[0x48]	311829	1			T1	1240		T2	1		T3	18
valid_sources[0x49]	753582	1			T1	1270		T2	4		T3	21
valid_sources[0x4a]	691983	1			T1	1201		T2	3		T3	14
valid_sources[0x4b]	1158675	1			T1	1177		T2	3		T3	19
valid_sources[0x4c]	317634	1			T1	1120		T2	1		T3	17
valid_sources[0x4d]	533843	1			T1	1328		T2	8		T3	20
valid_sources[0x4e]	304783	1			T1	1156		T2	2		T3	17
valid_sources[0x4f]	309263	1			T1	1206		T2	4		T3	13
valid_sources[0x50]	312332	1			T1	1218		T2	4		T3	26
valid_sources[0x51]	316341	1			T1	1316		T2	7		T3	14
valid_sources[0x52]	309286	1			T1	1323		T2	4		T3	16
valid_sources[0x53]	315401	1			T1	1169		T2	1		T3	25
valid_sources[0x54]	307850	1			T1	1150		T2	6		T3	15
valid_sources[0x55]	312549	1			T1	1185		T2	4		T3	19
valid_sources[0x56]	311426	1			T1	1292		T2	3		T3	12
valid_sources[0x57]	328850	1			T1	1287		T2	2		T3	16
valid_sources[0x58]	310136	1			T1	1155		T2	6		T3	19
valid_sources[0x59]	305459	1			T1	1265		T2	7		T3	18
valid_sources[0x5a]	318172	1			T1	1152		T2	4		T3	29
valid_sources[0x5b]	560752	1			T1	1275		T2	5		T3	18
valid_sources[0x5c]	312009	1			T1	1114		T2	2		T3	18
valid_sources[0x5d]	314898	1			T1	1206		T2	2		T3	14
valid_sources[0x5e]	309070	1			T1	1235		T2	5		T3	18
valid_sources[0x5f]	317464	1			T1	1231		T2	1		T3	18
valid_sources[0x60]	313010	1			T1	1189		T2	1		T3	17
valid_sources[0x61]	324392	1			T1	1236		T2	1		T3	23
valid_sources[0x62]	533165	1			T1	1278		T2	2		T3	28
valid_sources[0x63]	316408	1			T1	1268		T2	2		T3	17
valid_sources[0x64]	302817	1			T1	1298		T2	3		T3	21
valid_sources[0x65]	323463	1			T1	1221		T2	4		T3	10
valid_sources[0x66]	308893	1			T1	1250		T3	18		T7	1008
valid_sources[0x67]	309511	1			T1	1271		T2	4		T3	23
valid_sources[0x68]	315406	1			T1	1254		T2	6		T3	17
valid_sources[0x69]	303990	1			T1	1197		T2	5		T3	15
valid_sources[0x6a]	648496	1			T1	1221		T2	3		T3	14
valid_sources[0x6b]	307406	1			T1	1246		T2	6		T3	18
valid_sources[0x6c]	323494	1			T1	1174		T2	5		T3	14
valid_sources[0x6d]	316008	1			T1	1149		T2	2		T3	11
valid_sources[0x6e]	355750	1			T1	1163		T2	2		T3	10
valid_sources[0x6f]	340606	1			T1	1325		T2	5		T3	12
valid_sources[0x70]	310255	1			T1	1304		T2	1		T3	20
valid_sources[0x71]	326829	1			T1	1280		T2	4		T3	14
valid_sources[0x72]	315677	1			T1	1252		T2	5		T3	19
valid_sources[0x73]	318208	1			T1	1236		T2	4		T3	15
valid_sources[0x74]	323113	1			T1	1238		T2	4		T3	14
valid_sources[0x75]	964405	1			T1	1181		T2	3		T3	27
valid_sources[0x76]	616995	1			T1	1272		T2	3		T3	16
valid_sources[0x77]	589202	1			T1	1193		T2	2		T3	18
valid_sources[0x78]	310191	1			T1	1177		T2	7		T3	21
valid_sources[0x79]	309608	1			T1	1267		T2	6		T3	21
valid_sources[0x7a]	320405	1			T1	1260		T2	3		T3	18
valid_sources[0x7b]	427149	1			T1	1208		T2	6		T3	16
valid_sources[0x7c]	319761	1			T1	1230		T2	1		T3	22
valid_sources[0x7d]	312673	1			T1	1203		T2	8		T3	11
valid_sources[0x7e]	320729	1			T1	1216		T2	4		T3	24
valid_sources[0x7f]	314215	1			T1	1223		T2	6		T3	20
valid_sources[0x80]	312466	1			T1	1326		T2	3		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7108165

1

T1

19480

T2

47

T3

333

values[0x0]

all_enables

biggest_size

15030065

1

T1

51256

T2

159

T3

794

values[0x1]

all_enables

biggest_size

8763511

1

T1

29114

T2

69

T3

426