Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T204,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12193	0	0
DisabledNoTrigBkwd_A	2147483647	847991	0	0
DisabledNoTrigFwd_A	2147483647	1498576127	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12193	0	0
T88	282674	0	0	0
T102	891277	0	0	0
T116	277366	0	0	0
T184	0	398	0	0
T203	2862	538	0	0
T204	1580	792	0	0
T205	0	533	0	0
T206	0	839	0	0
T207	0	656	0	0
T208	0	331	0	0
T209	0	702	0	0
T210	0	588	0	0
T211	1257	487	0	0
T212	966	230	0	0
T213	0	935	0	0
T214	0	763	0	0
T215	0	524	0	0
T216	0	744	0	0
T217	0	264	0	0
T218	0	923	0	0
T219	0	852	0	0
T220	0	156	0	0
T221	0	938	0	0
T222	4181	0	0	0
T223	282227	0	0	0
T224	27199	0	0	0
T225	37119	0	0	0
T226	554149	0	0	0
T227	4903	0	0	0
T228	193470	0	0	0
T229	637019	0	0	0
T230	98607	0	0	0
T231	1610	0	0	0
T232	44225	0	0	0
T233	668424	0	0	0
T234	12355	0	0	0
T235	230079	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	847991	0	0
T1	548702	703	0	0
T2	14716	0	0	0
T3	1042290	4	0	0
T4	302442	16	0	0
T5	725844	3141	0	0
T6	55600	0	0	0
T7	1181600	2325	0	0
T8	2709408	8	0	0
T12	0	97	0	0
T14	0	5132	0	0
T15	261084	34	0	0
T16	31112	4	0	0
T17	15800	0	0	0
T21	444602	1223	0	0
T26	93831	3	0	0
T42	0	486	0	0
T43	0	590	0	0
T44	0	6	0	0
T45	0	78	0	0
T46	0	130	0	0
T47	0	14	0	0
T48	0	44	0	0
T49	0	69	0	0
T50	31958	0	0	0
T51	37325	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1498576127	0	0
T1	1097404	824461	0	0
T2	29432	22279	0	0
T3	2084580	706006	0	0
T4	403256	2079071	0	0
T5	725844	370629	0	0
T7	1181600	853431	0	0
T8	3612544	1443635	0	0
T15	261084	197612	0	0
T16	31112	25856	0	0
T17	15800	4802	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T205,T207
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	689880002	5768	0	0
DisabledNoTrigBkwd_A	689880002	211786	0	0
DisabledNoTrigFwd_A	689880002	396568778	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	5768	0	0
T88	282674	0	0	0
T102	891277	0	0	0
T116	277366	0	0	0
T184	0	398	0	0
T203	2862	538	0	0
T205	0	533	0	0
T207	0	656	0	0
T210	0	588	0	0
T213	0	935	0	0
T215	0	524	0	0
T216	0	744	0	0
T219	0	852	0	0
T222	4181	0	0	0
T223	282227	0	0	0
T224	27199	0	0	0
T225	37119	0	0	0
T226	554149	0	0	0
T227	4903	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	211786	0	0
T4	100814	16	0	0
T5	181461	6	0	0
T6	27800	0	0	0
T7	295400	1905	0	0
T8	903136	0	0	0
T12	0	97	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	488	0	0
T26	0	3	0	0
T42	0	281	0	0
T43	0	587	0	0
T44	0	1	0	0
T45	0	44	0	0
T50	15979	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	396568778	0	0
T1	274351	274343	0	0
T2	7358	5578	0	0
T3	521145	365063	0	0
T4	100814	48947	0	0
T5	181461	180720	0	0
T7	295400	173205	0	0
T8	903136	859709	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T7,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T218,T221
1	1	Covered	T8,T7,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T7,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	689880002	2348	0	0
DisabledNoTrigBkwd_A	689880002	216881	0	0
DisabledNoTrigFwd_A	689880002	382775565	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	2348	0	0
T211	1257	487	0	0
T212	966	0	0	0
T218	0	923	0	0
T221	0	938	0	0
T228	193470	0	0	0
T229	637019	0	0	0
T230	98607	0	0	0
T231	1610	0	0	0
T232	44225	0	0	0
T233	668424	0	0	0
T234	12355	0	0	0
T235	230079	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	216881	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	7	0	0
T15	65271	34	0	0
T16	7778	3	0	0
T17	3950	0	0	0
T21	222301	53	0	0
T26	93831	0	0	0
T43	0	3	0	0
T45	0	8	0	0
T46	0	19	0	0
T47	0	9	0	0
T48	0	44	0	0
T49	0	69	0	0
T50	15979	0	0	0
T51	37325	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	382775565	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	91953	0	0
T4	100814	990576	0	0
T5	181461	181451	0	0
T7	295400	293748	0	0
T8	903136	143423	0	0
T15	65271	2054	0	0
T16	7778	6051	0	0
T17	3950	586	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T206,T208
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	689880002	3158	0	0
DisabledNoTrigBkwd_A	689880002	198000	0	0
DisabledNoTrigFwd_A	689880002	357374568	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	3158	0	0
T109	538916	0	0	0
T113	45750	0	0	0
T204	1580	792	0	0
T206	0	839	0	0
T208	0	331	0	0
T209	0	702	0	0
T212	0	230	0	0
T217	0	264	0	0
T236	15509	0	0	0
T237	16306	0	0	0
T238	9075	0	0	0
T239	167273	0	0	0
T240	56100	0	0	0
T241	102926	0	0	0
T242	171618	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	198000	0	0
T1	274351	17	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1364	0	0
T7	295400	193	0	0
T8	903136	0	0	0
T14	0	3144	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	387	0	0
T42	0	205	0	0
T44	0	5	0	0
T45	0	22	0	0
T46	0	109	0	0
T47	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	357374568	0	0
T1	274351	273230	0	0
T2	7358	2173	0	0
T3	521145	144226	0	0
T4	100814	48975	0	0
T5	181461	6181	0	0
T7	295400	210178	0	0
T8	903136	292985	0	0
T15	65271	65186	0	0
T16	7778	6051	0	0
T17	3950	590	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T220
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	689880002	919	0	0
DisabledNoTrigBkwd_A	689880002	221324	0	0
DisabledNoTrigFwd_A	689880002	361857216	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	919	0	0
T214	1509	763	0	0
T220	0	156	0	0
T243	207100	0	0	0
T244	10584	0	0	0
T245	716733	0	0	0
T246	117880	0	0	0
T247	31200	0	0	0
T248	46955	0	0	0
T249	17755	0	0	0
T250	68845	0	0	0
T251	102787	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	221324	0	0
T1	274351	686	0	0
T2	7358	0	0	0
T3	521145	4	0	0
T4	100814	0	0	0
T5	181461	1771	0	0
T7	295400	220	0	0
T8	903136	8	0	0
T14	0	1988	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	295	0	0
T45	0	4	0	0
T46	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	361857216	0	0
T1	274351	2545	0	0
T2	7358	7264	0	0
T3	521145	104764	0	0
T4	100814	990573	0	0
T5	181461	2277	0	0
T7	295400	176300	0	0
T8	903136	147518	0	0
T15	65271	65186	0	0
T16	7778	6051	0	0
T17	3950	3044	0	0