Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19,T20
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T16
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T7,T15,T16
1	1	1	Covered	T7,T15,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T15,T17
0	1	Covered	T7,T15,T21
1	0	Covered	T22,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T17
1	0	Covered	T25
1	1	Covered	T7,T15,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T7,T21,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T15,T16,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T7,T5,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T4,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T7,T15,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T7,T15,T17
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T7,T27,T28
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T7,T12,T29
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T14,T29,T30
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T7,T21,T22
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T7
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T7,T17,T21
TimeoutSt->Phase0St	172	Covered	T7,T15,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T17,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T12,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T21,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T16,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	888	0	0
CheckAccumTrig0_A	2147483647	2374	0	0
CheckAccumTrig1_A	2147483647	114	0	0
CheckClr_A	2147483647	1046	0	0
CheckEn_A	2147483647	1141448007	0	0
CheckPhase0_A	2147483647	2724	0	0
CheckPhase1_A	2147483647	2682	0	0
CheckPhase2_A	2147483647	2630	0	0
CheckPhase3_A	2147483647	2579	0	0
CheckTimeout0_A	2147483647	4912	0	0
CheckTimeoutSt1_A	2147483647	545246	0	0
CheckTimeoutSt2_A	2147483647	4509	0	0
CheckTimeoutStTrig_A	2147483647	282	0	0
ErrorStAllEscAsserted_A	2147483647	4888	0	0
ErrorStIsTerminal_A	2147483647	4048	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	888	0	0
T9	78720	111	0	0
T10	0	157	0	0
T11	0	283	0	0
T24	358020	0	0	0
T32	0	229	0	0
T33	0	108	0	0
T34	310316	0	0	0
T35	43360	0	0	0
T36	112860	0	0	0
T37	38856	0	0	0
T38	1018220	0	0	0
T39	59936	0	0	0
T40	1315292	0	0	0
T41	73072	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2374	0	0
T1	548702	6	0	0
T2	14716	0	0	0
T3	1042290	2	0	0
T4	302442	1	0	0
T5	725844	14	0	0
T6	55600	0	0	0
T7	1181600	13	0	0
T8	2709408	1	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	261084	0	0	0
T16	31112	2	0	0
T17	15800	0	0	0
T21	444602	15	0	0
T22	0	2	0	0
T26	93831	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	2	0	0
T50	31958	0	0	0
T51	37325	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114	0	0
T9	19680	0	0	0
T22	150999	1	0	0
T23	135816	1	0	0
T24	0	1	0	0
T29	319095	2	0	0
T30	158661	0	0	0
T31	0	1	0	0
T38	254555	1	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	6	0	0
T64	0	2	0	0
T65	0	3	0	0
T66	0	2	0	0
T67	184454	0	0	0
T68	38741	0	0	0
T69	18546	0	0	0
T70	959234	0	0	0
T71	545236	0	0	0
T72	1051376	0	0	0
T73	84170	0	0	0
T74	118222	0	0	0
T75	267460	0	0	0
T76	64876	0	0	0
T77	43836	0	0	0
T78	251305	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1046	0	0
T1	274351	0	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	544383	0	0	0
T6	83400	0	0	0
T7	886200	10	0	0
T8	903136	0	0	0
T12	0	6	0	0
T14	0	1	0	0
T15	195813	0	0	0
T16	31112	1	0	0
T17	15800	0	0	0
T21	666903	7	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	6	0	0
T26	281493	1	0	0
T29	0	7	0	0
T30	0	4	0	0
T38	0	4	0	0
T40	0	1	0	0
T42	321191	0	0	0
T45	0	1	0	0
T46	0	3	0	0
T49	0	1	0	0
T50	47937	0	0	0
T51	111975	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	83751	0	0	0
T82	75002	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1141448007	0	0
T1	1097404	562484	0	0
T2	29432	22277	0	0
T3	2084580	706005	0	0
T4	403256	2079069	0	0
T5	725844	195675	0	0
T7	1181600	809137	0	0
T8	3612544	1443634	0	0
T15	261084	197609	0	0
T16	31112	22222	0	0
T17	15800	4802	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2724	0	0
T1	548702	6	0	0
T2	14716	0	0	0
T3	1042290	2	0	0
T4	302442	1	0	0
T5	725844	14	0	0
T6	55600	0	0	0
T7	1181600	18	0	0
T8	2709408	1	0	0
T14	0	2	0	0
T15	261084	1	0	0
T16	31112	2	0	0
T17	15800	0	0	0
T21	444602	25	0	0
T26	93831	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	31958	0	0	0
T51	37325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2682	0	0
T1	548702	6	0	0
T2	14716	0	0	0
T3	1042290	2	0	0
T4	302442	1	0	0
T5	725844	14	0	0
T6	55600	0	0	0
T7	1181600	17	0	0
T8	2709408	1	0	0
T14	0	2	0	0
T15	261084	1	0	0
T16	31112	2	0	0
T17	15800	0	0	0
T21	444602	25	0	0
T26	93831	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	31958	0	0	0
T51	37325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2630	0	0
T1	548702	6	0	0
T2	14716	0	0	0
T3	1042290	2	0	0
T4	302442	1	0	0
T5	725844	14	0	0
T6	55600	0	0	0
T7	1181600	17	0	0
T8	2709408	1	0	0
T14	0	1	0	0
T15	261084	1	0	0
T16	31112	2	0	0
T17	15800	0	0	0
T21	444602	25	0	0
T26	93831	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	31958	0	0	0
T51	37325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T1	548702	6	0	0
T2	14716	0	0	0
T3	1042290	2	0	0
T4	302442	1	0	0
T5	725844	14	0	0
T6	55600	0	0	0
T7	1181600	16	0	0
T8	2709408	1	0	0
T14	0	1	0	0
T15	261084	1	0	0
T16	31112	2	0	0
T17	15800	0	0	0
T21	444602	24	0	0
T26	93831	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	31958	0	0	0
T51	37325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4912	0	0
T5	544383	0	0	0
T6	111200	0	0	0
T7	886200	10	0	0
T15	261084	1	0	0
T16	31112	0	0	0
T17	15800	1	0	0
T21	889204	45	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	4	0	0
T26	375324	0	0	0
T38	0	1	0	0
T43	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	63916	0	0	0
T51	149300	13	0	0
T68	0	1	0	0
T74	0	1	0	0
T75	0	56	0	0
T81	83751	14	0	0
T82	75002	11	0	0
T83	0	10	0	0
T84	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	545246	0	0
T5	544383	0	0	0
T6	111200	0	0	0
T7	886200	871	0	0
T15	261084	158	0	0
T16	31112	0	0	0
T17	15800	36	0	0
T21	889204	7625	0	0
T22	0	20	0	0
T23	0	30	0	0
T24	0	534	0	0
T26	375324	0	0	0
T38	0	42	0	0
T43	0	701	0	0
T45	0	34	0	0
T46	0	285	0	0
T48	0	83	0	0
T49	0	272	0	0
T50	63916	0	0	0
T51	149300	1976	0	0
T71	0	157	0	0
T74	0	174	0	0
T75	0	9194	0	0
T81	83751	2253	0	0
T82	75002	1880	0	0
T83	0	637	0	0
T84	0	1809	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4509	0	0
T5	362922	0	0	0
T6	111200	0	0	0
T7	590800	3	0	0
T15	130542	0	0	0
T16	15556	0	0	0
T17	11850	1	0	0
T21	889204	35	0	0
T23	0	1	0	0
T24	0	2	0	0
T26	375324	0	0	0
T29	0	4	0	0
T30	0	215	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	642382	0	0	0
T43	326748	2	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	63916	0	0	0
T51	149300	13	0	0
T71	0	2	0	0
T74	0	2	0	0
T75	0	121	0	0
T76	0	10	0	0
T81	167502	13	0	0
T82	150004	11	0	0
T83	40598	9	0	0
T84	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	282	0	0
T5	181461	0	0	0
T6	111200	0	0	0
T7	295400	6	0	0
T15	130542	1	0	0
T16	15556	0	0	0
T17	7900	0	0	0
T21	889204	6	0	0
T24	0	1	0	0
T26	375324	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	5	0	0
T30	0	5	0	0
T42	642382	0	0	0
T43	326748	1	0	0
T45	0	2	0	0
T50	63916	0	0	0
T51	149300	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T76	0	2	0	0
T80	0	2	0	0
T81	251253	1	0	0
T82	225006	0	0	0
T83	81196	1	0	0
T84	0	1	0	0
T85	0	3	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	6	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4888	0	0
T9	78720	668	0	0
T10	0	697	0	0
T11	0	1416	0	0
T24	358020	0	0	0
T32	0	1413	0	0
T33	0	694	0	0
T34	310316	0	0	0
T35	43360	0	0	0
T36	112860	0	0	0
T37	38856	0	0	0
T38	1018220	0	0	0
T39	59936	0	0	0
T40	1315292	0	0	0
T41	73072	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4048	0	0
T9	78720	548	0	0
T10	0	577	0	0
T11	0	1176	0	0
T24	358020	0	0	0
T32	0	1173	0	0
T33	0	574	0	0
T34	310316	0	0	0
T35	43360	0	0	0
T36	112860	0	0	0
T37	38856	0	0	0
T38	1018220	0	0	0
T39	59936	0	0	0
T40	1315292	0	0	0
T41	73072	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1097404	1097372	0	0
T2	29432	29056	0	0
T3	2084580	2084328	0	0
T4	403256	403232	0	0
T5	725844	725804	0	0
T7	1181600	1181544	0	0
T8	3612544	3612172	0	0
T15	261084	260744	0	0
T16	31112	30812	0	0
T17	15800	15408	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1097404	1097372	0	0
T2	29432	29056	0	0
T3	2084580	2084328	0	0
T4	403256	403232	0	0
T5	725844	725804	0	0
T7	1181600	1181544	0	0
T8	3612544	3612172	0	0
T15	261084	260744	0	0
T16	31112	30812	0	0
T17	15800	15408	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T17,T21
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T7,T15,T16
1	1	1	Covered	T7,T17,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T17,T21
0	1	Covered	T21,T81,T43
1	0	Covered	T38,T29,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T17,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T38,T29,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T21
1	0	Not Covered
1	1	Covered	T21,T81,T43

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T5
1	Covered	T7,T21,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T5
1	Covered	T21,T79,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T21
1	Covered	T7,T5,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T5,T21
1	Covered	T4,T7,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T21,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T7,T5
Phase1St	198	Covered	T4,T7,T5
Phase2St	215	Covered	T4,T7,T5
Phase3St	233	Covered	T4,T7,T5
TerminalSt	249	Covered	T4,T7,T5
TimeoutSt	159	Covered	T7,T17,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T4,T7,T5
IdleSt->TimeoutSt	159	Covered	T7,T17,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T31,T89
Phase0St->Phase1St	198	Covered	T4,T7,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T7,T12,T30
Phase1St->Phase2St	215	Covered	T4,T7,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T86,T90
Phase2St->Phase3St	233	Covered	T4,T7,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T7,T21,T88
Phase3St->TerminalSt	249	Covered	T4,T7,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T21,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T17,T21
TimeoutSt->Phase0St	172	Covered	T21,T81,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T17,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T81,T43
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T17,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T82
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T31,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T7,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T7,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T12,T54
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T7,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T7,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T86,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T7,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T7,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T21,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T7,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T7,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T21,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T7,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	689880002	209	0	0
CheckAccumTrig0_A	689880002	850	0	0
CheckAccumTrig1_A	689880002	51	0	0
CheckClr_A	689880002	408	0	0
CheckEn_A	689749940	278506665	0	0
CheckPhase0_A	689880002	957	0	0
CheckPhase1_A	689880002	940	0	0
CheckPhase2_A	689880002	916	0	0
CheckPhase3_A	689880002	897	0	0
CheckTimeout0_A	689880002	1221	0	0
CheckTimeoutSt1_A	689880002	136270	0	0
CheckTimeoutSt2_A	689880002	1095	0	0
CheckTimeoutStTrig_A	689880002	73	0	0
ErrorStAllEscAsserted_A	689880002	1264	0	0
ErrorStIsTerminal_A	689880002	1054	0	0
EscStateOut_A	689748954	689674702	0	0
u_state_regs_A	689880002	689716350	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	209	0	0
T9	19680	28	0	0
T10	0	34	0	0
T11	0	55	0	0
T24	89505	0	0	0
T32	0	57	0	0
T33	0	35	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	850	0	0
T4	100814	1	0	0
T5	181461	1	0	0
T6	27800	0	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T12	0	7	0	0
T13	0	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	5	0	0
T26	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	15979	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	51	0	0
T29	319095	2	0	0
T30	158661	0	0	0
T38	254555	1	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T63	0	5	0	0
T65	0	3	0	0
T75	267460	0	0	0
T76	64876	0	0	0
T77	43836	0	0	0
T78	251305	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	408	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	5	0	0
T12	0	6	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	2	0	0
T22	0	1	0	0
T26	93831	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T46	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T74	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689749940	278506665	0	0
T1	274351	274343	0	0
T2	7358	5578	0	0
T3	521145	365062	0	0
T4	100814	48947	0	0
T5	181461	5766	0	0
T7	295400	157815	0	0
T8	903136	859708	0	0
T15	65271	65185	0	0
T16	7778	7702	0	0
T17	3950	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	957	0	0
T4	100814	1	0	0
T5	181461	1	0	0
T6	27800	0	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	7	0	0
T26	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	15979	0	0	0
T81	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	940	0	0
T4	100814	1	0	0
T5	181461	1	0	0
T6	27800	0	0	0
T7	295400	7	0	0
T8	903136	0	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	7	0	0
T26	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	15979	0	0	0
T81	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	916	0	0
T4	100814	1	0	0
T5	181461	1	0	0
T6	27800	0	0	0
T7	295400	7	0	0
T8	903136	0	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	7	0	0
T26	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	15979	0	0	0
T81	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	897	0	0
T4	100814	1	0	0
T5	181461	1	0	0
T6	27800	0	0	0
T7	295400	6	0	0
T8	903136	0	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	6	0	0
T26	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	15979	0	0	0
T81	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1221	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	1	0	0
T21	222301	3	0	0
T26	93831	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T74	0	1	0	0
T81	0	1	0	0
T82	0	6	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	136270	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	64	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	36	0	0
T21	222301	1738	0	0
T26	93831	0	0	0
T38	0	42	0	0
T43	0	607	0	0
T48	0	83	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T74	0	174	0	0
T81	0	137	0	0
T82	0	1019	0	0
T84	0	371	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1095	0	0
T6	27800	0	0	0
T17	3950	1	0	0
T21	222301	1	0	0
T26	93831	0	0	0
T30	0	215	0	0
T41	0	1	0	0
T42	321191	0	0	0
T43	163374	0	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T74	0	1	0	0
T75	0	65	0	0
T76	0	3	0	0
T81	83751	0	0	0
T82	75002	6	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	73	0	0
T6	27800	0	0	0
T21	222301	2	0	0
T26	93831	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T42	321191	0	0	0
T43	163374	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T52	0	1	0	0
T76	0	1	0	0
T81	83751	1	0	0
T82	75002	0	0	0
T83	40598	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1264	0	0
T9	19680	160	0	0
T10	0	180	0	0
T11	0	384	0	0
T24	89505	0	0	0
T32	0	358	0	0
T33	0	182	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1054	0	0
T9	19680	130	0	0
T10	0	150	0	0
T11	0	324	0	0
T24	89505	0	0	0
T32	0	298	0	0
T33	0	152	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689748954	689674702	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	689716350	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T7,T16,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T16
1	0	1	Covered	T8,T42,T44
1	1	0	Covered	T7,T21,T51
1	1	1	Covered	T15,T21,T51

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T21,T51
0	1	Covered	T15,T21,T83
1	0	Covered	T22,T24,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T21,T51
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T24,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T21,T51
1	0	Not Covered
1	1	Covered	T15,T21,T83

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T15,T16
1	Covered	T7,T46,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T21,T43
1	Covered	T15,T16,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T15,T16
1	Covered	T21,T43,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T15,T16
1	Covered	T21,T83,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T15,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T15,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T21,T45,T46

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T15,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T7,T15,T16
Phase1St	198	Covered	T7,T15,T16
Phase2St	215	Covered	T7,T15,T16
Phase3St	233	Covered	T7,T15,T16
TerminalSt	249	Covered	T7,T15,T16
TimeoutSt	159	Covered	T15,T21,T51

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T7,T16,T21
IdleSt->TimeoutSt	159	Covered	T15,T21,T51
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T7,T27,T91
Phase0St->Phase1St	198	Covered	T7,T15,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T90,T92
Phase1St->Phase2St	215	Covered	T7,T15,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T93,T94
Phase2St->Phase3St	233	Covered	T7,T15,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T22,T24,T75
Phase3St->TerminalSt	249	Covered	T7,T15,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T16,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T51,T81
TimeoutSt->Phase0St	172	Covered	T15,T21,T83

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T21,T51
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T21,T83
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T21,T51
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T51,T81
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T91,T66
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T15,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T15,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T90,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T7,T15,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T15,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T93,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T7,T15,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T24,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T7,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T21,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T15,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	689880002	240	0	0
CheckAccumTrig0_A	689880002	486	0	0
CheckAccumTrig1_A	689880002	27	0	0
CheckClr_A	689880002	214	0	0
CheckEn_A	689749940	315935051	0	0
CheckPhase0_A	689880002	573	0	0
CheckPhase1_A	689880002	566	0	0
CheckPhase2_A	689880002	558	0	0
CheckPhase3_A	689880002	545	0	0
CheckTimeout0_A	689880002	1311	0	0
CheckTimeoutSt1_A	689880002	153244	0	0
CheckTimeoutSt2_A	689880002	1209	0	0
CheckTimeoutStTrig_A	689880002	73	0	0
ErrorStAllEscAsserted_A	689880002	1160	0	0
ErrorStIsTerminal_A	689880002	950	0	0
EscStateOut_A	689748954	689674702	0	0
u_state_regs_A	689880002	689716350	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	240	0	0
T9	19680	26	0	0
T10	0	35	0	0
T11	0	77	0	0
T24	89505	0	0	0
T32	0	78	0	0
T33	0	24	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	486	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	2	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	2	0	0
T22	0	2	0	0
T26	93831	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	15979	0	0	0
T51	37325	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	27	0	0
T22	150999	1	0	0
T23	67908	0	0	0
T24	0	1	0	0
T31	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	2	0	0
T67	184454	0	0	0
T68	38741	0	0	0
T69	18546	0	0	0
T70	959234	0	0	0
T71	272618	0	0	0
T72	525688	0	0	0
T73	42085	0	0	0
T74	59111	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	214	0	0
T6	27800	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	2	0	0
T22	0	2	0	0
T24	0	5	0	0
T26	93831	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T38	0	1	0	0
T42	321191	0	0	0
T46	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T71	0	1	0	0
T80	0	1	0	0
T81	83751	0	0	0
T82	75002	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689749940	315935051	0	0
T1	274351	274343	0	0
T2	7358	7263	0	0
T3	521145	91953	0	0
T4	100814	990575	0	0
T5	181461	181451	0	0
T7	295400	270401	0	0
T8	903136	143423	0	0
T15	65271	2054	0	0
T16	7778	4235	0	0
T17	3950	586	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	573	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	1	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	5	0	0
T26	93831	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T83	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	566	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	1	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	5	0	0
T26	93831	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T83	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	558	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	1	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	5	0	0
T26	93831	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T83	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	545	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	1	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	222301	5	0	0
T26	93831	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T83	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1311	0	0
T6	27800	0	0	0
T15	65271	1	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	16	0	0
T22	0	1	0	0
T24	0	4	0	0
T26	93831	0	0	0
T43	0	1	0	0
T50	15979	0	0	0
T51	37325	7	0	0
T81	83751	7	0	0
T82	75002	1	0	0
T83	0	1	0	0
T84	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	153244	0	0
T6	27800	0	0	0
T15	65271	158	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	2554	0	0
T22	0	20	0	0
T24	0	534	0	0
T26	93831	0	0	0
T43	0	47	0	0
T50	15979	0	0	0
T51	37325	1044	0	0
T81	83751	1159	0	0
T82	75002	176	0	0
T83	0	48	0	0
T84	0	874	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1209	0	0
T6	27800	0	0	0
T21	222301	13	0	0
T24	0	2	0	0
T26	93831	0	0	0
T29	0	4	0	0
T38	0	1	0	0
T42	321191	0	0	0
T43	163374	1	0	0
T50	15979	0	0	0
T51	37325	7	0	0
T76	0	5	0	0
T81	83751	7	0	0
T82	75002	1	0	0
T83	40598	0	0	0
T84	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	73	0	0
T6	27800	0	0	0
T15	65271	1	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	3	0	0
T24	0	1	0	0
T26	93831	0	0	0
T27	0	1	0	0
T29	0	3	0	0
T30	0	5	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T57	0	1	0	0
T80	0	2	0	0
T81	83751	0	0	0
T82	75002	0	0	0
T83	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1160	0	0
T9	19680	165	0	0
T10	0	141	0	0
T11	0	348	0	0
T24	89505	0	0	0
T32	0	348	0	0
T33	0	158	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	950	0	0
T9	19680	135	0	0
T10	0	111	0	0
T11	0	288	0	0
T24	89505	0	0	0
T32	0	288	0	0
T33	0	128	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689748954	689674702	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	689716350	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T20
1	1	1	Covered	T1,T7,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T16,T17
1	0	1	Covered	T2,T4,T7
1	1	0	Covered	T15,T16,T21
1	1	1	Covered	T7,T21,T51

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T51
0	1	Covered	T7,T21,T84
1	0	Covered	T23,T52,T85

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T21,T51
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T52,T85

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T21,T51
1	0	Not Covered
1	1	Covered	T7,T21,T84

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T5
1	Covered	T7,T21,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T5
1	Covered	T21,T42,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T5
1	Covered	T7,T84,T47

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T21,T42
1	Covered	T1,T7,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T7,T5
Phase1St	198	Covered	T1,T7,T5
Phase2St	215	Covered	T1,T7,T5
Phase3St	233	Covered	T1,T7,T5
TerminalSt	249	Covered	T1,T7,T5
TimeoutSt	159	Covered	T7,T21,T51

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T7,T5
IdleSt->TimeoutSt	159	Covered	T7,T21,T51
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T95,T96,T97
Phase0St->Phase1St	198	Covered	T1,T7,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T98,T99
Phase1St->Phase2St	215	Covered	T1,T7,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T91,T100
Phase2St->Phase3St	233	Covered	T1,T7,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T101,T102,T103
Phase3St->TerminalSt	249	Covered	T1,T7,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T21,T45
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T21,T51
TimeoutSt->Phase0St	172	Covered	T7,T21,T84

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T51
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T84
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T51
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T51
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T95,T96,T97
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T99,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T91,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T101,T102,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T21,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	689880002	198	0	0
CheckAccumTrig0_A	689880002	531	0	0
CheckAccumTrig1_A	689880002	20	0	0
CheckClr_A	689880002	224	0	0
CheckEn_A	689749940	271699092	0	0
CheckPhase0_A	689880002	610	0	0
CheckPhase1_A	689880002	604	0	0
CheckPhase2_A	689880002	592	0	0
CheckPhase3_A	689880002	580	0	0
CheckTimeout0_A	689880002	793	0	0
CheckTimeoutSt1_A	689880002	104951	0	0
CheckTimeoutSt2_A	689880002	705	0	0
CheckTimeoutStTrig_A	689880002	67	0	0
ErrorStAllEscAsserted_A	689880002	1203	0	0
ErrorStIsTerminal_A	689880002	993	0	0
EscStateOut_A	689748954	689674702	0	0
u_state_regs_A	689880002	689716350	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	198	0	0
T9	19680	22	0	0
T10	0	45	0	0
T11	0	68	0	0
T24	89505	0	0	0
T32	0	33	0	0
T33	0	30	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	531	0	0
T1	274351	1	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1	0	0
T7	295400	2	0	0
T8	903136	0	0	0
T14	0	2	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	5	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	20	0	0
T9	19680	0	0	0
T23	67908	1	0	0
T24	89505	0	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T52	0	1	0	0
T61	0	1	0	0
T64	0	1	0	0
T71	272618	0	0	0
T72	525688	0	0	0
T73	42085	0	0	0
T74	59111	0	0	0
T85	0	1	0	0
T95	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	224	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	5	0	0
T14	0	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	93831	0	0	0
T29	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689749940	271699092	0	0
T1	274351	11253	0	0
T2	7358	2173	0	0
T3	521145	144226	0	0
T4	100814	48975	0	0
T5	181461	6181	0	0
T7	295400	210175	0	0
T8	903136	292985	0	0
T15	65271	65185	0	0
T16	7778	6050	0	0
T17	3950	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	610	0	0
T1	274351	1	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T14	0	2	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	6	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	604	0	0
T1	274351	1	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T14	0	2	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	6	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	592	0	0
T1	274351	1	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T14	0	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	6	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	580	0	0
T1	274351	1	0	0
T2	7358	0	0	0
T3	521145	0	0	0
T4	100814	0	0	0
T5	181461	1	0	0
T7	295400	8	0	0
T8	903136	0	0	0
T14	0	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	0	6	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	793	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	8	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	18	0	0
T23	0	2	0	0
T26	93831	0	0	0
T45	0	2	0	0
T49	0	3	0	0
T50	15979	0	0	0
T51	37325	6	0	0
T75	0	56	0	0
T81	0	5	0	0
T82	0	2	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	104951	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	763	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	1617	0	0
T23	0	30	0	0
T26	93831	0	0	0
T45	0	34	0	0
T49	0	180	0	0
T50	15979	0	0	0
T51	37325	932	0	0
T75	0	9194	0	0
T81	0	806	0	0
T82	0	362	0	0
T84	0	292	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	705	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	2	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	17	0	0
T23	0	1	0	0
T26	93831	0	0	0
T49	0	3	0	0
T50	15979	0	0	0
T51	37325	6	0	0
T75	0	56	0	0
T76	0	2	0	0
T81	0	5	0	0
T82	0	2	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	67	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	6	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	1	0	0
T26	93831	0	0	0
T29	0	1	0	0
T45	0	2	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T76	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T88	0	6	0	0
T109	0	1	0	0
T110	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1203	0	0
T9	19680	182	0	0
T10	0	195	0	0
T11	0	337	0	0
T24	89505	0	0	0
T32	0	328	0	0
T33	0	161	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	993	0	0
T9	19680	152	0	0
T10	0	165	0	0
T11	0	277	0	0
T24	89505	0	0	0
T32	0	268	0	0
T33	0	131	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689748954	689674702	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	689716350	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T16,T17
1	0	1	Covered	T3,T4,T8
1	1	0	Covered	T7,T15,T17
1	1	1	Covered	T7,T21,T81

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T81
0	1	Covered	T21,T84,T46
1	0	Covered	T21,T49,T68

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T21,T81
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T49,T68

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T21,T81
1	0	Covered	T25
1	1	Covered	T21,T84,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T3,T7,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T7
1	Covered	T1,T21,T46

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T3,T5,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T8,T45,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T8
Phase1St	198	Covered	T1,T3,T8
Phase2St	215	Covered	T1,T3,T8
Phase3St	233	Covered	T1,T3,T8
TerminalSt	249	Covered	T1,T3,T8
TimeoutSt	159	Covered	T7,T21,T81

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T8
IdleSt->TimeoutSt	159	Covered	T7,T21,T81
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T86,T111,T63
Phase0St->Phase1St	198	Covered	T1,T3,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T86,T112,T101
Phase1St->Phase2St	215	Covered	T1,T3,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T113,T114
Phase2St->Phase3St	233	Covered	T1,T3,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T115,T114,T64
Phase3St->TerminalSt	249	Covered	T1,T3,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T21,T81
TimeoutSt->Phase0St	172	Covered	T21,T84,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T81
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T84,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T81
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T21,T81
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T86,T111,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T86,T112,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T113,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T115,T114,T64
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	689880002	241	0	0
CheckAccumTrig0_A	689880002	507	0	0
CheckAccumTrig1_A	689880002	16	0	0
CheckClr_A	689880002	200	0	0
CheckEn_A	689749940	275307199	0	0
CheckPhase0_A	689880002	584	0	0
CheckPhase1_A	689880002	572	0	0
CheckPhase2_A	689880002	564	0	0
CheckPhase3_A	689880002	557	0	0
CheckTimeout0_A	689880002	1587	0	0
CheckTimeoutSt1_A	689880002	150781	0	0
CheckTimeoutSt2_A	689880002	1500	0	0
CheckTimeoutStTrig_A	689880002	69	0	0
ErrorStAllEscAsserted_A	689880002	1261	0	0
ErrorStIsTerminal_A	689880002	1051	0	0
EscStateOut_A	689748954	689674702	0	0
u_state_regs_A	689880002	689716350	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	241	0	0
T9	19680	35	0	0
T10	0	43	0	0
T11	0	83	0	0
T24	89505	0	0	0
T32	0	61	0	0
T33	0	19	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	507	0	0
T1	274351	5	0	0
T2	7358	0	0	0
T3	521145	2	0	0
T4	100814	0	0	0
T5	181461	12	0	0
T7	295400	1	0	0
T8	903136	1	0	0
T14	0	1	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	3	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	16	0	0
T6	27800	0	0	0
T21	222301	2	0	0
T26	93831	0	0	0
T42	321191	0	0	0
T43	163374	0	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T60	0	1	0	0
T68	0	1	0	0
T81	83751	0	0	0
T82	75002	0	0	0
T83	40598	0	0	0
T89	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	200	0	0
T1	274351	4	0	0
T2	7358	0	0	0
T3	521145	1	0	0
T4	100814	0	0	0
T5	181461	11	0	0
T7	295400	0	0	0
T8	903136	0	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	1	0	0
T29	0	1	0	0
T45	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689749940	275307199	0	0
T1	274351	2545	0	0
T2	7358	7263	0	0
T3	521145	104764	0	0
T4	100814	990572	0	0
T5	181461	2277	0	0
T7	295400	170746	0	0
T8	903136	147518	0	0
T15	65271	65185	0	0
T16	7778	4235	0	0
T17	3950	3044	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	584	0	0
T1	274351	5	0	0
T2	7358	0	0	0
T3	521145	2	0	0
T4	100814	0	0	0
T5	181461	12	0	0
T7	295400	1	0	0
T8	903136	1	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	7	0	0
T45	0	1	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	572	0	0
T1	274351	5	0	0
T2	7358	0	0	0
T3	521145	2	0	0
T4	100814	0	0	0
T5	181461	12	0	0
T7	295400	1	0	0
T8	903136	1	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	7	0	0
T45	0	1	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	564	0	0
T1	274351	5	0	0
T2	7358	0	0	0
T3	521145	2	0	0
T4	100814	0	0	0
T5	181461	12	0	0
T7	295400	1	0	0
T8	903136	1	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	7	0	0
T45	0	1	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	557	0	0
T1	274351	5	0	0
T2	7358	0	0	0
T3	521145	2	0	0
T4	100814	0	0	0
T5	181461	12	0	0
T7	295400	1	0	0
T8	903136	1	0	0
T15	65271	0	0	0
T16	7778	1	0	0
T17	3950	0	0	0
T21	0	7	0	0
T45	0	1	0	0
T46	0	1	0	0
T84	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1587	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	8	0	0
T26	93831	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T68	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	9	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	150781	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	44	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	1716	0	0
T26	93831	0	0	0
T43	0	47	0	0
T46	0	285	0	0
T49	0	92	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T71	0	157	0	0
T81	0	151	0	0
T82	0	323	0	0
T83	0	589	0	0
T84	0	272	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1500	0	0
T5	181461	0	0	0
T6	27800	0	0	0
T7	295400	1	0	0
T15	65271	0	0	0
T16	7778	0	0	0
T17	3950	0	0	0
T21	222301	4	0	0
T26	93831	0	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T71	0	2	0	0
T74	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	9	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	69	0	0
T6	27800	0	0	0
T21	222301	2	0	0
T26	93831	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T42	321191	0	0	0
T43	163374	0	0	0
T46	0	1	0	0
T50	15979	0	0	0
T51	37325	0	0	0
T75	0	2	0	0
T76	0	1	0	0
T81	83751	0	0	0
T82	75002	0	0	0
T83	40598	0	0	0
T84	0	1	0	0
T86	0	4	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1261	0	0
T9	19680	161	0	0
T10	0	181	0	0
T11	0	347	0	0
T24	89505	0	0	0
T32	0	379	0	0
T33	0	193	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	1051	0	0
T9	19680	131	0	0
T10	0	151	0	0
T11	0	287	0	0
T24	89505	0	0	0
T32	0	319	0	0
T33	0	163	0	0
T34	77579	0	0	0
T35	10840	0	0	0
T36	28215	0	0	0
T37	9714	0	0	0
T38	254555	0	0	0
T39	14984	0	0	0
T40	328823	0	0	0
T41	18268	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689748954	689674702	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689880002	689716350	0	0
T1	274351	274343	0	0
T2	7358	7264	0	0
T3	521145	521082	0	0
T4	100814	100808	0	0
T5	181461	181451	0	0
T7	295400	295386	0	0
T8	903136	903043	0	0
T15	65271	65186	0	0
T16	7778	7703	0	0
T17	3950	3852	0	0