Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64291578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30900543

1

T1

1028

T2

12433

T3

1016

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14320474	1			T1	495		T2	4815		T3	394
values[0x0]	39688075	1			T1	1289		T2	17865		T3	1323
values[0x1]	41183572	1			T1	1261		T2	17581		T3	1321

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55206391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39985730

1

T1

1301

T2

15753

T3

1266

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	294465	1			T1	11		T2	137		T3	10
valid_sources[0x01]	324871	1			T1	8		T2	160		T3	17
valid_sources[0x02]	306652	1			T1	15		T2	148		T3	12
valid_sources[0x03]	324513	1			T1	15		T2	151		T3	7
valid_sources[0x04]	881058	1			T1	16		T2	162		T3	11
valid_sources[0x05]	309984	1			T1	16		T2	167		T3	14
valid_sources[0x06]	617077	1			T1	3		T2	147		T3	9
valid_sources[0x07]	294280	1			T1	8		T2	154		T3	7
valid_sources[0x08]	301637	1			T1	14		T2	180		T3	15
valid_sources[0x09]	799950	1			T1	7		T2	172		T3	10
valid_sources[0x0a]	319783	1			T1	22		T2	148		T3	9
valid_sources[0x0b]	310609	1			T1	10		T2	142		T3	9
valid_sources[0x0c]	534418	1			T1	15		T2	165		T3	23
valid_sources[0x0d]	293376	1			T1	9		T2	194		T3	9
valid_sources[0x0e]	304690	1			T1	12		T2	149		T3	16
valid_sources[0x0f]	295299	1			T1	18		T2	137		T3	13
valid_sources[0x10]	298739	1			T1	10		T2	172		T3	9
valid_sources[0x11]	309273	1			T1	8		T2	195		T3	12
valid_sources[0x12]	290345	1			T1	13		T2	175		T3	9
valid_sources[0x13]	291867	1			T1	17		T2	139		T3	14
valid_sources[0x14]	295015	1			T1	2		T2	153		T3	8
valid_sources[0x15]	309889	1			T1	9		T2	191		T3	13
valid_sources[0x16]	298806	1			T1	15		T2	156		T3	16
valid_sources[0x17]	302275	1			T1	14		T2	187		T3	14
valid_sources[0x18]	297029	1			T1	19		T2	173		T3	9
valid_sources[0x19]	304383	1			T1	12		T2	168		T3	15
valid_sources[0x1a]	300495	1			T1	6		T2	167		T3	15
valid_sources[0x1b]	294164	1			T1	15		T2	187		T3	7
valid_sources[0x1c]	324157	1			T1	19		T2	113		T3	9
valid_sources[0x1d]	617452	1			T1	8		T2	125		T3	11
valid_sources[0x1e]	308156	1			T1	10		T2	162		T3	18
valid_sources[0x1f]	327022	1			T1	14		T2	170		T3	19
valid_sources[0x20]	297532	1			T1	13		T2	164		T3	12
valid_sources[0x21]	291910	1			T1	14		T2	137		T3	12
valid_sources[0x22]	582401	1			T1	13		T2	161		T3	12
valid_sources[0x23]	295681	1			T1	11		T2	129		T3	13
valid_sources[0x24]	297862	1			T1	18		T2	147		T3	5
valid_sources[0x25]	299222	1			T1	29		T2	171		T3	12
valid_sources[0x26]	294791	1			T1	8		T2	126		T3	11
valid_sources[0x27]	752257	1			T1	10		T2	175		T3	16
valid_sources[0x28]	293186	1			T1	11		T2	145		T3	10
valid_sources[0x29]	295116	1			T1	16		T2	141		T3	8
valid_sources[0x2a]	335159	1			T1	8		T2	132		T3	15
valid_sources[0x2b]	318040	1			T1	9		T2	192		T3	13
valid_sources[0x2c]	755529	1			T1	8		T2	133		T3	17
valid_sources[0x2d]	305746	1			T1	11		T2	172		T3	13
valid_sources[0x2e]	294631	1			T1	13		T2	154		T3	14
valid_sources[0x2f]	300170	1			T1	7		T2	175		T3	15
valid_sources[0x30]	299812	1			T1	22		T2	195		T3	7
valid_sources[0x31]	305832	1			T1	8		T2	165		T3	10
valid_sources[0x32]	299405	1			T1	14		T2	162		T3	11
valid_sources[0x33]	752551	1			T1	13		T2	150		T3	18
valid_sources[0x34]	303155	1			T1	15		T2	162		T3	9
valid_sources[0x35]	722039	1			T1	15		T2	141		T3	11
valid_sources[0x36]	305897	1			T1	7		T2	139		T3	7
valid_sources[0x37]	305508	1			T1	21		T2	183		T3	18
valid_sources[0x38]	299891	1			T1	6		T2	165		T3	11
valid_sources[0x39]	307045	1			T1	7		T2	138		T3	14
valid_sources[0x3a]	1111429	1			T1	10		T2	136		T3	9
valid_sources[0x3b]	289416	1			T1	9		T2	155		T3	7
valid_sources[0x3c]	295316	1			T1	3		T2	126		T3	20
valid_sources[0x3d]	769988	1			T1	7		T2	145		T3	11
valid_sources[0x3e]	291244	1			T1	12		T2	153		T3	9
valid_sources[0x3f]	314607	1			T1	5		T2	148		T3	13
valid_sources[0x40]	295467	1			T1	13		T2	150		T3	23
valid_sources[0x41]	315148	1			T1	12		T2	169		T3	6
valid_sources[0x42]	291433	1			T1	6		T2	186		T3	4
valid_sources[0x43]	298375	1			T1	5		T2	153		T3	9
valid_sources[0x44]	305543	1			T1	13		T2	152		T3	11
valid_sources[0x45]	739621	1			T1	18		T2	143		T3	9
valid_sources[0x46]	760358	1			T1	14		T2	195		T3	10
valid_sources[0x47]	306890	1			T1	6		T2	151		T3	10
valid_sources[0x48]	296977	1			T1	19		T2	177		T3	20
valid_sources[0x49]	303776	1			T1	13		T2	165		T3	17
valid_sources[0x4a]	664445	1			T1	9		T2	138		T3	9
valid_sources[0x4b]	303243	1			T1	6		T2	180		T3	3
valid_sources[0x4c]	307477	1			T1	11		T2	140		T3	19
valid_sources[0x4d]	695100	1			T1	8		T2	161		T3	11
valid_sources[0x4e]	313405	1			T1	16		T2	199		T3	11
valid_sources[0x4f]	294502	1			T1	14		T2	148		T3	17
valid_sources[0x50]	290675	1			T1	16		T2	159		T3	25
valid_sources[0x51]	337398	1			T1	14		T2	146		T3	8
valid_sources[0x52]	304689	1			T1	6		T2	166		T3	6
valid_sources[0x53]	305575	1			T1	10		T2	175		T3	19
valid_sources[0x54]	305339	1			T1	12		T2	165		T3	19
valid_sources[0x55]	295982	1			T1	7		T2	166		T3	14
valid_sources[0x56]	296778	1			T1	14		T2	146		T3	12
valid_sources[0x57]	326038	1			T1	8		T2	161		T3	8
valid_sources[0x58]	293571	1			T1	11		T2	148		T3	11
valid_sources[0x59]	300542	1			T1	11		T2	162		T3	18
valid_sources[0x5a]	305158	1			T1	8		T2	163		T3	14
valid_sources[0x5b]	309132	1			T1	21		T2	167		T3	7
valid_sources[0x5c]	294696	1			T1	10		T2	176		T3	15
valid_sources[0x5d]	302103	1			T1	7		T2	140		T3	15
valid_sources[0x5e]	780545	1			T1	13		T2	141		T3	12
valid_sources[0x5f]	302568	1			T1	6		T2	165		T3	6
valid_sources[0x60]	302882	1			T1	11		T2	148		T3	11
valid_sources[0x61]	295023	1			T1	8		T2	176		T3	9
valid_sources[0x62]	293804	1			T1	12		T2	126		T3	9
valid_sources[0x63]	296899	1			T1	8		T2	153		T3	18
valid_sources[0x64]	294511	1			T1	17		T2	142		T3	8
valid_sources[0x65]	305600	1			T1	10		T2	169		T3	15
valid_sources[0x66]	595580	1			T1	9		T2	143		T3	8
valid_sources[0x67]	304731	1			T1	16		T2	144		T3	14
valid_sources[0x68]	289955	1			T1	5		T2	160		T3	14
valid_sources[0x69]	294546	1			T1	10		T2	152		T3	13
valid_sources[0x6a]	297339	1			T1	24		T2	134		T3	18
valid_sources[0x6b]	671887	1			T1	19		T2	187		T3	14
valid_sources[0x6c]	639998	1			T1	2		T2	208		T3	9
valid_sources[0x6d]	303778	1			T1	8		T2	156		T3	12
valid_sources[0x6e]	303492	1			T1	19		T2	115		T3	11
valid_sources[0x6f]	293350	1			T1	12		T2	160		T3	11
valid_sources[0x70]	317191	1			T1	20		T2	168		T3	11
valid_sources[0x71]	304814	1			T1	10		T2	153		T3	14
valid_sources[0x72]	308623	1			T1	5		T2	169		T3	10
valid_sources[0x73]	298696	1			T1	8		T2	142		T3	9
valid_sources[0x74]	302802	1			T1	10		T2	159		T3	12
valid_sources[0x75]	298299	1			T1	15		T2	166		T3	8
valid_sources[0x76]	302172	1			T1	13		T2	148		T3	9
valid_sources[0x77]	301421	1			T1	5		T2	167		T3	6
valid_sources[0x78]	296528	1			T1	15		T2	143		T3	4
valid_sources[0x79]	293691	1			T1	11		T2	169		T3	15
valid_sources[0x7a]	785728	1			T1	16		T2	160		T3	9
valid_sources[0x7b]	720143	1			T1	16		T2	155		T3	11
valid_sources[0x7c]	771742	1			T1	18		T2	162		T3	11
valid_sources[0x7d]	296011	1			T1	4		T2	158		T3	12
valid_sources[0x7e]	306366	1			T1	20		T2	169		T3	13
valid_sources[0x7f]	300913	1			T1	5		T2	140		T3	10
valid_sources[0x80]	306665	1			T1	17		T2	152		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7071075

1

T1

250

T2

2383

T3

198

values[0x0]

all_enables

biggest_size

15090999

1

T1

487

T2

6526

T3

515

values[0x1]

all_enables

biggest_size

8738469

1

T1

291

T2

3524

T3

303