Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T185,T186,T187
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12268	0	0
DisabledNoTrigBkwd_A	2147483647	832984	0	0
DisabledNoTrigFwd_A	2147483647	1470996704	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12268	0	0
T77	459050	0	0	0
T81	19752	0	0	0
T108	786332	0	0	0
T111	100370	0	0	0
T185	1081	299	0	0
T186	0	591	0	0
T187	1263	573	0	0
T188	0	612	0	0
T189	0	834	0	0
T190	0	447	0	0
T191	0	708	0	0
T192	0	482	0	0
T193	0	878	0	0
T194	0	818	0	0
T195	0	623	0	0
T196	1406	624	0	0
T197	0	680	0	0
T198	0	702	0	0
T199	0	613	0	0
T200	0	1131	0	0
T201	0	483	0	0
T202	0	525	0	0
T203	0	287	0	0
T204	0	358	0	0
T205	14227	0	0	0
T206	80707	0	0	0
T207	567204	0	0	0
T208	308359	0	0	0
T209	415538	0	0	0
T210	488241	0	0	0
T211	25544	0	0	0
T212	16336	0	0	0
T213	49528	0	0	0
T214	192946	0	0	0
T215	917431	0	0	0
T216	125766	0	0	0
T217	108879	0	0	0
T218	2395	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	832984	0	0
T1	47800	21	0	0
T2	1505421	253	0	0
T3	35622	0	0	0
T4	3967648	1827	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	2276	0	0
T9	1016592	648	0	0
T10	2337104	2	0	0
T14	0	3	0	0
T16	0	4224	0	0
T17	161512	0	0	0
T18	1125932	14106	0	0
T19	40291	1	0	0
T20	191725	95	0	0
T21	0	1720	0	0
T25	0	1162	0	0
T31	0	46	0	0
T44	0	5	0	0
T45	0	10	0	0
T46	0	3	0	0
T47	0	77	0	0
T49	0	1185	0	0
T75	0	99	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1470996704	0	0
T1	95600	56423	0	0
T2	2007228	1531247	0	0
T3	47496	21133	0	0
T4	3967648	2972852	0	0
T5	3023404	1497975	0	0
T6	446432	1068859	0	0
T7	1521152	786325	0	0
T9	1016592	765186	0	0
T10	2337104	1292934	0	0
T17	161512	146225	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T190,T193
1	1	Covered	T3,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	669010952	3847	0	0
DisabledNoTrigBkwd_A	669010952	228253	0	0
DisabledNoTrigFwd_A	669010952	359139255	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	3847	0	0
T187	1263	573	0	0
T190	0	447	0	0
T193	0	878	0	0
T194	0	818	0	0
T200	0	1131	0	0
T210	488241	0	0	0
T211	25544	0	0	0
T212	16336	0	0	0
T213	49528	0	0	0
T214	192946	0	0	0
T215	917431	0	0	0
T216	125766	0	0	0
T217	108879	0	0	0
T218	2395	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	228253	0	0
T4	991912	1817	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	438	0	0
T10	584276	0	0	0
T16	0	1624	0	0
T17	40378	0	0	0
T18	562966	9202	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	0	5	0	0
T44	0	3	0	0
T45	0	10	0	0
T46	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	359139255	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	1700	0	0
T4	991912	582	0	0
T5	755851	40550	0	0
T6	111608	582	0	0
T7	380288	379286	0	0
T9	254148	105028	0	0
T10	584276	619	0	0
T17	40378	28634	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T185,T186,T195
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	669010952	1996	0	0
DisabledNoTrigBkwd_A	669010952	193572	0	0
DisabledNoTrigFwd_A	669010952	384328027	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1996	0	0
T77	459050	0	0	0
T81	19752	0	0	0
T108	786332	0	0	0
T111	100370	0	0	0
T185	1081	299	0	0
T186	0	591	0	0
T195	0	623	0	0
T201	0	483	0	0
T205	14227	0	0	0
T206	80707	0	0	0
T207	567204	0	0	0
T208	308359	0	0	0
T209	415538	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	193572	0	0
T1	23900	17	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	10	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	7	0	0
T9	254148	199	0	0
T10	584276	2	0	0
T14	0	3	0	0
T16	0	2034	0	0
T17	40378	0	0	0
T18	0	891	0	0
T31	0	17	0	0
T47	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	384328027	0	0
T1	23900	2170	0	0
T2	501807	501719	0	0
T3	11874	6969	0	0
T4	991912	988642	0	0
T5	755851	661112	0	0
T6	111608	111600	0	0
T7	380288	377903	0	0
T9	254148	157182	0	0
T10	584276	439779	0	0
T17	40378	36999	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T199,T202
1	1	Covered	T1,T5,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	669010952	2120	0	0
DisabledNoTrigBkwd_A	669010952	180345	0	0
DisabledNoTrigFwd_A	669010952	379703785	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	2120	0	0
T24	28398	0	0	0
T93	308290	0	0	0
T196	1406	624	0	0
T199	0	613	0	0
T202	0	525	0	0
T204	0	358	0	0
T219	23596	0	0	0
T220	121429	0	0	0
T221	9136	0	0	0
T222	178344	0	0	0
T223	128581	0	0	0
T224	376111	0	0	0
T225	105477	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	180345	0	0
T1	23900	4	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	742	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T16	0	507	0	0
T17	40378	0	0	0
T18	0	537	0	0
T21	0	1720	0	0
T25	0	1162	0	0
T31	0	15	0	0
T47	0	69	0	0
T49	0	1185	0	0
T75	0	79	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	379703785	0	0
T1	23900	6623	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	40558	0	0
T6	111608	100861	0	0
T7	380288	10095	0	0
T9	254148	252245	0	0
T10	584276	504578	0	0
T17	40378	40296	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T191
1	1	Covered	T2,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	669010952	4305	0	0
DisabledNoTrigBkwd_A	669010952	230814	0	0
DisabledNoTrigFwd_A	669010952	347825637	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	4305	0	0
T94	13418	0	0	0
T188	2990	612	0	0
T189	3959	834	0	0
T190	1213	0	0	0
T191	0	708	0	0
T192	0	482	0	0
T197	0	680	0	0
T198	0	702	0	0
T203	0	287	0	0
T226	37661	0	0	0
T227	38867	0	0	0
T228	7296	0	0	0
T229	24616	0	0	0
T230	360484	0	0	0
T231	352262	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	230814	0	0
T2	501807	253	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1527	0	0
T9	254148	11	0	0
T10	584276	0	0	0
T16	0	59	0	0
T17	40378	0	0	0
T18	562966	3476	0	0
T20	0	95	0	0
T31	0	9	0	0
T44	0	2	0	0
T48	0	4	0	0
T75	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	347825637	0	0
T1	23900	23815	0	0
T2	501807	26090	0	0
T3	11874	640	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	855816	0	0
T7	380288	19041	0	0
T9	254148	250731	0	0
T10	584276	347958	0	0
T17	40378	40296	0	0