Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T3,T4,T9

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T9
0	1	Covered	T9,T17,T18
1	0	Covered	T4,T7,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T23,T24
1	1	Covered	T9,T17,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T17,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T4,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T9,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T3,T4,T9

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T9
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T18,T16,T25
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T18,T26,T27
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T26,T27,T28
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T29,T30
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T9,T18,T31
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T7,T18
TimeoutSt->Phase0St	172	Covered	T4,T9,T17

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T26,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T18,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1147	0	0
CheckAccumTrig0_A	2147483647	2324	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1069	0	0
CheckEn_A	2147483647	1138727066	0	0
CheckPhase0_A	2147483647	2640	0	0
CheckPhase1_A	2147483647	2594	0	0
CheckPhase2_A	2147483647	2558	0	0
CheckPhase3_A	2147483647	2516	0	0
CheckTimeout0_A	2147483647	3389	0	0
CheckTimeoutSt1_A	2147483647	377377	0	0
CheckTimeoutSt2_A	2147483647	3021	0	0
CheckTimeoutStTrig_A	2147483647	254	0	0
ErrorStAllEscAsserted_A	2147483647	5668	0	0
ErrorStIsTerminal_A	2147483647	4708	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T11	124572	294	0	0
T12	0	276	0	0
T13	0	171	0	0
T30	240832	0	0	0
T34	0	153	0	0
T35	0	253	0	0
T36	2363036	0	0	0
T37	528404	0	0	0
T38	3588640	0	0	0
T39	1106612	0	0	0
T40	453432	0	0	0
T41	2917808	0	0	0
T42	899448	0	0	0
T43	1408924	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2324	0	0
T1	47800	2	0	0
T2	1505421	1	0	0
T3	35622	0	0	0
T4	3967648	1	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	3	0	0
T9	1016592	8	0	0
T10	2337104	1	0	0
T14	0	1	0	0
T16	0	42	0	0
T17	161512	0	0	0
T18	1125932	20	0	0
T19	40291	0	0	0
T20	191725	1	0	0
T21	0	6	0	0
T25	0	2	0	0
T26	0	3	0	0
T31	0	13	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	15	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	1	0	0
T17	40378	0	0	0
T18	1125932	2	0	0
T19	80582	0	0	0
T20	383450	0	0	0
T27	380146	0	0	0
T31	60253	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T50	0	1	0	0
T51	986626	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	70725	0	0	0
T67	112033	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1069	0	0
T7	380288	0	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T14	2472060	0	0	0
T15	32058	0	0	0
T16	1212735	27	0	0
T17	40378	0	0	0
T18	2251864	12	0	0
T19	161164	0	0	0
T20	766900	0	0	0
T21	0	4	0	0
T25	0	1	0	0
T26	0	7	0	0
T27	0	4	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	180759	10	0	0
T32	0	1	0	0
T37	0	1	0	0
T44	20820	0	0	0
T45	148592	0	0	0
T46	183798	2	0	0
T49	0	17	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138727066	0	0
T1	95600	56421	0	0
T2	2007228	1521567	0	0
T3	47496	21132	0	0
T4	3967648	1984794	0	0
T5	3023404	1497973	0	0
T6	446432	1068858	0	0
T7	1521152	405570	0	0
T9	1016592	619375	0	0
T10	2337104	853776	0	0
T17	161512	119582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2640	0	0
T1	47800	2	0	0
T2	1505421	1	0	0
T3	35622	0	0	0
T4	3967648	2	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	3	0	0
T9	1016592	10	0	0
T10	2337104	1	0	0
T14	0	1	0	0
T16	0	29	0	0
T17	161512	1	0	0
T18	1125932	25	0	0
T19	40291	1	0	0
T20	191725	1	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	13	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T75	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2594	0	0
T1	47800	2	0	0
T2	1505421	1	0	0
T3	35622	0	0	0
T4	3967648	2	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	3	0	0
T9	1016592	10	0	0
T10	2337104	1	0	0
T14	0	1	0	0
T16	0	29	0	0
T17	161512	1	0	0
T18	1125932	22	0	0
T19	40291	1	0	0
T20	191725	1	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	13	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T75	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T1	47800	2	0	0
T2	1505421	1	0	0
T3	35622	0	0	0
T4	3967648	2	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	3	0	0
T9	1016592	10	0	0
T10	2337104	1	0	0
T14	0	1	0	0
T16	0	29	0	0
T17	161512	1	0	0
T18	1125932	22	0	0
T19	40291	1	0	0
T20	191725	1	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	13	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T75	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T1	47800	2	0	0
T2	1505421	1	0	0
T3	35622	0	0	0
T4	3967648	2	0	0
T5	3023404	0	0	0
T6	446432	1	0	0
T7	1521152	3	0	0
T9	1016592	10	0	0
T10	2337104	1	0	0
T14	0	1	0	0
T16	0	28	0	0
T17	161512	1	0	0
T18	1125932	22	0	0
T19	40291	1	0	0
T20	191725	1	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	13	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T75	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3389	0	0
T3	23748	6	0	0
T4	2975736	1	0	0
T5	2267553	0	0	0
T6	334824	0	0	0
T7	1521152	7	0	0
T9	1016592	2	0	0
T10	2337104	0	0	0
T14	618015	0	0	0
T15	0	11	0	0
T16	0	8	0	0
T17	161512	1	0	0
T18	2251864	32	0	0
T19	161164	1	0	0
T20	383450	0	0	0
T25	0	6	0	0
T26	0	7	0	0
T31	0	2	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	8	0	0
T68	0	6	0	0
T69	0	1	0	0
T71	0	4	0	0
T75	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	377377	0	0
T3	23748	460	0	0
T4	2975736	6	0	0
T5	2267553	0	0	0
T6	334824	0	0	0
T7	1521152	683	0	0
T9	1016592	984	0	0
T10	2337104	0	0	0
T14	618015	0	0	0
T15	0	809	0	0
T16	0	712	0	0
T17	161512	140	0	0
T18	2251864	4280	0	0
T19	161164	45	0	0
T20	383450	0	0	0
T25	0	235	0	0
T26	0	1025	0	0
T31	0	90	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T47	0	422	0	0
T48	0	364	0	0
T49	0	1994	0	0
T68	0	380	0	0
T69	0	28	0	0
T71	0	370	0	0
T75	0	2169	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3021	0	0
T3	11874	6	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	760576	7	0	0
T8	368660	0	0	0
T9	254148	0	0	0
T10	1168552	0	0	0
T15	10686	11	0	0
T16	404245	5	0	0
T17	80756	0	0	0
T18	1125932	24	0	0
T19	80582	0	0	0
T20	191725	0	0	0
T21	449929	0	0	0
T25	110355	6	0	0
T26	0	7	0	0
T31	120506	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T46	61266	0	0	0
T47	21117	0	0	0
T48	39064	0	0	0
T49	0	3	0	0
T51	0	4	0	0
T66	0	10	0	0
T68	0	6	0	0
T71	0	6	0	0
T72	0	82	0	0
T74	0	5	0	0
T75	72542	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	254	0	0
T7	760576	0	0	0
T9	508296	2	0	0
T10	1168552	0	0	0
T14	2472060	0	0	0
T15	21372	0	0	0
T16	404245	1	0	0
T17	121134	1	0	0
T18	2251864	2	0	0
T19	161164	1	0	0
T20	766900	0	0	0
T27	0	1	0	0
T31	120506	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	20820	0	0	0
T45	148592	0	0	0
T46	122532	0	0	0
T47	0	1	0	0
T49	0	5	0	0
T60	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5668	0	0
T11	124572	1411	0	0
T12	0	1446	0	0
T13	0	767	0	0
T30	240832	0	0	0
T34	0	689	0	0
T35	0	1355	0	0
T36	2363036	0	0	0
T37	528404	0	0	0
T38	3588640	0	0	0
T39	1106612	0	0	0
T40	453432	0	0	0
T41	2917808	0	0	0
T42	899448	0	0	0
T43	1408924	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4708	0	0
T11	124572	1171	0	0
T12	0	1206	0	0
T13	0	647	0	0
T30	240832	0	0	0
T34	0	569	0	0
T35	0	1115	0	0
T36	2363036	0	0	0
T37	528404	0	0	0
T38	3588640	0	0	0
T39	1106612	0	0	0
T40	453432	0	0	0
T41	2917808	0	0	0
T42	899448	0	0	0
T43	1408924	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	95600	95260	0	0
T2	2007228	2006876	0	0
T3	47496	47296	0	0
T4	3967648	3967256	0	0
T5	3023404	3023020	0	0
T6	446432	446400	0	0
T7	1521152	1521132	0	0
T9	1016592	1016556	0	0
T10	2337104	2336888	0	0
T17	161512	161184	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	95600	95260	0	0
T2	2007228	2006876	0	0
T3	47496	47296	0	0
T4	3967648	3967256	0	0
T5	3023404	3023020	0	0
T6	446432	446400	0	0
T7	1521152	1521132	0	0
T9	1016592	1016556	0	0
T10	2337104	2336888	0	0
T17	161512	161184	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T9
1	0	1	Covered	T5,T9,T16
1	1	0	Covered	T1,T9,T7
1	1	1	Covered	T3,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T17,T18
0	1	Covered	T17,T18,T19
1	0	Covered	T18,T50,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T50,T38

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T18
1	0	Not Covered
1	1	Covered	T17,T18,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T9,T17,T18
1	Covered	T4,T6,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T9
1	Covered	T17,T18,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T9
1	Covered	T9,T18,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T9
1	Covered	T9,T18,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T9,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T9,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T6,T9
Phase1St	198	Covered	T4,T6,T9
Phase2St	215	Covered	T4,T6,T9
Phase3St	233	Covered	T4,T6,T9
TerminalSt	249	Covered	T4,T6,T9
TimeoutSt	159	Covered	T3,T17,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T6,T9
IdleSt->TimeoutSt	159	Covered	T3,T17,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T18,T16,T37
Phase0St->Phase1St	198	Covered	T4,T6,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T53,T81
Phase1St->Phase2St	215	Covered	T4,T6,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T28,T77
Phase2St->Phase3St	233	Covered	T4,T6,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T82,T33
Phase3St->TerminalSt	249	Covered	T4,T6,T9
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T18,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T18,T15
TimeoutSt->Phase0St	172	Covered	T17,T18,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T83,T63
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T6,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T53,T81
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T6,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T6,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T28,T77
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T6,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T6,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T82,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T6,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T6,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T18,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	669010952	294	0	0
CheckAccumTrig0_A	669010952	815	0	0
CheckAccumTrig1_A	669010952	45	0	0
CheckClr_A	669010952	378	0	0
CheckEn_A	668474116	277415421	0	0
CheckPhase0_A	669010952	899	0	0
CheckPhase1_A	669010952	882	0	0
CheckPhase2_A	669010952	864	0	0
CheckPhase3_A	669010952	850	0	0
CheckTimeout0_A	669010952	928	0	0
CheckTimeoutSt1_A	669010952	98894	0	0
CheckTimeoutSt2_A	669010952	820	0	0
CheckTimeoutStTrig_A	669010952	62	0	0
ErrorStAllEscAsserted_A	669010952	1458	0	0
ErrorStIsTerminal_A	669010952	1218	0	0
EscStateOut_A	668472681	668399953	0	0
u_state_regs_A	669010952	668836815	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	294	0	0
T11	31143	69	0	0
T12	0	70	0	0
T13	0	59	0	0
T30	60208	0	0	0
T34	0	37	0	0
T35	0	59	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	815	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	4	0	0
T10	584276	0	0	0
T16	0	16	0	0
T17	40378	0	0	0
T18	562966	6	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T21	0	1	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	45	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	0	0	0
T18	562966	1	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T31	60253	0	0	0
T38	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T50	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	378	0	0
T7	380288	0	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T16	0	10	0	0
T17	40378	0	0	0
T18	562966	2	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	0	2	0	0
T49	0	4	0	0
T70	0	4	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668474116	277415421	0	0
T1	23900	23814	0	0
T2	501807	501718	0	0
T3	11874	1700	0	0
T4	991912	582	0	0
T5	755851	40550	0	0
T6	111608	582	0	0
T7	380288	379285	0	0
T9	254148	105028	0	0
T10	584276	619	0	0
T17	40378	1994	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	899	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	4	0	0
T10	584276	0	0	0
T17	40378	1	0	0
T18	562966	7	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	882	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	4	0	0
T10	584276	0	0	0
T17	40378	1	0	0
T18	562966	7	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	864	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	4	0	0
T10	584276	0	0	0
T17	40378	1	0	0
T18	562966	7	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	850	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	1	0	0
T7	380288	0	0	0
T9	254148	4	0	0
T10	584276	0	0	0
T17	40378	1	0	0
T18	562966	7	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	928	0	0
T3	11874	2	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	6	0	0
T16	0	1	0	0
T17	40378	1	0	0
T18	562966	20	0	0
T19	40291	1	0	0
T25	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	98894	0	0
T3	11874	137	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	423	0	0
T16	0	41	0	0
T17	40378	140	0	0
T18	562966	3163	0	0
T19	40291	45	0	0
T25	0	51	0	0
T47	0	422	0	0
T49	0	729	0	0
T75	0	383	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	820	0	0
T3	11874	2	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	6	0	0
T16	0	1	0	0
T17	40378	0	0	0
T18	562966	18	0	0
T19	40291	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T51	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T74	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	62	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T17	40378	1	0	0
T18	562966	1	0	0
T19	40291	1	0	0
T20	191725	0	0	0
T31	60253	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T68	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1458	0	0
T11	31143	374	0	0
T12	0	371	0	0
T13	0	214	0	0
T30	60208	0	0	0
T34	0	179	0	0
T35	0	320	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1218	0	0
T11	31143	314	0	0
T12	0	311	0	0
T13	0	184	0	0
T30	60208	0	0	0
T34	0	149	0	0
T35	0	260	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668472681	668399953	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	668836815	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T9,T14,T25
1	1	0	Covered	T9,T18,T15
1	1	1	Covered	T4,T9,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T18
0	1	Covered	T9,T49,T27
1	0	Covered	T4,T18,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T9,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T18
1	0	Covered	T24
1	1	Covered	T9,T49,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T10,T18,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T9,T16,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T7,T31,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T7,T10
1	Covered	T1,T4,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T9,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T9,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T9
Phase1St	198	Covered	T1,T4,T9
Phase2St	215	Covered	T1,T4,T9
Phase3St	233	Covered	T1,T4,T9
TerminalSt	249	Covered	T1,T4,T9
TimeoutSt	159	Covered	T4,T9,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T9,T7
IdleSt->TimeoutSt	159	Covered	T4,T9,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T83,T84,T85
Phase0St->Phase1St	198	Covered	T1,T4,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T27,T86
Phase1St->Phase2St	215	Covered	T1,T4,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T86,T84
Phase2St->Phase3St	233	Covered	T1,T4,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T87,T81
Phase3St->TerminalSt	249	Covered	T1,T4,T9
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T18,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T31,T16
TimeoutSt->Phase0St	172	Covered	T4,T9,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T31,T16,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T83,T84,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T27,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T86,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T87,T81
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T31,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	669010952	292	0	0
CheckAccumTrig0_A	669010952	499	0	0
CheckAccumTrig1_A	669010952	19	0	0
CheckClr_A	669010952	243	0	0
CheckEn_A	668474116	295222770	0	0
CheckPhase0_A	669010952	579	0	0
CheckPhase1_A	669010952	566	0	0
CheckPhase2_A	669010952	557	0	0
CheckPhase3_A	669010952	544	0	0
CheckTimeout0_A	669010952	1279	0	0
CheckTimeoutSt1_A	669010952	123848	0	0
CheckTimeoutSt2_A	669010952	1186	0	0
CheckTimeoutStTrig_A	669010952	69	0	0
ErrorStAllEscAsserted_A	669010952	1387	0	0
ErrorStIsTerminal_A	669010952	1147	0	0
EscStateOut_A	668472681	668399953	0	0
u_state_regs_A	669010952	668836815	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	292	0	0
T11	31143	85	0	0
T12	0	46	0	0
T13	0	35	0	0
T30	60208	0	0	0
T34	0	61	0	0
T35	0	65	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	499	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	40378	0	0	0
T18	0	5	0	0
T31	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	19	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T16	0	1	0	0
T17	40378	0	0	0
T18	562966	1	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T42	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	243	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	1	0	0
T18	562966	3	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	60253	2	0	0
T37	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T49	0	2	0	0
T72	0	1	0	0
T74	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668474116	295222770	0	0
T1	23900	2170	0	0
T2	501807	501718	0	0
T3	11874	6969	0	0
T4	991912	586	0	0
T5	755851	661111	0	0
T6	111608	111600	0	0
T7	380288	2063	0	0
T9	254148	127292	0	0
T10	584276	623	0	0
T17	40378	36998	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	579	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	3	0	0
T10	584276	1	0	0
T14	0	1	0	0
T16	0	4	0	0
T17	40378	0	0	0
T18	0	6	0	0
T31	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	566	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	3	0	0
T10	584276	1	0	0
T14	0	1	0	0
T16	0	4	0	0
T17	40378	0	0	0
T18	0	5	0	0
T31	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	557	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	3	0	0
T10	584276	1	0	0
T14	0	1	0	0
T16	0	4	0	0
T17	40378	0	0	0
T18	0	5	0	0
T31	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	544	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	3	0	0
T10	584276	1	0	0
T14	0	1	0	0
T16	0	4	0	0
T17	40378	0	0	0
T18	0	5	0	0
T31	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1279	0	0
T4	991912	1	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T16	0	2	0	0
T17	40378	0	0	0
T18	562966	2	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T25	0	3	0	0
T26	0	2	0	0
T31	0	1	0	0
T49	0	1	0	0
T68	0	2	0	0
T71	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	123848	0	0
T4	991912	6	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	602	0	0
T10	584276	0	0	0
T16	0	221	0	0
T17	40378	0	0	0
T18	562966	75	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T25	0	153	0	0
T26	0	285	0	0
T31	0	52	0	0
T49	0	23	0	0
T68	0	157	0	0
T71	0	370	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1186	0	0
T8	368660	0	0	0
T15	10686	0	0	0
T16	404245	1	0	0
T21	449929	0	0	0
T25	110355	3	0	0
T26	0	2	0	0
T31	60253	1	0	0
T37	0	1	0	0
T46	61266	0	0	0
T47	21117	0	0	0
T48	39064	0	0	0
T66	0	2	0	0
T68	0	2	0	0
T71	0	4	0	0
T72	0	82	0	0
T74	0	3	0	0
T75	72542	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	69	0	0
T7	380288	0	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T17	40378	0	0	0
T18	562966	0	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T27	0	1	0	0
T42	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T49	0	1	0	0
T60	0	1	0	0
T74	0	4	0	0
T77	0	3	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1387	0	0
T11	31143	353	0	0
T12	0	322	0	0
T13	0	188	0	0
T30	60208	0	0	0
T34	0	177	0	0
T35	0	347	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1147	0	0
T11	31143	293	0	0
T12	0	262	0	0
T13	0	158	0	0
T30	60208	0	0	0
T34	0	147	0	0
T35	0	287	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668472681	668399953	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	668836815	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T7
1	0	1	Covered	T5,T9,T16
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T9,T7,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T9,T7,T18
0	1	Covered	T9,T18,T16
1	0	Covered	T7,T51,T60

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T9,T7,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T51,T60

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T7,T18
1	0	Covered	T23
1	1	Covered	T9,T18,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T18
1	Covered	T9,T18,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T16,T47,T75

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T18,T31
1	Covered	T1,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T18,T49,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T18,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T7,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T18,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T9,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T9,T7
Phase1St	198	Covered	T1,T9,T7
Phase2St	215	Covered	T1,T9,T7
Phase3St	233	Covered	T1,T9,T7
TerminalSt	249	Covered	T1,T9,T7
TimeoutSt	159	Covered	T9,T7,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T7,T18
IdleSt->TimeoutSt	159	Covered	T9,T7,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T18,T25,T32
Phase0St->Phase1St	198	Covered	T1,T9,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T89,T90
Phase1St->Phase2St	215	Covered	T1,T9,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T91,T92,T93
Phase2St->Phase3St	233	Covered	T1,T9,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T30,T85
Phase3St->TerminalSt	249	Covered	T1,T9,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T18,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T18,T15
TimeoutSt->Phase0St	172	Covered	T9,T18,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T7,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T9,T7,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T9,T7,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T32,T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T9,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T9,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T90,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T9,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T9,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T9,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T9,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T30,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T9,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T9,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T31,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	669010952	258	0	0
CheckAccumTrig0_A	669010952	471	0	0
CheckAccumTrig1_A	669010952	12	0	0
CheckClr_A	669010952	199	0	0
CheckEn_A	668474116	296142210	0	0
CheckPhase0_A	669010952	552	0	0
CheckPhase1_A	669010952	544	0	0
CheckPhase2_A	669010952	539	0	0
CheckPhase3_A	669010952	533	0	0
CheckTimeout0_A	669010952	643	0	0
CheckTimeoutSt1_A	669010952	88677	0	0
CheckTimeoutSt2_A	669010952	552	0	0
CheckTimeoutStTrig_A	669010952	79	0	0
ErrorStAllEscAsserted_A	669010952	1417	0	0
ErrorStIsTerminal_A	669010952	1177	0	0
EscStateOut_A	668472681	668399953	0	0
u_state_regs_A	669010952	668836815	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	258	0	0
T11	31143	60	0	0
T12	0	75	0	0
T13	0	30	0	0
T30	60208	0	0	0
T34	0	34	0	0
T35	0	59	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	471	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T16	0	17	0	0
T17	40378	0	0	0
T18	0	6	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	3	0	0
T31	0	7	0	0
T47	0	1	0	0
T49	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	12	0	0
T27	380146	0	0	0
T29	958922	0	0	0
T51	986626	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	70725	0	0	0
T67	112033	0	0	0
T72	275164	0	0	0
T73	23236	0	0	0
T74	239609	0	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	88962	0	0	0
T103	42775	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	199	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	14	0	0
T18	562966	3	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T21	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	60253	6	0	0
T32	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T49	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668474116	296142210	0	0
T1	23900	6623	0	0
T2	501807	501718	0	0
T3	11874	11823	0	0
T4	991912	991813	0	0
T5	755851	40558	0	0
T6	111608	100861	0	0
T7	380288	10095	0	0
T9	254148	222994	0	0
T10	584276	504577	0	0
T17	40378	40295	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	552	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T16	0	18	0	0
T17	40378	0	0	0
T18	0	6	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	7	0	0
T47	0	1	0	0
T75	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	544	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T16	0	18	0	0
T17	40378	0	0	0
T18	0	5	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	7	0	0
T47	0	1	0	0
T75	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	539	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T16	0	18	0	0
T17	40378	0	0	0
T18	0	5	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	7	0	0
T47	0	1	0	0
T75	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	533	0	0
T1	23900	1	0	0
T2	501807	0	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T16	0	17	0	0
T17	40378	0	0	0
T18	0	5	0	0
T21	0	4	0	0
T25	0	1	0	0
T31	0	7	0	0
T47	0	1	0	0
T75	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	643	0	0
T7	380288	7	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T15	0	4	0	0
T16	0	2	0	0
T17	40378	0	0	0
T18	562966	3	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T26	0	3	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T49	0	6	0	0
T68	0	2	0	0
T69	0	1	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	88677	0	0
T7	380288	683	0	0
T9	254148	382	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T15	0	295	0	0
T16	0	59	0	0
T17	40378	0	0	0
T18	562966	190	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T26	0	518	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T49	0	1242	0	0
T68	0	130	0	0
T69	0	28	0	0
T75	0	1738	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	552	0	0
T7	380288	7	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	40378	0	0	0
T18	562966	2	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T26	0	3	0	0
T31	60253	0	0	0
T32	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T49	0	3	0	0
T68	0	2	0	0
T71	0	2	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	79	0	0
T7	380288	0	0	0
T9	254148	1	0	0
T10	584276	0	0	0
T14	618015	0	0	0
T16	0	1	0	0
T17	40378	0	0	0
T18	562966	1	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T32	0	1	0	0
T42	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T49	0	3	0	0
T52	0	3	0	0
T69	0	1	0	0
T75	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1417	0	0
T11	31143	350	0	0
T12	0	384	0	0
T13	0	185	0	0
T30	60208	0	0	0
T34	0	166	0	0
T35	0	332	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1177	0	0
T11	31143	290	0	0
T12	0	324	0	0
T13	0	155	0	0
T30	60208	0	0	0
T34	0	136	0	0
T35	0	272	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668472681	668399953	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	668836815	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T2,T6,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T2,T6,T20
1	1	0	Covered	T1,T4,T9
1	1	1	Covered	T3,T18,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T18,T31
0	1	Covered	T18,T16,T75
1	0	Covered	T18,T26,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T18,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T26,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T31
1	0	Not Covered
1	1	Covered	T18,T16,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T9,T18
1	Covered	T9,T7,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T9,T7
1	Covered	T18,T16,T75

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T9,T7
1	Covered	T18,T16,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T7,T18
1	Covered	T2,T9,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T18,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T18,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T18,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T7,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T9,T7
Phase1St	198	Covered	T2,T9,T7
Phase2St	215	Covered	T2,T9,T7
Phase3St	233	Covered	T2,T9,T7
TerminalSt	249	Covered	T2,T9,T7
TimeoutSt	159	Covered	T3,T18,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T9,T7
IdleSt->TimeoutSt	159	Covered	T3,T18,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T42,T84,T105
Phase0St->Phase1St	198	Covered	T2,T9,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T77,T106
Phase1St->Phase2St	215	Covered	T2,T9,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T107,T94
Phase2St->Phase3St	233	Covered	T2,T9,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T108,T109
Phase3St->TerminalSt	249	Covered	T2,T9,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T18,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T18,T31
TimeoutSt->Phase0St	172	Covered	T18,T16,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T16,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T9,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T9,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T77,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T9,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T9,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T107,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T9,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T9,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T9,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T9,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T31,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T9,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	669010952	303	0	0
CheckAccumTrig0_A	669010952	539	0	0
CheckAccumTrig1_A	669010952	30	0	0
CheckClr_A	669010952	249	0	0
CheckEn_A	668474116	269946665	0	0
CheckPhase0_A	669010952	610	0	0
CheckPhase1_A	669010952	602	0	0
CheckPhase2_A	669010952	598	0	0
CheckPhase3_A	669010952	589	0	0
CheckTimeout0_A	669010952	539	0	0
CheckTimeoutSt1_A	669010952	65958	0	0
CheckTimeoutSt2_A	669010952	463	0	0
CheckTimeoutStTrig_A	669010952	44	0	0
ErrorStAllEscAsserted_A	669010952	1406	0	0
ErrorStIsTerminal_A	669010952	1166	0	0
EscStateOut_A	668472681	668399953	0	0
u_state_regs_A	669010952	668836815	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	303	0	0
T11	31143	80	0	0
T12	0	85	0	0
T13	0	47	0	0
T30	60208	0	0	0
T34	0	21	0	0
T35	0	70	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	539	0	0
T2	501807	1	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	0	0	0
T16	0	6	0	0
T17	40378	0	0	0
T18	562966	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	0	2	0	0
T44	0	1	0	0
T49	0	13	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	30	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	0	0	0
T18	562966	1	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T26	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	60253	0	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T62	0	2	0	0
T71	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	249	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	2	0	0
T18	562966	4	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T21	0	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	60253	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T49	0	9	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668474116	269946665	0	0
T1	23900	23814	0	0
T2	501807	16413	0	0
T3	11874	640	0	0
T4	991912	991813	0	0
T5	755851	755754	0	0
T6	111608	855815	0	0
T7	380288	14127	0	0
T9	254148	164061	0	0
T10	584276	347957	0	0
T17	40378	40295	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	610	0	0
T2	501807	1	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	0	0	0
T16	0	7	0	0
T17	40378	0	0	0
T18	562966	6	0	0
T20	0	1	0	0
T31	0	2	0	0
T44	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	602	0	0
T2	501807	1	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	0	0	0
T16	0	7	0	0
T17	40378	0	0	0
T18	562966	5	0	0
T20	0	1	0	0
T31	0	2	0	0
T44	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	598	0	0
T2	501807	1	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	0	0	0
T16	0	7	0	0
T17	40378	0	0	0
T18	562966	5	0	0
T20	0	1	0	0
T31	0	2	0	0
T44	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	589	0	0
T2	501807	1	0	0
T3	11874	0	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	1	0	0
T9	254148	2	0	0
T10	584276	0	0	0
T16	0	7	0	0
T17	40378	0	0	0
T18	562966	5	0	0
T20	0	1	0	0
T31	0	2	0	0
T44	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	539	0	0
T3	11874	4	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	40378	0	0	0
T18	562966	7	0	0
T19	40291	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T31	0	1	0	0
T48	0	1	0	0
T68	0	2	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	65958	0	0
T3	11874	323	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	91	0	0
T16	0	391	0	0
T17	40378	0	0	0
T18	562966	852	0	0
T19	40291	0	0	0
T25	0	31	0	0
T26	0	222	0	0
T31	0	38	0	0
T48	0	364	0	0
T68	0	93	0	0
T75	0	48	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	463	0	0
T3	11874	4	0	0
T4	991912	0	0	0
T5	755851	0	0	0
T6	111608	0	0	0
T7	380288	0	0	0
T9	254148	0	0	0
T10	584276	0	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	40378	0	0	0
T18	562966	4	0	0
T19	40291	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	1	0	0
T51	0	3	0	0
T66	0	7	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	44	0	0
T14	618015	0	0	0
T15	10686	0	0	0
T16	404245	1	0	0
T18	562966	2	0	0
T19	40291	0	0	0
T20	191725	0	0	0
T31	60253	0	0	0
T32	0	1	0	0
T42	0	1	0	0
T44	5205	0	0	0
T45	37148	0	0	0
T46	61266	0	0	0
T48	0	1	0	0
T53	0	1	0	0
T68	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T112	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1406	0	0
T11	31143	334	0	0
T12	0	369	0	0
T13	0	180	0	0
T30	60208	0	0	0
T34	0	167	0	0
T35	0	356	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	1166	0	0
T11	31143	274	0	0
T12	0	309	0	0
T13	0	150	0	0
T30	60208	0	0	0
T34	0	137	0	0
T35	0	296	0	0
T36	590759	0	0	0
T37	132101	0	0	0
T38	897160	0	0	0
T39	276653	0	0	0
T40	113358	0	0	0
T41	729452	0	0	0
T42	224862	0	0	0
T43	352231	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668472681	668399953	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669010952	668836815	0	0
T1	23900	23815	0	0
T2	501807	501719	0	0
T3	11874	11824	0	0
T4	991912	991814	0	0
T5	755851	755755	0	0
T6	111608	111600	0	0
T7	380288	380283	0	0
T9	254148	254139	0	0
T10	584276	584222	0	0
T17	40378	40296	0	0