Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64671098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31348382

1

T1

1009

T2

83

T3

1119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14463673	1			T1	400		T2	28		T3	890
values[0x0]	39783653	1			T1	1294		T2	160		T3	1081
values[0x1]	41772154	1			T1	1368		T2	160		T3	1073

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55250274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40769206

1

T1

1267

T2

112

T3

1367

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	310169	1			T3	5		T4	1843		T5	1369
valid_sources[0x01]	303575	1			T2	1		T3	9		T4	1883
valid_sources[0x02]	302390	1			T3	15		T4	1903		T5	1441
valid_sources[0x03]	332207	1			T2	3		T3	17		T4	1845
valid_sources[0x04]	807551	1			T2	1		T3	10		T4	1889
valid_sources[0x05]	306550	1			T3	8		T4	1878		T5	1506
valid_sources[0x06]	301179	1			T3	11		T4	1879		T5	1526
valid_sources[0x07]	308398	1			T2	1		T3	14		T4	1868
valid_sources[0x08]	304089	1			T2	1		T3	15		T4	1865
valid_sources[0x09]	309824	1			T3	7		T4	1793		T5	1483
valid_sources[0x0a]	309752	1			T2	1		T3	2		T4	2004
valid_sources[0x0b]	302297	1			T2	3		T3	4		T4	1842
valid_sources[0x0c]	303536	1			T3	2		T4	1795		T5	1470
valid_sources[0x0d]	560102	1			T3	10		T4	1827		T5	1493
valid_sources[0x0e]	728045	1			T2	1		T3	24		T4	1831
valid_sources[0x0f]	606434	1			T3	18		T4	1841		T5	1451
valid_sources[0x10]	308114	1			T2	3		T3	17		T4	1790
valid_sources[0x11]	315276	1			T2	1		T3	4		T4	1752
valid_sources[0x12]	708363	1			T2	1		T3	12		T4	1811
valid_sources[0x13]	314615	1			T2	1		T3	4		T4	1829
valid_sources[0x14]	307332	1			T2	2		T3	10		T4	1766
valid_sources[0x15]	343058	1			T2	2		T3	15		T4	1807
valid_sources[0x16]	302587	1			T2	3		T3	19		T4	1881
valid_sources[0x17]	524928	1			T3	11		T4	1835		T5	1558
valid_sources[0x18]	305318	1			T2	2		T3	4		T4	1881
valid_sources[0x19]	308367	1			T2	2		T3	8		T4	1892
valid_sources[0x1a]	316333	1			T3	8		T4	1847		T5	1430
valid_sources[0x1b]	309979	1			T2	2		T3	10		T4	1835
valid_sources[0x1c]	311772	1			T3	6		T4	1813		T5	1448
valid_sources[0x1d]	333418	1			T2	2		T3	10		T4	1844
valid_sources[0x1e]	517899	1			T2	1		T3	3		T4	1829
valid_sources[0x1f]	528327	1			T2	4		T3	12		T4	1798
valid_sources[0x20]	307114	1			T2	1		T3	18		T4	1866
valid_sources[0x21]	309932	1			T3	7		T4	1802		T5	1432
valid_sources[0x22]	305803	1			T2	2		T3	18		T4	1818
valid_sources[0x23]	312053	1			T2	3		T3	8		T4	1843
valid_sources[0x24]	309594	1			T2	1		T3	10		T4	1795
valid_sources[0x25]	311924	1			T2	1		T3	11		T4	1841
valid_sources[0x26]	557811	1			T3	11		T4	1789		T5	1457
valid_sources[0x27]	300717	1			T2	3		T3	11		T4	1816
valid_sources[0x28]	304288	1			T2	2		T3	14		T4	1820
valid_sources[0x29]	301019	1			T2	1		T3	5		T4	1771
valid_sources[0x2a]	313074	1			T3	6		T4	1878		T5	1528
valid_sources[0x2b]	313172	1			T2	2		T3	17		T4	1803
valid_sources[0x2c]	308656	1			T2	2		T3	11		T4	1769
valid_sources[0x2d]	306258	1			T2	3		T3	10		T4	1802
valid_sources[0x2e]	306625	1			T3	12		T4	1964		T5	1509
valid_sources[0x2f]	303448	1			T3	11		T4	1773		T5	1465
valid_sources[0x30]	325680	1			T3	6		T4	1843		T5	1512
valid_sources[0x31]	559990	1			T2	1		T3	9		T4	1862
valid_sources[0x32]	307090	1			T2	1		T3	7		T4	1851
valid_sources[0x33]	320647	1			T3	25		T4	1802		T5	1502
valid_sources[0x34]	308292	1			T3	6		T4	1884		T5	1371
valid_sources[0x35]	681520	1			T3	11		T4	1858		T5	1513
valid_sources[0x36]	324273	1			T2	1		T3	9		T4	1735
valid_sources[0x37]	697155	1			T3	13		T4	1767		T5	1488
valid_sources[0x38]	774198	1			T2	1		T3	23		T4	1862
valid_sources[0x39]	305648	1			T3	12		T4	1906		T5	1513
valid_sources[0x3a]	548459	1			T2	1		T3	14		T4	1805
valid_sources[0x3b]	606344	1			T3	8		T4	1785		T5	1502
valid_sources[0x3c]	339767	1			T2	1		T3	6		T4	1797
valid_sources[0x3d]	300032	1			T3	15		T4	1806		T5	1449
valid_sources[0x3e]	705828	1			T2	2		T3	25		T4	1850
valid_sources[0x3f]	300907	1			T3	13		T4	1894		T5	1400
valid_sources[0x40]	305234	1			T2	3		T3	8		T4	1892
valid_sources[0x41]	945271	1			T2	3		T3	7		T4	1882
valid_sources[0x42]	306917	1			T3	6		T4	1921		T5	1402
valid_sources[0x43]	779884	1			T2	1		T3	10		T4	1894
valid_sources[0x44]	311709	1			T2	1		T3	10		T4	1790
valid_sources[0x45]	312096	1			T2	3		T3	10		T4	1831
valid_sources[0x46]	306533	1			T3	9		T4	1794		T5	1492
valid_sources[0x47]	316676	1			T2	1		T3	15		T4	1756
valid_sources[0x48]	645466	1			T2	2		T3	7		T4	1863
valid_sources[0x49]	309966	1			T2	1		T3	13		T4	1953
valid_sources[0x4a]	310605	1			T2	1		T3	14		T4	1843
valid_sources[0x4b]	303375	1			T2	2		T3	4		T4	1774
valid_sources[0x4c]	302568	1			T2	2		T3	17		T4	1774
valid_sources[0x4d]	315718	1			T2	2		T3	12		T4	1835
valid_sources[0x4e]	312084	1			T3	7		T4	1733		T5	1438
valid_sources[0x4f]	302775	1			T3	8		T4	1933		T5	1506
valid_sources[0x50]	356638	1			T2	1		T3	10		T4	1837
valid_sources[0x51]	305324	1			T2	1		T3	15		T4	1825
valid_sources[0x52]	519332	1			T2	5		T3	18		T4	1892
valid_sources[0x53]	312017	1			T2	1		T3	10		T4	1800
valid_sources[0x54]	306696	1			T2	1		T3	13		T4	1849
valid_sources[0x55]	307553	1			T3	9		T4	1831		T5	1532
valid_sources[0x56]	303084	1			T2	1		T3	18		T4	1863
valid_sources[0x57]	310398	1			T2	3		T3	15		T4	1866
valid_sources[0x58]	310647	1			T2	3		T3	9		T4	1767
valid_sources[0x59]	301753	1			T2	1		T3	19		T4	1814
valid_sources[0x5a]	302522	1			T3	5		T4	1888		T5	1488
valid_sources[0x5b]	302591	1			T3	13		T4	1884		T5	1455
valid_sources[0x5c]	295705	1			T3	14		T4	1871		T5	1429
valid_sources[0x5d]	319281	1			T2	1		T3	12		T4	1785
valid_sources[0x5e]	303471	1			T2	2		T3	20		T4	1819
valid_sources[0x5f]	701518	1			T2	1		T3	2		T4	1830
valid_sources[0x60]	307338	1			T2	1		T3	12		T4	1902
valid_sources[0x61]	669153	1			T2	2		T3	13		T4	1839
valid_sources[0x62]	300953	1			T2	1		T3	11		T4	1734
valid_sources[0x63]	300077	1			T2	1		T3	4		T4	1867
valid_sources[0x64]	305083	1			T3	2		T4	1913		T5	1492
valid_sources[0x65]	300994	1			T2	1		T3	20		T4	1821
valid_sources[0x66]	314744	1			T2	1		T3	13		T4	1819
valid_sources[0x67]	701916	1			T2	2		T3	18		T4	1796
valid_sources[0x68]	1000174	1			T3	11		T4	1873		T5	1359
valid_sources[0x69]	316506	1			T2	2		T3	9		T4	1859
valid_sources[0x6a]	726330	1			T2	1		T3	16		T4	1897
valid_sources[0x6b]	308706	1			T3	15		T4	1796		T5	1519
valid_sources[0x6c]	299798	1			T2	1		T3	6		T4	1826
valid_sources[0x6d]	316758	1			T2	3		T3	7		T4	1839
valid_sources[0x6e]	308390	1			T2	1		T3	23		T4	1773
valid_sources[0x6f]	303397	1			T3	5		T4	1848		T5	1565
valid_sources[0x70]	309897	1			T2	1		T3	7		T4	1897
valid_sources[0x71]	570565	1			T2	2		T3	14		T4	1896
valid_sources[0x72]	821636	1			T3	21		T4	1872		T5	1439
valid_sources[0x73]	592573	1			T2	5		T3	25		T4	1846
valid_sources[0x74]	522192	1			T2	1		T3	15		T4	1895
valid_sources[0x75]	305265	1			T2	2		T3	10		T4	1765
valid_sources[0x76]	949279	1			T3	18		T4	1880		T5	1465
valid_sources[0x77]	304768	1			T2	2		T3	16		T4	1832
valid_sources[0x78]	312187	1			T2	1		T3	21		T4	1918
valid_sources[0x79]	308558	1			T2	2		T3	16		T4	1726
valid_sources[0x7a]	299276	1			T2	1		T3	12		T4	1870
valid_sources[0x7b]	590264	1			T2	1		T3	13		T4	1918
valid_sources[0x7c]	772437	1			T2	3		T3	9		T4	1894
valid_sources[0x7d]	306877	1			T2	1		T3	16		T4	1767
valid_sources[0x7e]	304548	1			T2	3		T3	6		T4	1870
valid_sources[0x7f]	314063	1			T2	1		T3	16		T4	1829
valid_sources[0x80]	308842	1			T3	10		T4	1792		T5	1403

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7202757

1

T1

206

T2

13

T3

442

values[0x0]

all_enables

biggest_size

15242697

1

T1

510

T2

45

T3

418

values[0x1]

all_enables

biggest_size

8902928

1

T1

293

T2

25

T3

259