Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T19,T39
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11966	0	0
DisabledNoTrigBkwd_A	2147483647	759084	0	0
DisabledNoTrigFwd_A	2147483647	1629459966	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11966	0	0
T2	2843	538	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	356622	0	0	0
T15	602416	0	0	0
T19	7276	358	0	0
T20	25362	0	0	0
T21	8692	0	0	0
T22	50104	0	0	0
T39	0	644	0	0
T67	16759	0	0	0
T68	835650	0	0	0
T102	13945	0	0	0
T167	0	885	0	0
T168	0	875	0	0
T182	2728	480	0	0
T183	0	734	0	0
T184	0	844	0	0
T185	0	600	0	0
T186	0	533	0	0
T187	0	635	0	0
T188	0	450	0	0
T189	0	1034	0	0
T190	0	613	0	0
T191	0	262	0	0
T192	0	425	0	0
T193	0	254	0	0
T194	0	969	0	0
T195	0	419	0	0
T196	0	414	0	0
T197	25217	0	0	0
T198	325523	0	0	0
T199	78030	0	0	0
T200	99634	0	0	0
T201	567259	0	0	0
T202	133718	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	759084	0	0
T2	2843	10	0	0
T3	14130	19	0	0
T4	355803	8333	0	0
T5	1276868	3173	0	0
T6	1914224	8091	0	0
T7	713244	751	0	0
T8	386784	364	0	0
T15	1204832	942	0	0
T16	0	2660	0	0
T17	0	4498	0	0
T19	14552	4	0	0
T20	50724	210	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	94	0	0
T33	0	9	0	0
T35	0	7522	0	0
T38	0	15	0	0
T39	0	15	0	0
T40	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1629459966	0	0
T1	39988	20700	0	0
T2	11372	8517	0	0
T3	28260	21620	0	0
T4	474404	131301	0	0
T5	1276868	690997	0	0
T6	1914224	969302	0	0
T7	713244	366501	0	0
T15	1204832	1192516	0	0
T19	14552	12352	0	0
T20	50724	29659	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T182,T189,T191
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	732120420	2030	0	0
DisabledNoTrigBkwd_A	732120420	214650	0	0
DisabledNoTrigFwd_A	732120420	412240854	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	2030	0	0
T67	16759	0	0	0
T68	835650	0	0	0
T102	13945	0	0	0
T182	2728	480	0	0
T189	0	1034	0	0
T191	0	262	0	0
T193	0	254	0	0
T197	25217	0	0	0
T198	325523	0	0	0
T199	78030	0	0	0
T200	99634	0	0	0
T201	567259	0	0	0
T202	133718	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	214650	0	0
T3	7065	19	0	0
T4	118601	3232	0	0
T5	319217	1060	0	0
T6	478556	5699	0	0
T7	178311	0	0	0
T8	0	364	0	0
T15	301208	428	0	0
T16	0	3	0	0
T17	0	676	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	72	0	0
T33	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	412240854	0	0
T1	9997	7674	0	0
T2	2843	2111	0	0
T3	7065	596	0	0
T4	118601	3193	0	0
T5	319217	30474	0	0
T6	478556	13478	0	0
T7	178311	177998	0	0
T15	301208	492026	0	0
T19	3638	3044	0	0
T20	12681	2199	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T39,T185
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	732120420	4386	0	0
DisabledNoTrigBkwd_A	732120420	191924	0	0
DisabledNoTrigFwd_A	732120420	414006679	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	4386	0	0
T2	2843	538	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T39	0	644	0	0
T167	0	885	0	0
T168	0	875	0	0
T185	0	600	0	0
T192	0	425	0	0
T195	0	419	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	191924	0	0
T2	2843	10	0	0
T3	7065	0	0	0
T4	118601	2504	0	0
T5	319217	6	0	0
T6	478556	9	0	0
T7	178311	3	0	0
T15	301208	88	0	0
T16	0	965	0	0
T17	0	1975	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	2	0	0
T39	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	414006679	0	0
T1	9997	2083	0	0
T2	2843	2118	0	0
T3	7065	7008	0	0
T4	118601	3197	0	0
T5	319217	317163	0	0
T6	478556	475337	0	0
T7	178311	597	0	0
T15	301208	194010	0	0
T19	3638	3070	0	0
T20	12681	12616	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T183,T186
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	732120420	3643	0	0
DisabledNoTrigBkwd_A	732120420	165648	0	0
DisabledNoTrigFwd_A	732120420	416985617	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	3643	0	0
T7	178311	0	0	0
T8	386784	0	0	0
T15	301208	0	0	0
T19	3638	358	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T39	2905	0	0	0
T61	35158	0	0	0
T183	0	734	0	0
T186	0	533	0	0
T187	0	635	0	0
T194	0	969	0	0
T196	0	414	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	165648	0	0
T4	118601	2597	0	0
T5	319217	2097	0	0
T6	478556	2374	0	0
T7	178311	0	0	0
T15	301208	277	0	0
T16	0	8	0	0
T17	0	1278	0	0
T19	3638	4	0	0
T20	12681	207	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	2346	0	0
T40	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	416985617	0	0
T1	9997	7674	0	0
T2	2843	2139	0	0
T3	7065	7008	0	0
T4	118601	6461	0	0
T5	319217	26199	0	0
T6	478556	2996	0	0
T7	178311	178165	0	0
T15	301208	233491	0	0
T19	3638	3112	0	0
T20	12681	6868	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T188,T190
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	732120420	1907	0	0
DisabledNoTrigBkwd_A	732120420	186862	0	0
DisabledNoTrigFwd_A	732120420	386226816	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1907	0	0
T50	60974	0	0	0
T70	441518	0	0	0
T184	3158	844	0	0
T185	1418	0	0	0
T188	0	450	0	0
T190	0	613	0	0
T203	176249	0	0	0
T204	21122	0	0	0
T205	18049	0	0	0
T206	297162	0	0	0
T207	117088	0	0	0
T208	75342	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	186862	0	0
T5	319217	10	0	0
T6	478556	9	0	0
T7	178311	748	0	0
T8	386784	0	0	0
T15	301208	149	0	0
T16	0	1684	0	0
T17	0	569	0	0
T19	3638	0	0	0
T20	12681	3	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	20	0	0
T35	0	5176	0	0
T38	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	386226816	0	0
T1	9997	3269	0	0
T2	2843	2149	0	0
T3	7065	7008	0	0
T4	118601	118450	0	0
T5	319217	317161	0	0
T6	478556	477491	0	0
T7	178311	9741	0	0
T15	301208	272989	0	0
T19	3638	3126	0	0
T20	12681	7976	0	0