Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T2,T5,T19
1	1	0	Covered	T1,T4,T15
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T15,T23
1	0	Covered	T6,T17,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T17,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T15,T17,T25
1	1	Covered	T3,T15,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T2,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T6,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T5,T6,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T17,T26
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T17,T27
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T17,T28
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T17,T29,T30
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T4,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T4,T6
TimeoutSt->Phase0St	172	Covered	T3,T6,T15

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T17,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T17,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T17,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1270	0	0
CheckAccumTrig0_A	2147483647	2489	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1119	0	0
CheckEn_A	2147483647	1267022053	0	0
CheckPhase0_A	2147483647	2813	0	0
CheckPhase1_A	2147483647	2752	0	0
CheckPhase2_A	2147483647	2700	0	0
CheckPhase3_A	2147483647	2642	0	0
CheckTimeout0_A	2147483647	4287	0	0
CheckTimeoutSt1_A	2147483647	488532	0	0
CheckTimeoutSt2_A	2147483647	3923	0	0
CheckTimeoutStTrig_A	2147483647	229	0	0
ErrorStAllEscAsserted_A	2147483647	6541	0	0
ErrorStIsTerminal_A	2147483647	5461	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1270	0	0
T9	3471012	0	0	0
T12	167776	271	0	0
T13	0	157	0	0
T14	0	255	0	0
T17	934084	0	0	0
T18	98872	0	0	0
T31	0	299	0	0
T32	0	288	0	0
T33	30968	0	0	0
T34	41016	0	0	0
T35	1974172	0	0	0
T36	463552	0	0	0
T37	70744	0	0	0
T38	284636	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2489	0	0
T2	2843	1	0	0
T3	14130	1	0	0
T4	355803	9	0	0
T5	1276868	4	0	0
T6	1914224	3	0	0
T7	713244	2	0	0
T8	386784	1	0	0
T15	1204832	8	0	0
T16	0	6	0	0
T17	0	44	0	0
T19	14552	1	0	0
T20	50724	2	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	3	0	0
T33	0	1	0	0
T35	0	8	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	386784	0	0	0
T9	1735506	0	0	0
T10	883910	0	0	0
T15	301208	0	0	0
T17	467042	6	0	0
T18	49436	0	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T24	173931	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T33	15484	0	0	0
T34	20508	0	0	0
T35	987086	0	0	0
T36	231776	0	0	0
T37	35372	0	0	0
T38	213477	0	0	0
T39	2905	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1119	0	0
T3	7065	1	0	0
T4	237202	6	0	0
T5	638434	0	0	0
T6	957112	0	0	0
T7	534933	0	0	0
T8	773568	0	0	0
T12	41944	0	0	0
T15	1204832	2	0	0
T16	576718	3	0	0
T17	233521	30	0	0
T19	7276	0	0	0
T20	38043	1	0	0
T21	17384	0	0	0
T22	200416	0	0	0
T23	262899	2	0	0
T27	0	7	0	0
T29	0	9	0	0
T30	0	5	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	5810	0	0	0
T40	0	4	0	0
T41	0	7	0	0
T42	0	6	0	0
T45	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	70316	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1267022053	0	0
T1	39988	20697	0	0
T2	11372	8517	0	0
T3	28260	21617	0	0
T4	474404	131301	0	0
T5	1276868	38401	0	0
T6	1914224	11938	0	0
T7	713244	366501	0	0
T15	1204832	1192512	0	0
T19	14552	12352	0	0
T20	50724	29657	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2813	0	0
T2	2843	1	0	0
T3	14130	2	0	0
T4	355803	8	0	0
T5	1276868	4	0	0
T6	1914224	4	0	0
T7	713244	2	0	0
T8	386784	1	0	0
T15	1204832	11	0	0
T16	0	6	0	0
T17	0	51	0	0
T19	14552	1	0	0
T20	50724	2	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	4	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2752	0	0
T2	2843	1	0	0
T3	14130	2	0	0
T4	355803	6	0	0
T5	1276868	4	0	0
T6	1914224	4	0	0
T7	713244	2	0	0
T8	386784	1	0	0
T15	1204832	11	0	0
T16	0	6	0	0
T17	0	47	0	0
T19	14552	1	0	0
T20	50724	2	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	4	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2700	0	0
T2	2843	1	0	0
T3	14130	2	0	0
T4	355803	6	0	0
T5	1276868	4	0	0
T6	1914224	4	0	0
T7	713244	2	0	0
T8	386784	1	0	0
T15	1204832	10	0	0
T16	0	6	0	0
T17	0	44	0	0
T19	14552	1	0	0
T20	50724	2	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	4	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2642	0	0
T2	2843	1	0	0
T3	14130	2	0	0
T4	355803	6	0	0
T5	1276868	4	0	0
T6	1914224	4	0	0
T7	713244	2	0	0
T8	386784	1	0	0
T15	1204832	10	0	0
T16	0	6	0	0
T17	0	43	0	0
T19	14552	1	0	0
T20	50724	2	0	0
T21	17384	0	0	0
T22	150312	0	0	0
T23	175266	4	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4287	0	0
T1	29991	5	0	0
T2	8529	0	0	0
T3	28260	1	0	0
T4	474404	1	0	0
T5	1276868	0	0	0
T6	1914224	3	0	0
T7	713244	0	0	0
T15	1204832	15	0	0
T17	0	23	0	0
T19	14552	0	0	0
T20	50724	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	20	0	0
T29	0	6	0	0
T35	0	10	0	0
T36	0	14	0	0
T38	0	4	0	0
T41	0	6	0	0
T42	0	7	0	0
T43	0	1	0	0
T59	0	1	0	0
T61	0	26	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	488532	0	0
T1	29991	532	0	0
T2	8529	0	0	0
T3	28260	16	0	0
T4	474404	54	0	0
T5	1276868	0	0	0
T6	1914224	388	0	0
T7	713244	0	0	0
T15	1204832	2014	0	0
T17	0	759	0	0
T19	14552	0	0	0
T20	50724	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	360	0	0
T24	0	178	0	0
T27	0	1270	0	0
T29	0	418	0	0
T35	0	1603	0	0
T36	0	3524	0	0
T38	0	179	0	0
T41	0	225	0	0
T42	0	760	0	0
T43	0	181	0	0
T57	0	53	0	0
T59	0	472	0	0
T61	0	1696	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3923	0	0
T1	29991	5	0	0
T2	8529	0	0	0
T3	21195	0	0	0
T4	355803	1	0	0
T5	957651	0	0	0
T6	1435668	2	0	0
T7	534933	0	0	0
T8	386784	0	0	0
T12	41944	0	0	0
T15	1204832	12	0	0
T16	288359	0	0	0
T17	233521	15	0	0
T19	10914	0	0	0
T20	38043	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T24	0	1	0	0
T27	0	18	0	0
T29	0	181	0	0
T35	0	10	0	0
T36	0	13	0	0
T38	0	3	0	0
T39	2905	0	0	0
T41	0	4	0	0
T42	0	6	0	0
T43	0	1	0	0
T44	0	1	0	0
T57	0	1	0	0
T59	0	3	0	0
T61	35158	26	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	229	0	0
T3	7065	1	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T8	773568	0	0	0
T11	876020	0	0	0
T12	83888	0	0	0
T15	903624	3	0	0
T16	576718	0	0	0
T17	467042	2	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	13038	0	0	0
T22	150312	0	0	0
T23	175266	1	0	0
T27	469601	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T39	5810	0	0	0
T41	0	1	0	0
T48	0	3	0	0
T49	0	2	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	70316	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	4	0	0
T71	20338	0	0	0
T72	189782	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6541	0	0
T9	3471012	0	0	0
T12	167776	1488	0	0
T13	0	680	0	0
T14	0	1485	0	0
T17	934084	0	0	0
T18	98872	0	0	0
T31	0	1509	0	0
T32	0	1379	0	0
T33	30968	0	0	0
T34	41016	0	0	0
T35	1974172	0	0	0
T36	463552	0	0	0
T37	70744	0	0	0
T38	284636	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5461	0	0
T9	3471012	0	0	0
T12	167776	1248	0	0
T13	0	560	0	0
T14	0	1245	0	0
T17	934084	0	0	0
T18	98872	0	0	0
T31	0	1269	0	0
T32	0	1139	0	0
T33	30968	0	0	0
T34	41016	0	0	0
T35	1974172	0	0	0
T36	463552	0	0	0
T37	70744	0	0	0
T38	284636	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	39988	39612	0	0
T2	11372	11124	0	0
T3	28260	28032	0	0
T4	474404	474372	0	0
T5	1276868	1276832	0	0
T6	1914224	1914196	0	0
T7	713244	713216	0	0
T15	1204832	1204796	0	0
T19	14552	14252	0	0
T20	50724	50464	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	39988	39612	0	0
T2	11372	11124	0	0
T3	28260	28032	0	0
T4	474404	474372	0	0
T5	1276868	1276832	0	0
T6	1914224	1914196	0	0
T7	713244	713216	0	0
T15	1204832	1204796	0	0
T19	14552	14252	0	0
T20	50724	50464	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T6
1	0	1	Covered	T2,T7,T23
1	1	0	Covered	T1,T15,T23
1	1	1	Covered	T1,T4,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T15,T29,T60
1	0	Covered	T17,T41,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T41,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Not Covered
1	1	Covered	T15,T29,T60

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T39

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T5,T17,T35

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T4,T6,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T23,T16,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T5
Phase1St	198	Covered	T2,T4,T5
Phase2St	215	Covered	T2,T4,T5
Phase3St	233	Covered	T2,T4,T5
TerminalSt	249	Covered	T2,T4,T5
TimeoutSt	159	Covered	T1,T4,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T4,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T73,T74,T75
Phase0St->Phase1St	198	Covered	T2,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T41,T76
Phase1St->Phase2St	215	Covered	T2,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T17,T28
Phase2St->Phase3St	233	Covered	T2,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T52,T77,T78
Phase3St->TerminalSt	249	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T23,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T6
TimeoutSt->Phase0St	172	Covered	T15,T17,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T17,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T73,T74,T75
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T41,T76
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T17,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T52,T77,T78
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T16,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	732120420	333	0	0
CheckAccumTrig0_A	732120420	556	0	0
CheckAccumTrig1_A	732120420	23	0	0
CheckClr_A	732120420	240	0	0
CheckEn_A	731923544	307173599	0	0
CheckPhase0_A	732120420	632	0	0
CheckPhase1_A	732120420	617	0	0
CheckPhase2_A	732120420	598	0	0
CheckPhase3_A	732120420	589	0	0
CheckTimeout0_A	732120420	949	0	0
CheckTimeoutSt1_A	732120420	114452	0	0
CheckTimeoutSt2_A	732120420	865	0	0
CheckTimeoutStTrig_A	732120420	59	0	0
ErrorStAllEscAsserted_A	732120420	1709	0	0
ErrorStIsTerminal_A	732120420	1439	0	0
EscStateOut_A	731921433	731848399	0	0
u_state_regs_A	732120420	731932530	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	333	0	0
T9	867753	0	0	0
T12	41944	62	0	0
T13	0	49	0	0
T14	0	75	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	72	0	0
T32	0	75	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	556	0	0
T2	2843	1	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T15	301208	1	0	0
T16	0	2	0	0
T17	0	14	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	23	0	0
T9	867753	0	0	0
T17	233521	1	0	0
T18	24718	0	0	0
T24	57977	0	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	240	0	0
T8	386784	0	0	0
T12	41944	0	0	0
T15	301208	1	0	0
T16	288359	1	0	0
T17	233521	10	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T27	0	2	0	0
T29	0	2	0	0
T37	0	1	0	0
T39	2905	0	0	0
T41	0	3	0	0
T42	0	3	0	0
T59	0	1	0	0
T61	35158	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731923544	307173599	0	0
T1	9997	2083	0	0
T2	2843	2118	0	0
T3	7065	7007	0	0
T4	118601	3197	0	0
T5	319217	2065	0	0
T6	478556	2972	0	0
T7	178311	597	0	0
T15	301208	194009	0	0
T19	3638	3070	0	0
T20	12681	12615	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	632	0	0
T2	2843	1	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	15	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	1	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	617	0	0
T2	2843	1	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	13	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	1	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	598	0	0
T2	2843	1	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T15	301208	2	0	0
T16	0	2	0	0
T17	0	10	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	1	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	589	0	0
T2	2843	1	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T15	301208	2	0	0
T16	0	2	0	0
T17	0	10	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T23	0	1	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	949	0	0
T1	9997	2	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	0	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	9	0	0
T17	0	5	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T29	0	2	0	0
T35	0	4	0	0
T41	0	1	0	0
T42	0	1	0	0
T61	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	114452	0	0
T1	9997	189	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	54	0	0
T5	319217	0	0	0
T6	478556	194	0	0
T7	178311	0	0	0
T15	301208	923	0	0
T17	0	191	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T29	0	99	0	0
T35	0	705	0	0
T42	0	4	0	0
T59	0	345	0	0
T61	0	449	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	865	0	0
T1	9997	2	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	1	0	0
T5	319217	0	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	7	0	0
T17	0	4	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T44	0	1	0	0
T59	0	2	0	0
T61	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	59	0	0
T8	386784	0	0	0
T12	41944	0	0	0
T15	301208	2	0	0
T16	288359	0	0	0
T17	233521	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T39	2905	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T60	0	1	0	0
T61	35158	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1709	0	0
T9	867753	0	0	0
T12	41944	382	0	0
T13	0	176	0	0
T14	0	386	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	389	0	0
T32	0	376	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1439	0	0
T9	867753	0	0	0
T12	41944	322	0	0
T13	0	146	0	0
T14	0	326	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	329	0	0
T32	0	316	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731921433	731848399	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	731932530	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T15
1	0	1	Covered	T20,T7,T16
1	1	0	Covered	T1,T4,T15
1	1	1	Covered	T1,T61,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T61,T17
0	1	Covered	T27,T60,T30
1	0	Covered	T38,T49,T79

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T61,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T38,T49,T79

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T61,T17
1	0	Not Covered
1	1	Covered	T27,T60,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T20
1	Covered	T23,T17,T38

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T20,T35,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T20,T23
1	Covered	T6,T7,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T20,T7
1	Covered	T5,T16,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T20,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T20,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T6,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T6,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T5,T6,T20
Phase1St	198	Covered	T5,T6,T20
Phase2St	215	Covered	T5,T6,T20
Phase3St	233	Covered	T5,T6,T20
TerminalSt	249	Covered	T5,T6,T20
TimeoutSt	159	Covered	T1,T61,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T5,T6,T20
IdleSt->TimeoutSt	159	Covered	T1,T61,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T52,T80,T55
Phase0St->Phase1St	198	Covered	T5,T6,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T81,T82,T83
Phase1St->Phase2St	215	Covered	T5,T6,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T41,T51,T84
Phase2St->Phase3St	233	Covered	T5,T6,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T77,T85,T86
Phase3St->TerminalSt	249	Covered	T5,T6,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T15,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T61,T17
TimeoutSt->Phase0St	172	Covered	T38,T27,T60

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T61,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T38,T27,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T61,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T61,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T80,T55,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T5,T6,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T5,T6,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T81,T82,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T5,T6,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T5,T6,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T51,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T5,T6,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T5,T6,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T77,T85,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T5,T6,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T5,T6,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T17,T35
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T6,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	732120420	306	0	0
CheckAccumTrig0_A	732120420	519	0	0
CheckAccumTrig1_A	732120420	25	0	0
CheckClr_A	732120420	210	0	0
CheckEn_A	731923544	318105819	0	0
CheckPhase0_A	732120420	589	0	0
CheckPhase1_A	732120420	579	0	0
CheckPhase2_A	732120420	572	0	0
CheckPhase3_A	732120420	564	0	0
CheckTimeout0_A	732120420	1585	0	0
CheckTimeoutSt1_A	732120420	178352	0	0
CheckTimeoutSt2_A	732120420	1501	0	0
CheckTimeoutStTrig_A	732120420	53	0	0
ErrorStAllEscAsserted_A	732120420	1607	0	0
ErrorStIsTerminal_A	732120420	1337	0	0
EscStateOut_A	731921433	731848399	0	0
u_state_regs_A	732120420	731932530	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	306	0	0
T9	867753	0	0	0
T12	41944	66	0	0
T13	0	39	0	0
T14	0	49	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	93	0	0
T32	0	59	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	519	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T8	386784	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T35	0	3	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	25	0	0
T10	883910	0	0	0
T11	876020	0	0	0
T24	57977	0	0	0
T27	469601	0	0	0
T38	71159	1	0	0
T40	864680	0	0	0
T49	0	2	0	0
T57	8246	0	0	0
T71	20338	0	0	0
T72	189782	0	0	0
T79	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	150232	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	210	0	0
T7	178311	0	0	0
T8	386784	0	0	0
T15	301208	0	0	0
T16	288359	0	0	0
T17	0	2	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T30	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	2905	0	0	0
T40	0	4	0	0
T41	0	2	0	0
T46	0	1	0	0
T60	0	1	0	0
T61	35158	0	0	0
T96	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731923544	318105819	0	0
T1	9997	3268	0	0
T2	2843	2149	0	0
T3	7065	7007	0	0
T4	118601	118450	0	0
T5	319217	2092	0	0
T6	478556	3023	0	0
T7	178311	9741	0	0
T15	301208	272989	0	0
T19	3638	3126	0	0
T20	12681	7975	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	589	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T8	386784	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T35	0	3	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	579	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T8	386784	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T35	0	3	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	572	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T8	386784	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T35	0	3	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	564	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	1	0	0
T8	386784	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	1	0	0
T35	0	3	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1585	0	0
T1	9997	1	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T17	0	1	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	17	0	0
T29	0	2	0	0
T36	0	10	0	0
T38	0	4	0	0
T42	0	5	0	0
T43	0	1	0	0
T59	0	1	0	0
T61	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	178352	0	0
T1	9997	100	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T17	0	81	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	1114	0	0
T29	0	227	0	0
T36	0	2551	0	0
T38	0	179	0	0
T42	0	530	0	0
T43	0	181	0	0
T59	0	127	0	0
T61	0	489	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1501	0	0
T1	9997	1	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T17	0	1	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	15	0	0
T29	0	2	0	0
T36	0	10	0	0
T38	0	3	0	0
T42	0	5	0	0
T43	0	1	0	0
T59	0	1	0	0
T61	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	53	0	0
T11	876020	0	0	0
T13	21492	0	0	0
T27	469601	2	0	0
T29	172392	0	0	0
T30	0	2	0	0
T41	121439	0	0	0
T42	378078	0	0	0
T48	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T57	8246	0	0	0
T60	0	1	0	0
T66	0	4	0	0
T68	0	2	0	0
T70	0	1	0	0
T71	20338	0	0	0
T72	189782	0	0	0
T95	150232	0	0	0
T97	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1607	0	0
T9	867753	0	0	0
T12	41944	367	0	0
T13	0	192	0	0
T14	0	356	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	369	0	0
T32	0	323	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1337	0	0
T9	867753	0	0	0
T12	41944	307	0	0
T13	0	162	0	0
T14	0	296	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	309	0	0
T32	0	263	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731921433	731848399	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	731932530	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T7,T23
1	1	0	Covered	T1,T15,T61
1	1	1	Covered	T3,T6,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T15
0	1	Covered	T3,T23,T17
1	0	Covered	T6,T17,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T17,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T15
1	0	Covered	T17
1	1	Covered	T3,T23,T17

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T15
1	Covered	T3,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T8,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T15,T23,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T6,T15,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T5
Phase1St	198	Covered	T3,T4,T5
Phase2St	215	Covered	T3,T4,T5
Phase3St	233	Covered	T3,T4,T5
TerminalSt	249	Covered	T3,T4,T5
TimeoutSt	159	Covered	T3,T6,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T3,T6,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T26,T52
Phase0St->Phase1St	198	Covered	T3,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T17,T27
Phase1St->Phase2St	215	Covered	T3,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T98,T97,T49
Phase2St->Phase3St	233	Covered	T3,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T17,T29,T30
Phase3St->TerminalSt	249	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T61,T17
TimeoutSt->Phase0St	172	Covered	T3,T6,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T61,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T26,T54
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T17,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T98,T97,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	732120420	338	0	0
CheckAccumTrig0_A	732120420	909	0	0
CheckAccumTrig1_A	732120420	55	0	0
CheckClr_A	732120420	464	0	0
CheckEn_A	731923544	331570281	0	0
CheckPhase0_A	732120420	1015	0	0
CheckPhase1_A	732120420	987	0	0
CheckPhase2_A	732120420	970	0	0
CheckPhase3_A	732120420	944	0	0
CheckTimeout0_A	732120420	1191	0	0
CheckTimeoutSt1_A	732120420	125834	0	0
CheckTimeoutSt2_A	732120420	1074	0	0
CheckTimeoutStTrig_A	732120420	61	0	0
ErrorStAllEscAsserted_A	732120420	1637	0	0
ErrorStIsTerminal_A	732120420	1367	0	0
EscStateOut_A	731921433	731848399	0	0
u_state_regs_A	732120420	731932530	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	338	0	0
T9	867753	0	0	0
T12	41944	85	0	0
T13	0	36	0	0
T14	0	72	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	70	0	0
T32	0	75	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	909	0	0
T3	7065	1	0	0
T4	118601	4	0	0
T5	319217	1	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T8	0	1	0	0
T15	301208	4	0	0
T16	0	1	0	0
T17	0	15	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	55	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	386784	0	0	0
T15	301208	0	0	0
T17	0	1	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T39	2905	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	464	0	0
T3	7065	1	0	0
T4	118601	3	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T16	0	1	0	0
T17	0	11	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	1	0	0
T27	0	4	0	0
T29	0	6	0	0
T42	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731923544	331570281	0	0
T1	9997	7673	0	0
T2	2843	2111	0	0
T3	7065	596	0	0
T4	118601	3193	0	0
T5	319217	16277	0	0
T6	478556	2947	0	0
T7	178311	177998	0	0
T15	301208	492024	0	0
T19	3638	3044	0	0
T20	12681	2199	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1015	0	0
T3	7065	2	0	0
T4	118601	4	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	0	1	0	0
T15	301208	4	0	0
T16	0	1	0	0
T17	0	17	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	2	0	0
T33	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	987	0	0
T3	7065	2	0	0
T4	118601	3	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	0	1	0	0
T15	301208	4	0	0
T16	0	1	0	0
T17	0	15	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	2	0	0
T33	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	970	0	0
T3	7065	2	0	0
T4	118601	3	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	0	1	0	0
T15	301208	4	0	0
T16	0	1	0	0
T17	0	15	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	2	0	0
T33	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	944	0	0
T3	7065	2	0	0
T4	118601	3	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T8	0	1	0	0
T15	301208	4	0	0
T16	0	1	0	0
T17	0	14	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	2	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1191	0	0
T3	7065	1	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	4	0	0
T17	0	11	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T61	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	125834	0	0
T3	7065	16	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	763	0	0
T17	0	446	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	360	0	0
T24	0	178	0	0
T27	0	139	0	0
T35	0	175	0	0
T36	0	973	0	0
T57	0	53	0	0
T61	0	441	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1074	0	0
T8	386784	0	0	0
T12	41944	0	0	0
T15	301208	4	0	0
T16	288359	0	0	0
T17	233521	8	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T24	0	1	0	0
T27	0	2	0	0
T29	0	176	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	2905	0	0	0
T41	0	1	0	0
T57	0	1	0	0
T61	35158	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	61	0	0
T3	7065	1	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	0	0	0
T17	0	2	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	0	1	0	0
T30	0	1	0	0
T36	0	1	0	0
T48	0	2	0	0
T59	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1637	0	0
T9	867753	0	0	0
T12	41944	384	0	0
T13	0	168	0	0
T14	0	337	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	403	0	0
T32	0	345	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1367	0	0
T9	867753	0	0	0
T12	41944	324	0	0
T13	0	138	0	0
T14	0	277	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	343	0	0
T32	0	285	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731921433	731848399	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	731932530	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T6
1	0	1	Covered	T19,T15,T8
1	1	0	Covered	T1,T4,T15
1	1	1	Covered	T1,T6,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T15
0	1	Covered	T15,T41,T59
1	0	Covered	T17,T41,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T6,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T41,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T15
1	0	Covered	T15,T25
1	1	Covered	T15,T41,T59

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T16,T40

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T4,T6,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T20,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T5,T35,T41

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T5,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T1,T6,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T6,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T55,T99
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T100,T101
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T97,T102,T54
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T68,T77
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T15,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T6,T15
TimeoutSt->Phase0St	172	Covered	T15,T17,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T17,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T55,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T100,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T97,T102,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T103,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	732120420	293	0	0
CheckAccumTrig0_A	732120420	505	0	0
CheckAccumTrig1_A	732120420	22	0	0
CheckClr_A	732120420	205	0	0
CheckEn_A	731923544	310172354	0	0
CheckPhase0_A	732120420	577	0	0
CheckPhase1_A	732120420	569	0	0
CheckPhase2_A	732120420	560	0	0
CheckPhase3_A	732120420	545	0	0
CheckTimeout0_A	732120420	562	0	0
CheckTimeoutSt1_A	732120420	69894	0	0
CheckTimeoutSt2_A	732120420	483	0	0
CheckTimeoutStTrig_A	732120420	56	0	0
ErrorStAllEscAsserted_A	732120420	1588	0	0
ErrorStIsTerminal_A	732120420	1318	0	0
EscStateOut_A	731921433	731848399	0	0
u_state_regs_A	732120420	731932530	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	293	0	0
T9	867753	0	0	0
T12	41944	58	0	0
T13	0	33	0	0
T14	0	59	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	64	0	0
T32	0	79	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	505	0	0
T4	118601	4	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	2	0	0
T16	0	2	0	0
T17	0	9	0	0
T19	3638	1	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	3	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	22	0	0
T9	867753	0	0	0
T17	233521	4	0	0
T18	24718	0	0	0
T24	57977	0	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T83	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	205	0	0
T4	118601	3	0	0
T5	319217	0	0	0
T6	478556	0	0	0
T7	178311	0	0	0
T15	301208	1	0	0
T16	0	1	0	0
T17	0	7	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731923544	310172354	0	0
T1	9997	7673	0	0
T2	2843	2139	0	0
T3	7065	7007	0	0
T4	118601	6461	0	0
T5	319217	17967	0	0
T6	478556	2996	0	0
T7	178311	178165	0	0
T15	301208	233490	0	0
T19	3638	3112	0	0
T20	12681	6868	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	577	0	0
T4	118601	3	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	13	0	0
T19	3638	1	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	3	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	569	0	0
T4	118601	2	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	13	0	0
T19	3638	1	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	3	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	560	0	0
T4	118601	2	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	13	0	0
T19	3638	1	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	3	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	545	0	0
T4	118601	2	0	0
T5	319217	1	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	3	0	0
T16	0	2	0	0
T17	0	13	0	0
T19	3638	1	0	0
T20	12681	1	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T35	0	3	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	562	0	0
T1	9997	2	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	2	0	0
T17	0	6	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T35	0	5	0	0
T41	0	5	0	0
T42	0	1	0	0
T61	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	69894	0	0
T1	9997	243	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	194	0	0
T7	178311	0	0	0
T15	301208	328	0	0
T17	0	41	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	17	0	0
T29	0	92	0	0
T35	0	723	0	0
T41	0	225	0	0
T42	0	226	0	0
T61	0	317	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	483	0	0
T1	9997	2	0	0
T2	2843	0	0	0
T3	7065	0	0	0
T4	118601	0	0	0
T5	319217	0	0	0
T6	478556	1	0	0
T7	178311	0	0	0
T15	301208	1	0	0
T17	0	2	0	0
T19	3638	0	0	0
T20	12681	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T35	0	5	0	0
T41	0	3	0	0
T42	0	1	0	0
T61	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	56	0	0
T8	386784	0	0	0
T12	41944	0	0	0
T15	301208	1	0	0
T16	288359	0	0	0
T17	233521	0	0	0
T21	4346	0	0	0
T22	50104	0	0	0
T23	87633	0	0	0
T39	2905	0	0	0
T41	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T59	0	1	0	0
T61	35158	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T70	0	2	0	0
T97	0	1	0	0
T102	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1588	0	0
T9	867753	0	0	0
T12	41944	355	0	0
T13	0	144	0	0
T14	0	406	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	348	0	0
T32	0	335	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	1318	0	0
T9	867753	0	0	0
T12	41944	295	0	0
T13	0	114	0	0
T14	0	346	0	0
T17	233521	0	0	0
T18	24718	0	0	0
T31	0	288	0	0
T32	0	275	0	0
T33	7742	0	0	0
T34	10254	0	0	0
T35	493543	0	0	0
T36	115888	0	0	0
T37	17686	0	0	0
T38	71159	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731921433	731848399	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732120420	731932530	0	0
T1	9997	9903	0	0
T2	2843	2781	0	0
T3	7065	7008	0	0
T4	118601	118593	0	0
T5	319217	319208	0	0
T6	478556	478549	0	0
T7	178311	178304	0	0
T15	301208	301199	0	0
T19	3638	3563	0	0
T20	12681	12616	0	0