Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T217,T72
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13928	0	0
DisabledNoTrigBkwd_A	2147483647	757705	0	0
DisabledNoTrigFwd_A	2147483647	1551460694	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13928	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	306027	0	0	0
T16	19802	0	0	0
T21	49673	0	0	0
T26	3232	423	0	0
T30	6241	0	0	0
T46	21075	0	0	0
T54	331743	0	0	0
T72	2751	357	0	0
T77	100272	0	0	0
T78	10663	0	0	0
T86	79084	0	0	0
T87	71576	0	0	0
T123	116683	0	0	0
T217	0	646	0	0
T218	3763	392	0	0
T219	0	992	0	0
T220	0	684	0	0
T221	0	592	0	0
T222	0	812	0	0
T223	0	737	0	0
T224	0	716	0	0
T225	0	938	0	0
T226	0	441	0	0
T227	0	478	0	0
T228	0	545	0	0
T229	0	682	0	0
T230	0	1166	0	0
T231	0	964	0	0
T232	0	1158	0	0
T233	0	347	0	0
T234	0	858	0	0
T235	116026	0	0	0
T236	350801	0	0	0
T237	41237	0	0	0
T238	47541	0	0	0
T239	57600	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	757705	0	0
T2	69852	43	0	0
T3	1213580	6781	0	0
T4	473860	0	0	0
T5	436748	304	0	0
T6	993364	966	0	0
T7	98148	0	0	0
T8	2114664	1	0	0
T9	0	934	0	0
T14	0	1098	0	0
T15	0	374	0	0
T17	234628	48	0	0
T18	15936	3	0	0
T19	854296	540	0	0
T20	0	60	0	0
T22	0	45	0	0
T26	0	4	0	0
T31	0	1203	0	0
T45	0	80	0	0
T46	0	9	0	0
T47	0	1055	0	0
T48	0	628	0	0
T49	0	3	0	0
T50	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1551460694	0	0
T1	141468	44372	0	0
T2	69852	25871	0	0
T3	1213580	15380	0	0
T4	473860	515753	0	0
T5	436748	229163	0	0
T6	993364	748090	0	0
T7	98148	10088	0	0
T17	234628	112095	0	0
T18	15936	7040	0	0
T19	854296	1857720	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T220,T221
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682088530	5882	0	0
DisabledNoTrigBkwd_A	682088530	217853	0	0
DisabledNoTrigFwd_A	682088530	329831670	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	5882	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	306027	0	0	0
T16	19802	0	0	0
T21	49673	0	0	0
T26	3232	423	0	0
T30	6241	0	0	0
T46	21075	0	0	0
T77	100272	0	0	0
T78	10663	0	0	0
T220	0	684	0	0
T221	0	592	0	0
T225	0	938	0	0
T226	0	441	0	0
T229	0	682	0	0
T231	0	964	0	0
T232	0	1158	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	217853	0	0
T2	17463	21	0	0
T3	303395	2100	0	0
T4	118465	0	0	0
T5	109187	39	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T14	0	1098	0	0
T17	58657	30	0	0
T18	3984	0	0	0
T19	213574	404	0	0
T20	0	60	0	0
T26	0	4	0	0
T45	0	80	0	0
T46	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	329831670	0	0
T1	35367	3013	0	0
T2	17463	6778	0	0
T3	303395	2030	0	0
T4	118465	210962	0	0
T5	109187	8138	0	0
T6	248341	248334	0	0
T7	24537	2501	0	0
T17	58657	7505	0	0
T18	3984	2524	0	0
T19	213574	981642	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682088530	392	0	0
DisabledNoTrigBkwd_A	682088530	157428	0	0
DisabledNoTrigFwd_A	682088530	413085594	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	392	0	0
T54	331743	0	0	0
T86	79084	0	0	0
T87	71576	0	0	0
T123	116683	0	0	0
T218	3763	392	0	0
T235	116026	0	0	0
T236	350801	0	0	0
T237	41237	0	0	0
T238	47541	0	0	0
T239	57600	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	157428	0	0
T2	17463	15	0	0
T3	303395	2938	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	374	0	0
T17	58657	3	0	0
T18	3984	0	0	0
T19	213574	0	0	0
T22	0	45	0	0
T31	0	1203	0	0
T47	0	1055	0	0
T48	0	628	0	0
T49	0	3	0	0
T50	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	413085594	0	0
T1	35367	3026	0	0
T2	17463	3599	0	0
T3	303395	9222	0	0
T4	118465	111771	0	0
T5	109187	103701	0	0
T6	248341	248334	0	0
T7	24537	2511	0	0
T17	58657	46447	0	0
T18	3984	586	0	0
T19	213574	158328	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T17
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T72,T227,T228
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682088530	3751	0	0
DisabledNoTrigBkwd_A	682088530	179134	0	0
DisabledNoTrigFwd_A	682088530	385576159	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	3751	0	0
T27	77014	0	0	0
T51	181243	0	0	0
T52	471212	0	0	0
T72	2751	357	0	0
T73	122177	0	0	0
T74	327195	0	0	0
T75	23155	0	0	0
T227	0	478	0	0
T228	0	545	0	0
T230	0	1166	0	0
T233	0	347	0	0
T234	0	858	0	0
T240	360535	0	0	0
T241	10874	0	0	0
T242	50493	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	179134	0	0
T2	17463	7	0	0
T3	303395	1743	0	0
T4	118465	0	0	0
T5	109187	265	0	0
T6	248341	966	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	934	0	0
T17	58657	15	0	0
T18	3984	3	0	0
T19	213574	136	0	0
T21	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	385576159	0	0
T1	35367	3052	0	0
T2	17463	5691	0	0
T3	303395	2057	0	0
T4	118465	84032	0	0
T5	109187	8196	0	0
T6	248341	3088	0	0
T7	24537	2531	0	0
T17	58657	9387	0	0
T18	3984	1965	0	0
T19	213574	567543	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T217,T219,T222
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682088530	3903	0	0
DisabledNoTrigBkwd_A	682088530	203290	0	0
DisabledNoTrigFwd_A	682088530	422967271	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	3903	0	0
T49	413684	0	0	0
T50	597592	0	0	0
T79	27551	0	0	0
T80	19958	0	0	0
T81	514969	0	0	0
T217	3600	646	0	0
T219	0	992	0	0
T222	0	812	0	0
T223	0	737	0	0
T224	0	716	0	0
T243	384479	0	0	0
T244	47399	0	0	0
T245	44258	0	0	0
T246	371687	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	203290	0	0
T2	17463	10	0	0
T3	303395	2067	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	472	0	0
T10	0	1	0	0
T15	0	1784	0	0
T17	58657	2	0	0
T18	3984	1	0	0
T19	213574	192	0	0
T65	0	1425	0	0
T67	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	422967271	0	0
T1	35367	35281	0	0
T2	17463	9803	0	0
T3	303395	2071	0	0
T4	118465	108988	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	2545	0	0
T17	58657	48756	0	0
T18	3984	1965	0	0
T19	213574	150207	0	0