Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T5,T19
1	0	Covered	T21,T15,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T21,T15,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T23,T24,T25
1	1	Covered	T1,T5,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T20,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T27,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T30,T31,T22
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T32,T33
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T18,T32,T34
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T5,T17
TimeoutSt->Phase0St	172	Covered	T1,T5,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T31,T22
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T32,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T32,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1235	0	0
CheckAccumTrig0_A	2147483647	2247	0	0
CheckAccumTrig1_A	2147483647	95	0	0
CheckClr_A	2147483647	1024	0	0
CheckEn_A	2147483647	1237084650	0	0
CheckPhase0_A	2147483647	2544	0	0
CheckPhase1_A	2147483647	2508	0	0
CheckPhase2_A	2147483647	2460	0	0
CheckPhase3_A	2147483647	2424	0	0
CheckTimeout0_A	2147483647	3692	0	0
CheckTimeoutSt1_A	2147483647	418355	0	0
CheckTimeoutSt2_A	2147483647	3334	0	0
CheckTimeoutStTrig_A	2147483647	255	0	0
ErrorStAllEscAsserted_A	2147483647	6360	0	0
ErrorStIsTerminal_A	2147483647	5280	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1235	0	0
T11	124208	315	0	0
T12	0	146	0	0
T13	0	244	0	0
T24	140580	0	0	0
T35	0	254	0	0
T36	0	276	0	0
T37	591196	0	0	0
T38	561904	0	0	0
T39	1647608	0	0	0
T40	1135296	0	0	0
T41	240880	0	0	0
T42	354576	0	0	0
T43	487948	0	0	0
T44	3228984	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2247	0	0
T2	69852	4	0	0
T3	1213580	6	0	0
T4	473860	0	0	0
T5	436748	3	0	0
T6	993364	1	0	0
T7	98148	0	0	0
T8	2114664	1	0	0
T9	0	2	0	0
T14	0	1	0	0
T15	0	12	0	0
T17	234628	3	0	0
T18	15936	1	0	0
T19	854296	2	0	0
T20	0	6	0	0
T22	0	2	0	0
T26	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95	0	0
T10	1892314	0	0	0
T15	612054	1	0	0
T16	39604	0	0	0
T21	49673	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T27	77014	3	0	0
T30	12482	0	0	0
T31	405328	0	0	0
T32	296356	1	0	0
T33	381180	0	0	0
T40	0	1	0	0
T47	1474268	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	654558	0	0	0
T66	15954	0	0	0
T67	819326	0	0	0
T68	186474	0	0	0
T69	359096	0	0	0
T70	101871	0	0	0
T71	688701	0	0	0
T72	2751	0	0	0
T73	122177	0	0	0
T74	327195	0	0	0
T75	23155	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1024	0	0
T1	35367	1	0	0
T2	34926	1	0	0
T3	910185	3	0	0
T4	355395	0	0	0
T5	327561	2	0	0
T6	745023	0	0	0
T7	98148	0	0	0
T8	1585998	1	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	0	13	0	0
T17	234628	1	0	0
T18	15936	1	0	0
T19	854296	3	0	0
T20	126098	5	0	0
T21	0	4	0	0
T22	0	2	0	0
T26	3232	0	0	0
T27	0	5	0	0
T30	0	1	0	0
T34	0	1	0	0
T45	85445	0	0	0
T46	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1237084650	0	0
T1	141468	44371	0	0
T2	69852	19243	0	0
T3	1213580	15380	0	0
T4	473860	515753	0	0
T5	436748	229161	0	0
T6	993364	748090	0	0
T7	98148	10084	0	0
T17	234628	104814	0	0
T18	15936	7038	0	0
T19	854296	2456993	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2544	0	0
T1	70734	3	0	0
T2	69852	5	0	0
T3	1213580	7	0	0
T4	473860	0	0	0
T5	436748	4	0	0
T6	993364	1	0	0
T7	98148	0	0	0
T8	1057332	1	0	0
T9	0	3	0	0
T14	0	1	0	0
T15	0	22	0	0
T17	234628	4	0	0
T18	15936	2	0	0
T19	854296	9	0	0
T20	0	6	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T65	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2508	0	0
T1	70734	3	0	0
T2	69852	5	0	0
T3	1213580	7	0	0
T4	473860	0	0	0
T5	436748	4	0	0
T6	993364	1	0	0
T7	98148	0	0	0
T8	1057332	1	0	0
T9	0	3	0	0
T14	0	1	0	0
T15	0	22	0	0
T17	234628	4	0	0
T18	15936	2	0	0
T19	854296	9	0	0
T20	0	6	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T65	0	7	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2460	0	0
T1	70734	3	0	0
T2	69852	5	0	0
T3	1213580	7	0	0
T4	473860	0	0	0
T5	436748	4	0	0
T6	993364	1	0	0
T7	98148	0	0	0
T8	1057332	1	0	0
T9	0	3	0	0
T14	0	1	0	0
T15	0	21	0	0
T17	234628	3	0	0
T18	15936	2	0	0
T19	854296	9	0	0
T20	0	6	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T65	0	7	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T1	70734	3	0	0
T2	69852	5	0	0
T3	1213580	7	0	0
T4	473860	0	0	0
T5	436748	4	0	0
T6	993364	1	0	0
T7	98148	0	0	0
T8	1057332	1	0	0
T9	0	3	0	0
T14	0	1	0	0
T15	0	21	0	0
T17	234628	3	0	0
T18	15936	1	0	0
T19	854296	9	0	0
T20	0	6	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3692	0	0
T1	106101	5	0	0
T2	69852	1	0	0
T3	1213580	0	0	0
T4	473860	0	0	0
T5	436748	2	0	0
T6	993364	0	0	0
T7	98148	0	0	0
T8	528666	0	0	0
T15	0	19	0	0
T17	234628	2	0	0
T18	15936	0	0	0
T19	854296	112	0	0
T21	0	3	0	0
T22	0	4	0	0
T27	0	2	0	0
T30	0	2	0	0
T32	0	18	0	0
T34	0	4	0	0
T66	0	1	0	0
T68	0	456	0	0
T78	0	7	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	418355	0	0
T1	106101	622	0	0
T2	69852	57	0	0
T3	1213580	0	0	0
T4	473860	0	0	0
T5	436748	56	0	0
T6	993364	0	0	0
T7	98148	0	0	0
T8	528666	0	0	0
T15	0	2902	0	0
T17	234628	195	0	0
T18	15936	0	0	0
T19	854296	15955	0	0
T21	0	131	0	0
T22	0	1137	0	0
T27	0	2	0	0
T30	0	845	0	0
T32	0	2296	0	0
T34	0	656	0	0
T66	0	61	0	0
T68	0	45638	0	0
T78	0	544	0	0
T79	0	1624	0	0
T80	0	853	0	0
T81	0	159	0	0
T82	0	85	0	0
T83	0	926	0	0
T84	0	31	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3334	0	0
T1	35367	2	0	0
T2	34926	0	0	0
T3	606790	0	0	0
T4	236930	0	0	0
T5	218374	1	0	0
T6	496682	0	0	0
T7	73611	0	0	0
T8	1585998	0	0	0
T9	333658	0	0	0
T14	1798908	0	0	0
T15	0	17	0	0
T17	175971	2	0	0
T18	11952	0	0	0
T19	854296	101	0	0
T20	126098	0	0	0
T21	49673	2	0	0
T22	0	1	0	0
T26	6464	0	0	0
T27	0	5	0	0
T30	0	1	0	0
T32	0	28	0	0
T34	0	7	0	0
T45	170890	0	0	0
T46	21075	0	0	0
T53	0	3	0	0
T66	0	1	0	0
T68	0	455	0	0
T74	0	2	0	0
T78	10663	2	0	0
T79	0	6	0	0
T80	0	8	0	0
T81	0	4	0	0
T84	0	1	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255	0	0
T1	70734	3	0	0
T2	34926	0	0	0
T3	606790	0	0	0
T4	236930	0	0	0
T5	218374	1	0	0
T6	496682	0	0	0
T7	49074	0	0	0
T8	528666	0	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T17	117314	0	0	0
T18	7968	0	0	0
T19	640722	6	0	0
T20	63049	0	0	0
T21	49673	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T26	3232	0	0	0
T30	0	1	0	0
T32	296356	1	0	0
T45	85445	0	0	0
T46	21075	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	3	0	0
T55	0	4	0	0
T69	359096	0	0	0
T78	10663	0	0	0
T81	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6360	0	0
T11	124208	1448	0	0
T12	0	705	0	0
T13	0	1424	0	0
T24	140580	0	0	0
T35	0	1359	0	0
T36	0	1424	0	0
T37	591196	0	0	0
T38	561904	0	0	0
T39	1647608	0	0	0
T40	1135296	0	0	0
T41	240880	0	0	0
T42	354576	0	0	0
T43	487948	0	0	0
T44	3228984	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5280	0	0
T11	124208	1208	0	0
T12	0	585	0	0
T13	0	1184	0	0
T24	140580	0	0	0
T35	0	1119	0	0
T36	0	1184	0	0
T37	591196	0	0	0
T38	561904	0	0	0
T39	1647608	0	0	0
T40	1135296	0	0	0
T41	240880	0	0	0
T42	354576	0	0	0
T43	487948	0	0	0
T44	3228984	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	141468	141124	0	0
T2	69852	69620	0	0
T3	1213580	1213544	0	0
T4	473860	473832	0	0
T5	436748	436512	0	0
T6	993364	993336	0	0
T7	98148	97672	0	0
T17	234628	234292	0	0
T18	15936	15628	0	0
T19	854296	854248	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	141468	141124	0	0
T2	69852	69620	0	0
T3	1213580	1213544	0	0
T4	473860	473832	0	0
T5	436748	436512	0	0
T6	993364	993336	0	0
T7	98148	97672	0	0
T17	234628	234292	0	0
T18	15936	15628	0	0
T19	854296	854248	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T18,T19
1	0	1	Covered	T3,T4,T19
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T2,T19,T78

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T78
0	1	Covered	T32,T54,T87
1	0	Covered	T94,T95,T96

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T19,T78
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T94,T95,T96

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T78
1	0	Not Covered
1	1	Covered	T32,T54,T87

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T15,T67,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T19,T15,T65

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T18
1	Covered	T2,T15,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T15
1	Covered	T3,T18,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T9,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T17
Phase1St	198	Covered	T2,T3,T17
Phase2St	215	Covered	T2,T3,T17
Phase3St	233	Covered	T2,T3,T18
TerminalSt	249	Covered	T2,T3,T18
TimeoutSt	159	Covered	T2,T19,T78

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T17
IdleSt->TimeoutSt	159	Covered	T2,T19,T78
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T56,T97,T38
Phase0St->Phase1St	198	Covered	T2,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T40,T98
Phase1St->Phase2St	215	Covered	T2,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T22,T99
Phase2St->Phase3St	233	Covered	T2,T3,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T53,T91,T100
Phase3St->TerminalSt	249	Covered	T2,T3,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T18,T19,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T78
TimeoutSt->Phase0St	172	Covered	T32,T54,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T78
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T32,T54,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T78
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T78
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T56,T97,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T40,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T22,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T53,T91,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T15,T65
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682088530	321	0	0
CheckAccumTrig0_A	682088530	481	0	0
CheckAccumTrig1_A	682088530	12	0	0
CheckClr_A	682088530	200	0	0
CheckEn_A	681876412	343738143	0	0
CheckPhase0_A	682088530	535	0	0
CheckPhase1_A	682088530	528	0	0
CheckPhase2_A	682088530	517	0	0
CheckPhase3_A	682088530	510	0	0
CheckTimeout0_A	682088530	779	0	0
CheckTimeoutSt1_A	682088530	95484	0	0
CheckTimeoutSt2_A	682088530	716	0	0
CheckTimeoutStTrig_A	682088530	49	0	0
ErrorStAllEscAsserted_A	682088530	1635	0	0
ErrorStIsTerminal_A	682088530	1365	0	0
EscStateOut_A	681875695	681807296	0	0
u_state_regs_A	682088530	681905001	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	321	0	0
T11	31052	92	0	0
T12	0	26	0	0
T13	0	52	0	0
T24	35145	0	0	0
T35	0	66	0	0
T36	0	85	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	481	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	10	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T65	0	7	0	0
T67	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	12	0	0
T93	399370	0	0	0
T95	88438	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	78563	0	0	0
T110	6035	0	0	0
T111	186642	0	0	0
T112	12024	0	0	0
T113	14270	0	0	0
T114	71786	0	0	0
T115	392451	0	0	0
T116	734720	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	200	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	0	5	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	0	0	0
T20	63049	0	0	0
T22	0	2	0	0
T26	3232	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T45	85445	0	0	0
T49	0	1	0	0
T65	0	6	0	0
T67	0	2	0	0
T74	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681876412	343738143	0	0
T1	35367	35280	0	0
T2	17463	9803	0	0
T3	303395	2071	0	0
T4	118465	108988	0	0
T5	109187	109127	0	0
T6	248341	248334	0	0
T7	24537	2544	0	0
T17	58657	48755	0	0
T18	3984	1964	0	0
T19	213574	150207	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	535	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	10	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T65	0	7	0	0
T67	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	528	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	10	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T65	0	7	0	0
T67	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	517	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	10	0	0
T17	58657	0	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T65	0	7	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	510	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	10	0	0
T17	58657	0	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T65	0	7	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	779	0	0
T2	17463	1	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	1	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	3	0	0
T32	0	4	0	0
T68	0	1	0	0
T69	0	5	0	0
T78	0	5	0	0
T79	0	9	0	0
T82	0	1	0	0
T83	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	95484	0	0
T2	17463	57	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	102	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	543	0	0
T32	0	560	0	0
T68	0	202	0	0
T69	0	494	0	0
T78	0	384	0	0
T79	0	973	0	0
T82	0	85	0	0
T83	0	926	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	716	0	0
T2	17463	1	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	1	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	2	0	0
T32	0	3	0	0
T68	0	1	0	0
T69	0	5	0	0
T78	0	5	0	0
T79	0	9	0	0
T82	0	1	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	49	0	0
T27	77014	0	0	0
T32	296356	1	0	0
T33	381180	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T61	0	1	0	0
T69	359096	0	0	0
T70	101871	0	0	0
T71	688701	0	0	0
T72	2751	0	0	0
T73	122177	0	0	0
T74	327195	0	0	0
T75	23155	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T117	0	5	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1635	0	0
T11	31052	403	0	0
T12	0	178	0	0
T13	0	334	0	0
T24	35145	0	0	0
T35	0	349	0	0
T36	0	371	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1365	0	0
T11	31052	343	0	0
T12	0	148	0	0
T13	0	274	0	0
T24	35145	0	0	0
T35	0	289	0	0
T36	0	311	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681875695	681807296	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	681905001	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T4,T5,T17
1	1	0	Covered	T2,T18,T19
1	1	1	Covered	T1,T5,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T19
0	1	Covered	T1,T5,T30
1	0	Covered	T15,T22,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T22,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T23
1	1	Covered	T1,T5,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T26,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T5,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T17
1	Covered	T2,T3,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T14,T46

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T19,T45

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T5,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T1,T5,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T121,T91
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T22,T33
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T52,T122
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T54,T123
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T5,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T78,T21
TimeoutSt->Phase0St	172	Covered	T1,T5,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T78,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T121,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T22,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T52,T122
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T54,T123
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682088530	299	0	0
CheckAccumTrig0_A	682088530	814	0	0
CheckAccumTrig1_A	682088530	44	0	0
CheckClr_A	682088530	391	0	0
CheckEn_A	681876412	249242609	0	0
CheckPhase0_A	682088530	908	0	0
CheckPhase1_A	682088530	891	0	0
CheckPhase2_A	682088530	874	0	0
CheckPhase3_A	682088530	855	0	0
CheckTimeout0_A	682088530	1140	0	0
CheckTimeoutSt1_A	682088530	124176	0	0
CheckTimeoutSt2_A	682088530	1022	0	0
CheckTimeoutStTrig_A	682088530	72	0	0
ErrorStAllEscAsserted_A	682088530	1559	0	0
ErrorStIsTerminal_A	682088530	1289	0	0
EscStateOut_A	681875695	681807296	0	0
u_state_regs_A	682088530	681905001	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	299	0	0
T11	31052	78	0	0
T12	0	35	0	0
T13	0	46	0	0
T24	35145	0	0	0
T35	0	59	0	0
T36	0	81	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	814	0	0
T2	17463	1	0	0
T3	303395	4	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T14	0	1	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	1	0	0
T20	0	6	0	0
T26	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	44	0	0
T10	946157	0	0	0
T15	306027	1	0	0
T16	19802	0	0	0
T22	0	1	0	0
T30	6241	0	0	0
T31	405328	0	0	0
T47	737134	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T65	327279	0	0	0
T66	7977	0	0	0
T67	409663	0	0	0
T68	186474	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	391	0	0
T3	303395	3	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	3	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	0	0	0
T20	63049	5	0	0
T21	0	4	0	0
T22	0	1	0	0
T30	0	1	0	0
T46	0	2	0	0
T49	0	2	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681876412	249242609	0	0
T1	35367	3013	0	0
T2	17463	6778	0	0
T3	303395	2030	0	0
T4	118465	210962	0	0
T5	109187	8138	0	0
T6	248341	248334	0	0
T7	24537	2500	0	0
T17	58657	7505	0	0
T18	3984	2524	0	0
T19	213574	981638	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	908	0	0
T1	35367	1	0	0
T2	17463	1	0	0
T3	303395	4	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T14	0	1	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	1	0	0
T20	0	6	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	891	0	0
T1	35367	1	0	0
T2	17463	1	0	0
T3	303395	4	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T14	0	1	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	1	0	0
T20	0	6	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	874	0	0
T1	35367	1	0	0
T2	17463	1	0	0
T3	303395	4	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T14	0	1	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	1	0	0
T20	0	6	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	855	0	0
T1	35367	1	0	0
T2	17463	1	0	0
T3	303395	4	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T14	0	1	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	1	0	0
T20	0	6	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1140	0	0
T1	35367	1	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	3	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	38	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	0	2	0	0
T66	0	1	0	0
T68	0	246	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	124176	0	0
T1	35367	66	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	28	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	946	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	5903	0	0
T21	0	130	0	0
T22	0	438	0	0
T30	0	845	0	0
T66	0	61	0	0
T68	0	24215	0	0
T78	0	94	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1022	0	0
T8	528666	0	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	0	2	0	0
T19	213574	37	0	0
T20	63049	0	0	0
T21	49673	2	0	0
T26	3232	0	0	0
T27	0	2	0	0
T30	0	1	0	0
T32	0	16	0	0
T45	85445	0	0	0
T46	21075	0	0	0
T66	0	1	0	0
T68	0	246	0	0
T78	10663	1	0	0
T81	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	72	0	0
T1	35367	1	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T30	0	1	0	0
T51	0	1	0	0
T54	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1559	0	0
T11	31052	318	0	0
T12	0	175	0	0
T13	0	368	0	0
T24	35145	0	0	0
T35	0	339	0	0
T36	0	359	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1289	0	0
T11	31052	258	0	0
T12	0	145	0	0
T13	0	308	0	0
T24	35145	0	0	0
T35	0	279	0	0
T36	0	299	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681875695	681807296	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	681905001	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T3,T4,T19
1	1	0	Covered	T5,T17,T19
1	1	1	Covered	T1,T17,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T19
0	1	Covered	T1,T19,T22
1	0	Covered	T32,T27,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T27,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T19
1	0	Covered	T24,T124
1	1	Covered	T1,T19,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T15,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T15,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T3,T17,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T2,T19,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T19,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T17,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T17
IdleSt->TimeoutSt	159	Covered	T1,T17,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T125,T38,T62
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T126,T96,T127
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T125,T127
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T128,T129,T130
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T17,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T78,T15
TimeoutSt->Phase0St	172	Covered	T1,T19,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T78,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T125,T131,T132
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T126,T96,T127
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T125,T127
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T128,T129,T130
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T17,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682088530	316	0	0
CheckAccumTrig0_A	682088530	442	0	0
CheckAccumTrig1_A	682088530	19	0	0
CheckClr_A	682088530	190	0	0
CheckEn_A	681876412	347732220	0	0
CheckPhase0_A	682088530	523	0	0
CheckPhase1_A	682088530	518	0	0
CheckPhase2_A	682088530	506	0	0
CheckPhase3_A	682088530	503	0	0
CheckTimeout0_A	682088530	952	0	0
CheckTimeoutSt1_A	682088530	91258	0	0
CheckTimeoutSt2_A	682088530	862	0	0
CheckTimeoutStTrig_A	682088530	70	0	0
ErrorStAllEscAsserted_A	682088530	1558	0	0
ErrorStIsTerminal_A	682088530	1288	0	0
EscStateOut_A	681875695	681807296	0	0
u_state_regs_A	682088530	681905001	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	316	0	0
T11	31052	78	0	0
T12	0	36	0	0
T13	0	97	0	0
T24	35145	0	0	0
T35	0	54	0	0
T36	0	51	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	442	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T15	0	12	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	0	0	0
T22	0	2	0	0
T31	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	19	0	0
T23	0	1	0	0
T27	77014	1	0	0
T32	296356	1	0	0
T33	381180	0	0	0
T40	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	359096	0	0	0
T70	101871	0	0	0
T71	688701	0	0	0
T72	2751	0	0	0
T73	122177	0	0	0
T74	327195	0	0	0
T75	23155	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	190	0	0
T1	35367	1	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	7	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	3	0	0
T22	0	1	0	0
T27	0	1	0	0
T34	0	1	0	0
T50	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681876412	347732220	0	0
T1	35367	3026	0	0
T2	17463	586	0	0
T3	303395	9222	0	0
T4	118465	111771	0	0
T5	109187	103700	0	0
T6	248341	248334	0	0
T7	24537	2510	0	0
T17	58657	46446	0	0
T18	3984	586	0	0
T19	213574	757607	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	523	0	0
T1	35367	2	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	12	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	3	0	0
T31	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	518	0	0
T1	35367	2	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	12	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	3	0	0
T31	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	506	0	0
T1	35367	2	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	11	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	3	0	0
T31	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	503	0	0
T1	35367	2	0	0
T2	17463	1	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	11	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	3	0	0
T31	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	952	0	0
T1	35367	2	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	15	0	0
T17	58657	2	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	1	0	0
T32	0	4	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	8	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	91258	0	0
T1	35367	188	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T15	0	1854	0	0
T17	58657	195	0	0
T18	3984	0	0	0
T19	213574	753	0	0
T22	0	628	0	0
T32	0	299	0	0
T78	0	66	0	0
T79	0	651	0	0
T80	0	853	0	0
T81	0	159	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	862	0	0
T7	24537	0	0	0
T8	528666	0	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T15	0	15	0	0
T17	58657	2	0	0
T18	3984	0	0	0
T19	213574	0	0	0
T20	63049	0	0	0
T26	3232	0	0	0
T27	0	3	0	0
T32	0	3	0	0
T34	0	3	0	0
T45	85445	0	0	0
T74	0	2	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	8	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	70	0	0
T1	35367	2	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	0	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	5	0	0
T22	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T81	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1558	0	0
T11	31052	364	0	0
T12	0	180	0	0
T13	0	349	0	0
T24	35145	0	0	0
T35	0	328	0	0
T36	0	337	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1288	0	0
T11	31052	304	0	0
T12	0	150	0	0
T13	0	289	0	0
T24	35145	0	0	0
T35	0	268	0	0
T36	0	277	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681875695	681807296	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	681905001	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T3,T4,T6
1	1	0	Covered	T2,T19,T78
1	1	1	Covered	T1,T5,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T19
0	1	Covered	T19,T32,T53
1	0	Covered	T21,T27,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T27,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T25
1	1	Covered	T19,T32,T53

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T19,T77,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T5,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T47,T67,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T2,T3,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T6,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T5
Phase1St	198	Covered	T2,T3,T5
Phase2St	215	Covered	T2,T3,T5
Phase3St	233	Covered	T2,T3,T5
TerminalSt	249	Covered	T2,T3,T5
TimeoutSt	159	Covered	T1,T5,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T1,T5,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T29,T61
Phase0St->Phase1St	198	Covered	T2,T3,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T53,T55,T133
Phase1St->Phase2St	215	Covered	T2,T3,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T27,T134
Phase2St->Phase3St	233	Covered	T2,T3,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T18,T34,T53
Phase3St->TerminalSt	249	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T5,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T5,T19
TimeoutSt->Phase0St	172	Covered	T19,T21,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T29,T61
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T53,T55,T133
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T27,T134
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T34,T53
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682088530	299	0	0
CheckAccumTrig0_A	682088530	510	0	0
CheckAccumTrig1_A	682088530	20	0	0
CheckClr_A	682088530	243	0	0
CheckEn_A	681876412	296371678	0	0
CheckPhase0_A	682088530	578	0	0
CheckPhase1_A	682088530	571	0	0
CheckPhase2_A	682088530	563	0	0
CheckPhase3_A	682088530	556	0	0
CheckTimeout0_A	682088530	821	0	0
CheckTimeoutSt1_A	682088530	107437	0	0
CheckTimeoutSt2_A	682088530	734	0	0
CheckTimeoutStTrig_A	682088530	64	0	0
ErrorStAllEscAsserted_A	682088530	1608	0	0
ErrorStIsTerminal_A	682088530	1338	0	0
EscStateOut_A	681875695	681807296	0	0
u_state_regs_A	682088530	681905001	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	299	0	0
T11	31052	67	0	0
T12	0	49	0	0
T13	0	49	0	0
T24	35145	0	0	0
T35	0	75	0	0
T36	0	59	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	510	0	0
T2	17463	2	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	1	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	2	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	1	0	0
T77	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	20	0	0
T10	946157	0	0	0
T15	306027	0	0	0
T16	19802	0	0	0
T21	49673	1	0	0
T23	0	1	0	0
T27	0	2	0	0
T30	6241	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T47	737134	0	0	0
T53	0	1	0	0
T65	327279	0	0	0
T66	7977	0	0	0
T67	409663	0	0	0
T77	100272	0	0	0
T97	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	243	0	0
T2	17463	1	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	58657	0	0	0
T18	3984	1	0	0
T19	213574	0	0	0
T27	0	4	0	0
T32	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681876412	296371678	0	0
T1	35367	3052	0	0
T2	17463	2076	0	0
T3	303395	2057	0	0
T4	118465	84032	0	0
T5	109187	8196	0	0
T6	248341	3088	0	0
T7	24537	2530	0	0
T17	58657	2108	0	0
T18	3984	1964	0	0
T19	213574	567541	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	578	0	0
T2	17463	2	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	1	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	2	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	2	0	0
T21	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	571	0	0
T2	17463	2	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	1	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	2	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	2	0	0
T21	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	563	0	0
T2	17463	2	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	1	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	2	0	0
T17	58657	1	0	0
T18	3984	1	0	0
T19	213574	2	0	0
T21	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	556	0	0
T2	17463	2	0	0
T3	303395	1	0	0
T4	118465	0	0	0
T5	109187	2	0	0
T6	248341	1	0	0
T7	24537	0	0	0
T8	528666	1	0	0
T9	0	2	0	0
T17	58657	1	0	0
T18	3984	0	0	0
T19	213574	2	0	0
T21	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	821	0	0
T1	35367	2	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	66	0	0
T21	0	1	0	0
T22	0	1	0	0
T27	0	2	0	0
T32	0	10	0	0
T34	0	4	0	0
T68	0	209	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	107437	0	0
T1	35367	368	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	28	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	8756	0	0
T21	0	1	0	0
T22	0	71	0	0
T27	0	2	0	0
T32	0	1437	0	0
T34	0	656	0	0
T68	0	21221	0	0
T84	0	31	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	734	0	0
T1	35367	2	0	0
T2	17463	0	0	0
T3	303395	0	0	0
T4	118465	0	0	0
T5	109187	1	0	0
T6	248341	0	0	0
T7	24537	0	0	0
T17	58657	0	0	0
T18	3984	0	0	0
T19	213574	64	0	0
T22	0	1	0	0
T32	0	9	0	0
T34	0	4	0	0
T53	0	3	0	0
T68	0	209	0	0
T84	0	1	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	64	0	0
T8	528666	0	0	0
T9	166829	0	0	0
T14	899454	0	0	0
T19	213574	1	0	0
T20	63049	0	0	0
T21	49673	0	0	0
T26	3232	0	0	0
T32	0	1	0	0
T45	85445	0	0	0
T46	21075	0	0	0
T53	0	1	0	0
T55	0	4	0	0
T78	10663	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	3	0	0
T138	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1608	0	0
T11	31052	363	0	0
T12	0	172	0	0
T13	0	373	0	0
T24	35145	0	0	0
T35	0	343	0	0
T36	0	357	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	1338	0	0
T11	31052	303	0	0
T12	0	142	0	0
T13	0	313	0	0
T24	35145	0	0	0
T35	0	283	0	0
T36	0	297	0	0
T37	147799	0	0	0
T38	140476	0	0	0
T39	411902	0	0	0
T40	283824	0	0	0
T41	60220	0	0	0
T42	88644	0	0	0
T43	121987	0	0	0
T44	807246	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681875695	681807296	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682088530	681905001	0	0
T1	35367	35281	0	0
T2	17463	17405	0	0
T3	303395	303386	0	0
T4	118465	118458	0	0
T5	109187	109128	0	0
T6	248341	248334	0	0
T7	24537	24418	0	0
T17	58657	58573	0	0
T18	3984	3907	0	0
T19	213574	213562	0	0