Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T115,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13929	0	0
DisabledNoTrigBkwd_A	2147483647	773926	0	0
DisabledNoTrigFwd_A	2147483647	1680037327	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13929	0	0
T22	48047	0	0	0
T39	4274	1132	0	0
T66	138267	0	0	0
T72	76213	0	0	0
T73	410365	0	0	0
T80	26349	0	0	0
T115	3176	776	0	0
T116	24045	0	0	0
T117	822565	0	0	0
T118	35327	0	0	0
T200	0	469	0	0
T201	3706	329	0	0
T202	3157	839	0	0
T203	1133	245	0	0
T204	0	135	0	0
T205	0	610	0	0
T206	0	846	0	0
T207	0	1027	0	0
T208	0	656	0	0
T209	0	976	0	0
T210	0	351	0	0
T211	0	604	0	0
T212	0	852	0	0
T213	0	1025	0	0
T214	0	1172	0	0
T215	0	685	0	0
T216	0	541	0	0
T217	0	659	0	0
T218	497600	0	0	0
T219	45774	0	0	0
T220	10412	0	0	0
T221	240782	0	0	0
T222	136229	0	0	0
T223	21918	0	0	0
T224	292612	0	0	0
T225	542708	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	773926	0	0
T1	485656	578	0	0
T2	1072620	414	0	0
T3	233264	35	0	0
T4	446488	9	0	0
T5	449676	20	0	0
T6	1578064	5857	0	0
T7	0	5380	0	0
T8	2527244	2878	0	0
T13	0	11945	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	1495	0	0
T26	0	2	0	0
T27	0	18	0	0
T45	0	274	0	0
T46	0	82	0	0
T47	0	371	0	0
T48	0	2	0	0
T49	0	885	0	0
T50	0	159	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1680037327	0	0
T1	485656	3207134	0	0
T2	1072620	549904	0	0
T3	233264	167800	0	0
T4	446488	292587	0	0
T5	449676	255055	0	0
T6	1578064	428790	0	0
T8	2527244	1733607	0	0
T16	49756	37793	0	0
T17	11680	9078	0	0
T18	29168	16218	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T203,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	720796785	4572	0	0
DisabledNoTrigBkwd_A	720796785	236921	0	0
DisabledNoTrigFwd_A	720796785	379641037	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	4572	0	0
T118	35327	0	0	0
T201	3706	329	0	0
T202	3157	0	0	0
T203	1133	245	0	0
T206	0	846	0	0
T210	0	351	0	0
T211	0	604	0	0
T213	0	1025	0	0
T214	0	1172	0	0
T220	10412	0	0	0
T221	240782	0	0	0
T222	136229	0	0	0
T223	21918	0	0	0
T224	292612	0	0	0
T225	542708	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	236921	0	0
T1	121414	277	0	0
T2	268155	2	0	0
T3	58316	35	0	0
T4	111622	8	0	0
T5	112419	0	0	0
T6	394516	1567	0	0
T7	0	9	0	0
T8	631811	209	0	0
T13	0	1722	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	1005	0	0
T45	0	274	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	379641037	0	0
T1	121414	710861	0	0
T2	268155	266517	0	0
T3	58316	7544	0	0
T4	111622	180985	0	0
T5	112419	12411	0	0
T6	394516	3109	0	0
T8	631811	332089	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	2962	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T115,T202,T204
1	1	Covered	T1,T2,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	720796785	4263	0	0
DisabledNoTrigBkwd_A	720796785	177265	0	0
DisabledNoTrigFwd_A	720796785	431573708	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	4263	0	0
T22	48047	0	0	0
T66	138267	0	0	0
T72	76213	0	0	0
T73	410365	0	0	0
T80	26349	0	0	0
T115	3176	776	0	0
T116	24045	0	0	0
T117	822565	0	0	0
T202	0	839	0	0
T204	0	135	0	0
T209	0	976	0	0
T212	0	852	0	0
T215	0	685	0	0
T218	497600	0	0	0
T219	45774	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	177265	0	0
T1	121414	131	0	0
T2	268155	412	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	2101	0	0
T8	631811	804	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	19	0	0
T27	0	6	0	0
T46	0	16	0	0
T47	0	247	0	0
T48	0	2	0	0
T49	0	884	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	431573708	0	0
T1	121414	946663	0	0
T2	268155	8145	0	0
T3	58316	53559	0	0
T4	111622	2098	0	0
T5	112419	144564	0	0
T6	394516	3125	0	0
T8	631811	511224	0	0
T16	12439	632	0	0
T17	2920	603	0	0
T18	7292	7240	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T208
1	1	Covered	T1,T5,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	720796785	1788	0	0
DisabledNoTrigBkwd_A	720796785	144201	0	0
DisabledNoTrigFwd_A	720796785	450903122	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1788	0	0
T39	4274	1132	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0
T85	9038	0	0	0
T208	0	656	0	0
T226	32422	0	0	0
T227	222904	0	0	0
T228	22893	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	144201	0	0
T1	121414	73	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	9	0	0
T6	394516	0	0	0
T7	0	2330	0	0
T8	631811	1179	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	132	0	0
T26	0	2	0	0
T27	0	12	0	0
T46	0	56	0	0
T49	0	1	0	0
T50	0	159	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	450903122	0	0
T1	121414	700983	0	0
T2	268155	267065	0	0
T3	58316	58216	0	0
T4	111622	107371	0	0
T5	112419	94921	0	0
T6	394516	393277	0	0
T8	631811	290597	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	3001	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T17
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T205,T207
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	720796785	3306	0	0
DisabledNoTrigBkwd_A	720796785	215539	0	0
DisabledNoTrigFwd_A	720796785	417919460	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	3306	0	0
T24	999678	0	0	0
T31	549645	0	0	0
T51	100849	0	0	0
T52	937700	0	0	0
T81	7582	0	0	0
T196	563487	0	0	0
T197	792159	0	0	0
T198	227002	0	0	0
T200	3865	469	0	0
T205	0	610	0	0
T207	0	1027	0	0
T216	0	541	0	0
T217	0	659	0	0
T229	127878	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	215539	0	0
T1	121414	97	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	11	0	0
T6	394516	2189	0	0
T7	0	3041	0	0
T8	631811	686	0	0
T13	0	10223	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	339	0	0
T46	0	10	0	0
T47	0	124	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	417919460	0	0
T1	121414	848627	0	0
T2	268155	8177	0	0
T3	58316	48481	0	0
T4	111622	2133	0	0
T5	112419	3159	0	0
T6	394516	29279	0	0
T8	631811	599697	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	3015	0	0