Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T16,T8
1	1	1	Covered	T1,T3,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T16
0	1	Covered	T8,T20,T21
1	0	Covered	T3,T8,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T8
1	1	Covered	T8,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T5,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T6,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T3,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T3,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T23,T24,T25
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T26,T27,T23
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T23,T28,T29
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T23,T30,T31
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T16,T17
TimeoutSt->Phase0St	172	Covered	T3,T8,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T23
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T30,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1450	0	0
CheckAccumTrig0_A	2147483647	2395	0	0
CheckAccumTrig1_A	2147483647	123	0	0
CheckClr_A	2147483647	1116	0	0
CheckEn_A	2147483647	1318481104	0	0
CheckPhase0_A	2147483647	2760	0	0
CheckPhase1_A	2147483647	2696	0	0
CheckPhase2_A	2147483647	2632	0	0
CheckPhase3_A	2147483647	2569	0	0
CheckTimeout0_A	2147483647	5041	0	0
CheckTimeoutSt1_A	2147483647	534586	0	0
CheckTimeoutSt2_A	2147483647	4631	0	0
CheckTimeoutStTrig_A	2147483647	282	0	0
ErrorStAllEscAsserted_A	2147483647	7249	0	0
ErrorStIsTerminal_A	2147483647	6049	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1450	0	0
T10	122688	327	0	0
T11	0	297	0	0
T12	0	330	0	0
T34	0	268	0	0
T35	0	228	0	0
T36	1497860	0	0	0
T37	1250764	0	0	0
T38	986360	0	0	0
T39	17096	0	0	0
T40	479068	0	0	0
T41	2097116	0	0	0
T42	1656376	0	0	0
T43	1340840	0	0	0
T44	309300	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T1	485656	19	0	0
T2	1072620	2	0	0
T3	233264	1	0	0
T4	446488	2	0	0
T5	449676	4	0	0
T6	1578064	11	0	0
T7	0	4	0	0
T8	2527244	6	0	0
T13	0	5	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	12	0	0
T26	0	2	0	0
T27	0	3	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	123	0	0
T3	58316	1	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	789032	0	0	0
T7	170795	0	0	0
T8	1263622	2	0	0
T9	915990	0	0	0
T13	290986	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	14584	0	0	0
T20	503910	0	0	0
T21	74404	0	0	0
T22	48047	1	0	0
T24	0	1	0	0
T26	16490	0	0	0
T28	0	1	0	0
T29	0	3	0	0
T45	8530	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	138267	0	0	0
T67	118149	0	0	0
T68	206443	0	0	0
T69	31735	0	0	0
T70	60964	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1116	0	0
T1	121414	7	0	0
T2	268155	0	0	0
T3	58316	1	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	789032	3	0	0
T7	341590	1	0	0
T8	1263622	1	0	0
T9	1831980	0	0	0
T13	145493	0	0	0
T14	23636	0	0	0
T15	22559	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	14584	0	0	0
T20	503910	6	0	0
T21	148808	0	0	0
T23	0	11	0	0
T26	32980	2	0	0
T27	0	3	0	0
T28	0	8	0	0
T30	0	1	0	0
T45	17060	0	0	0
T46	23149	0	0	0
T49	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T68	0	3	0	0
T69	0	1	0	0
T71	0	1	0	0
T72	0	8	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	27594	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1318481104	0	0
T1	485656	3163129	0	0
T2	1072620	291498	0	0
T3	233264	163156	0	0
T4	446488	292587	0	0
T5	449676	255055	0	0
T6	1578064	425961	0	0
T8	2527244	1480865	0	0
T16	49756	37790	0	0
T17	11680	9075	0	0
T18	29168	16217	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2760	0	0
T1	485656	19	0	0
T2	1072620	2	0	0
T3	233264	2	0	0
T4	446488	2	0	0
T5	449676	4	0	0
T6	1578064	11	0	0
T7	0	4	0	0
T8	2527244	12	0	0
T13	0	5	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	17	0	0
T21	0	1	0	0
T26	0	2	0	0
T27	0	4	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T1	485656	19	0	0
T2	1072620	2	0	0
T3	233264	2	0	0
T4	446488	2	0	0
T5	449676	4	0	0
T6	1578064	11	0	0
T7	0	4	0	0
T8	2527244	12	0	0
T13	0	5	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	17	0	0
T21	0	1	0	0
T26	0	1	0	0
T27	0	3	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2632	0	0
T1	485656	19	0	0
T2	1072620	2	0	0
T3	233264	2	0	0
T4	446488	2	0	0
T5	449676	4	0	0
T6	1578064	11	0	0
T7	0	4	0	0
T8	2527244	12	0	0
T13	0	5	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	17	0	0
T21	0	1	0	0
T26	0	1	0	0
T27	0	3	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T1	485656	19	0	0
T2	1072620	2	0	0
T3	233264	2	0	0
T4	446488	2	0	0
T5	449676	4	0	0
T6	1578064	10	0	0
T7	0	4	0	0
T8	2527244	12	0	0
T13	0	5	0	0
T16	49756	0	0	0
T17	11680	0	0	0
T18	29168	0	0	0
T20	0	17	0	0
T21	0	1	0	0
T26	0	1	0	0
T27	0	3	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5041	0	0
T1	242828	5	0	0
T2	536310	0	0	0
T3	174948	1	0	0
T4	334866	0	0	0
T5	449676	0	0	0
T6	1578064	0	0	0
T8	2527244	1075	0	0
T9	915990	0	0	0
T13	290986	0	0	0
T16	49756	6	0	0
T17	11680	1	0	0
T18	29168	2	0	0
T20	503910	6	0	0
T21	74404	7	0	0
T22	0	1	0	0
T23	0	73	0	0
T26	0	2	0	0
T27	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T69	0	1	0	0
T76	0	9	0	0
T77	0	19	0	0
T78	0	1	0	0
T79	0	3	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	534586	0	0
T1	242828	627	0	0
T2	536310	0	0	0
T3	174948	25	0	0
T4	334866	0	0	0
T5	449676	0	0	0
T6	1578064	0	0	0
T8	2527244	69456	0	0
T9	915990	0	0	0
T13	290986	0	0	0
T16	49756	466	0	0
T17	11680	70	0	0
T18	29168	495	0	0
T20	503910	1676	0	0
T21	74404	1609	0	0
T22	0	4	0	0
T23	0	13541	0	0
T26	0	222	0	0
T27	0	736	0	0
T45	0	505	0	0
T46	0	3	0	0
T69	0	80	0	0
T76	0	1882	0	0
T77	0	2631	0	0
T78	0	50	0	0
T79	0	542	0	0
T80	0	400	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4631	0	0
T1	242828	5	0	0
T2	536310	0	0	0
T3	116632	0	0	0
T4	223244	0	0	0
T5	337257	0	0	0
T6	1578064	0	0	0
T7	170795	0	0	0
T8	2527244	1069	0	0
T9	1831980	0	0	0
T13	290986	0	0	0
T16	37317	6	0	0
T17	8760	1	0	0
T18	29168	2	0	0
T20	503910	1	0	0
T21	148808	6	0	0
T23	0	66	0	0
T24	0	1	0	0
T26	16490	2	0	0
T27	0	1	0	0
T31	0	9	0	0
T45	8530	0	0	0
T46	0	1	0	0
T68	0	3	0	0
T69	0	2	0	0
T76	0	9	0	0
T77	0	13	0	0
T78	0	1	0	0
T79	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	282	0	0
T6	789032	0	0	0
T7	683180	0	0	0
T8	1263622	4	0	0
T9	3663960	0	0	0
T13	290986	0	0	0
T14	47272	0	0	0
T15	45118	0	0	0
T18	14584	0	0	0
T20	1007820	3	0	0
T21	297616	1	0	0
T23	0	12	0	0
T25	0	2	0	0
T26	65960	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T41	0	1	0	0
T45	34120	1	0	0
T46	46298	0	0	0
T52	0	6	0	0
T72	0	7	0	0
T76	55188	0	0	0
T77	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	6	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7249	0	0
T10	122688	1472	0	0
T11	0	1466	0	0
T12	0	1469	0	0
T34	0	1417	0	0
T35	0	1425	0	0
T36	1497860	0	0	0
T37	1250764	0	0	0
T38	986360	0	0	0
T39	17096	0	0	0
T40	479068	0	0	0
T41	2097116	0	0	0
T42	1656376	0	0	0
T43	1340840	0	0	0
T44	309300	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6049	0	0
T10	122688	1232	0	0
T11	0	1226	0	0
T12	0	1229	0	0
T34	0	1177	0	0
T35	0	1185	0	0
T36	1497860	0	0	0
T37	1250764	0	0	0
T38	986360	0	0	0
T39	17096	0	0	0
T40	479068	0	0	0
T41	2097116	0	0	0
T42	1656376	0	0	0
T43	1340840	0	0	0
T44	309300	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	485656	485432	0	0
T2	1072620	1072596	0	0
T3	233264	232864	0	0
T4	446488	446464	0	0
T5	449676	449656	0	0
T6	1578064	1578028	0	0
T8	2527244	2527192	0	0
T16	49756	49548	0	0
T17	11680	11300	0	0
T18	29168	28960	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	485656	485432	0	0
T2	1072620	1072596	0	0
T3	233264	232864	0	0
T4	446488	446464	0	0
T5	449676	449656	0	0
T6	1578064	1578028	0	0
T8	2527244	2527192	0	0
T16	49756	49548	0	0
T17	11680	11300	0	0
T18	29168	28960	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T8
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T8

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T18
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T16,T8,T20
1	1	1	Covered	T1,T8,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T18
0	1	Covered	T20,T27,T77
1	0	Covered	T22,T51,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T8,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T51,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T18
1	0	Not Covered
1	1	Covered	T20,T27,T77

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T20
1	Covered	T5,T20,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T26,T46,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T20,T7,T77

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T20,T26
1	Covered	T1,T8,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T20,T26,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T5,T8
Phase1St	198	Covered	T1,T5,T8
Phase2St	215	Covered	T1,T5,T8
Phase3St	233	Covered	T1,T5,T8
TerminalSt	249	Covered	T1,T5,T8
TimeoutSt	159	Covered	T1,T8,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T5,T8
IdleSt->TimeoutSt	159	Covered	T1,T8,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T88,T90
Phase0St->Phase1St	198	Covered	T1,T5,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T27,T84
Phase1St->Phase2St	215	Covered	T1,T5,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T91,T62,T63
Phase2St->Phase3St	233	Covered	T1,T5,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T51,T91
Phase3St->TerminalSt	249	Covered	T1,T5,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T8,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T8,T18
TimeoutSt->Phase0St	172	Covered	T20,T27,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T27,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T90,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T84
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T62,T63
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T51,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T26,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	720796785	401	0	0
CheckAccumTrig0_A	720796785	473	0	0
CheckAccumTrig1_A	720796785	19	0	0
CheckClr_A	720796785	208	0	0
CheckEn_A	720608589	365615591	0	0
CheckPhase0_A	720796785	556	0	0
CheckPhase1_A	720796785	546	0	0
CheckPhase2_A	720796785	539	0	0
CheckPhase3_A	720796785	524	0	0
CheckTimeout0_A	720796785	1609	0	0
CheckTimeoutSt1_A	720796785	168553	0	0
CheckTimeoutSt2_A	720796785	1517	0	0
CheckTimeoutStTrig_A	720796785	71	0	0
ErrorStAllEscAsserted_A	720796785	1813	0	0
ErrorStIsTerminal_A	720796785	1513	0	0
EscStateOut_A	720607632	720537232	0	0
u_state_regs_A	720796785	720599345	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	401	0	0
T10	30672	90	0	0
T11	0	85	0	0
T12	0	84	0	0
T34	0	71	0	0
T35	0	71	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	473	0	0
T1	121414	2	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	1	0	0
T6	394516	0	0	0
T7	0	2	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	1	0	0
T26	0	2	0	0
T27	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	19	0	0
T22	48047	1	0	0
T28	40815	0	0	0
T30	225677	0	0	0
T33	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T66	138267	0	0	0
T67	118149	0	0	0
T68	206443	0	0	0
T69	31735	0	0	0
T70	60964	0	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	19416	0	0	0
T98	284544	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	208	0	0
T7	170795	1	0	0
T9	915990	0	0	0
T14	23636	0	0	0
T15	22559	0	0	0
T20	251955	1	0	0
T21	74404	0	0	0
T23	0	3	0	0
T26	16490	2	0	0
T27	0	3	0	0
T45	8530	0	0	0
T46	23149	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T68	0	2	0	0
T75	0	1	0	0
T76	27594	0	0	0
T99	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720608589	365615591	0	0
T1	121414	694978	0	0
T2	268155	267065	0	0
T3	58316	58215	0	0
T4	111622	107371	0	0
T5	112419	94921	0	0
T6	394516	393277	0	0
T8	631811	290597	0	0
T16	12439	12386	0	0
T17	2920	2824	0	0
T18	7292	3001	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	556	0	0
T1	121414	2	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	1	0	0
T6	394516	0	0	0
T7	0	2	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T26	0	2	0	0
T27	0	3	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	546	0	0
T1	121414	2	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	1	0	0
T6	394516	0	0	0
T7	0	2	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T26	0	1	0	0
T27	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	539	0	0
T1	121414	2	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	1	0	0
T6	394516	0	0	0
T7	0	2	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T26	0	1	0	0
T27	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	524	0	0
T1	121414	2	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	1	0	0
T6	394516	0	0	0
T7	0	2	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T26	0	1	0	0
T27	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1609	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	674	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	1	0	0
T20	0	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T23	0	21	0	0
T27	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	168553	0	0
T1	121414	498	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	42854	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	247	0	0
T20	0	734	0	0
T21	0	734	0	0
T22	0	4	0	0
T23	0	5737	0	0
T27	0	736	0	0
T76	0	391	0	0
T77	0	41	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1517	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	674	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	1	0	0
T21	0	3	0	0
T23	0	16	0	0
T27	0	1	0	0
T31	0	9	0	0
T68	0	3	0	0
T76	0	2	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	71	0	0
T7	170795	0	0	0
T9	915990	0	0	0
T14	23636	0	0	0
T15	22559	0	0	0
T20	251955	1	0	0
T21	74404	0	0	0
T23	0	5	0	0
T26	16490	0	0	0
T27	0	1	0	0
T45	8530	0	0	0
T46	23149	0	0	0
T76	27594	0	0	0
T77	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1813	0	0
T10	30672	345	0	0
T11	0	365	0	0
T12	0	384	0	0
T34	0	343	0	0
T35	0	376	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1513	0	0
T10	30672	285	0	0
T11	0	305	0	0
T12	0	324	0	0
T34	0	283	0	0
T35	0	316	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720607632	720537232	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	720599345	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T1,T4,T8
1	1	0	Covered	T16,T8,T20
1	1	1	Covered	T1,T8,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T20,T77,T23
1	0	Covered	T77,T68,T101

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T8,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T77,T68,T101

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Not Covered
1	1	Covered	T20,T77,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T1,T4,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T5,T77,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T6,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T5
Phase1St	198	Covered	T1,T4,T5
Phase2St	215	Covered	T1,T4,T5
Phase3St	233	Covered	T1,T4,T5
TerminalSt	249	Covered	T1,T4,T5
TimeoutSt	159	Covered	T1,T8,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T8,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T33,T62
Phase0St->Phase1St	198	Covered	T1,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T77,T102,T103
Phase1St->Phase2St	215	Covered	T1,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T71,T68,T104
Phase2St->Phase3St	233	Covered	T1,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T105,T106
Phase3St->TerminalSt	249	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T8,T21
TimeoutSt->Phase0St	172	Covered	T20,T77,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T77,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T62
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T77,T103,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T71,T68,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T105,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	720796785	382	0	0
CheckAccumTrig0_A	720796785	543	0	0
CheckAccumTrig1_A	720796785	30	0	0
CheckClr_A	720796785	259	0	0
CheckEn_A	720608589	336705464	0	0
CheckPhase0_A	720796785	638	0	0
CheckPhase1_A	720796785	625	0	0
CheckPhase2_A	720796785	608	0	0
CheckPhase3_A	720796785	596	0	0
CheckTimeout0_A	720796785	914	0	0
CheckTimeoutSt1_A	720796785	103609	0	0
CheckTimeoutSt2_A	720796785	807	0	0
CheckTimeoutStTrig_A	720796785	75	0	0
ErrorStAllEscAsserted_A	720796785	1823	0	0
ErrorStIsTerminal_A	720796785	1523	0	0
EscStateOut_A	720607632	720537232	0	0
u_state_regs_A	720796785	720599345	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	382	0	0
T10	30672	92	0	0
T11	0	83	0	0
T12	0	84	0	0
T34	0	69	0	0
T35	0	54	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	543	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	3	0	0
T6	394516	6	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	4	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	30	0	0
T23	706527	0	0	0
T57	0	1	0	0
T68	0	1	0	0
T77	418216	3	0	0
T78	38069	0	0	0
T79	4260	0	0	0
T80	26349	0	0	0
T90	0	3	0	0
T101	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	36152	0	0	0
T114	143159	0	0	0
T115	3176	0	0	0
T116	24045	0	0	0
T117	822565	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	259	0	0
T1	121414	1	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	2	0	0
T6	394516	5	0	0
T8	631811	0	0	0
T13	0	3	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	1	0	0
T23	0	8	0	0
T46	0	2	0	0
T71	0	1	0	0
T77	0	8	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720608589	336705464	0	0
T1	121414	816487	0	0
T2	268155	8177	0	0
T3	58316	48480	0	0
T4	111622	2133	0	0
T5	112419	3159	0	0
T6	394516	26450	0	0
T8	631811	599697	0	0
T16	12439	12386	0	0
T17	2920	2824	0	0
T18	7292	3015	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	638	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	3	0	0
T6	394516	6	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	4	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	625	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	3	0	0
T6	394516	6	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	4	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	608	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	3	0	0
T6	394516	6	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	4	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	596	0	0
T1	121414	4	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	1	0	0
T5	112419	3	0	0
T6	394516	5	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	4	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	914	0	0
T1	121414	1	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	32	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T23	0	24	0	0
T46	0	1	0	0
T77	0	15	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	103609	0	0
T1	121414	129	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	6134	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	383	0	0
T21	0	275	0	0
T23	0	3264	0	0
T46	0	3	0	0
T77	0	2042	0	0
T78	0	50	0	0
T79	0	181	0	0
T80	0	400	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	807	0	0
T1	121414	1	0	0
T2	268155	0	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	32	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T21	0	1	0	0
T23	0	15	0	0
T46	0	1	0	0
T69	0	1	0	0
T77	0	11	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	75	0	0
T7	170795	0	0	0
T9	915990	0	0	0
T14	23636	0	0	0
T15	22559	0	0	0
T20	251955	2	0	0
T21	74404	0	0	0
T23	0	8	0	0
T26	16490	0	0	0
T32	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T45	8530	0	0	0
T46	23149	0	0	0
T58	0	1	0	0
T76	27594	0	0	0
T77	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T118	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1823	0	0
T10	30672	399	0	0
T11	0	342	0	0
T12	0	372	0	0
T34	0	366	0	0
T35	0	344	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1523	0	0
T10	30672	339	0	0
T11	0	282	0	0
T12	0	312	0	0
T34	0	306	0	0
T35	0	284	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720607632	720537232	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	720599345	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T16,T8,T20
1	1	1	Covered	T3,T8,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T18
0	1	Covered	T8,T77,T23
1	0	Covered	T3,T8,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T8,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T18
1	0	Not Covered
1	1	Covered	T8,T77,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T20,T78

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T20,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T8,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T8,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T25,T33
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T51,T119
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T29,T86
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T31,T55
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T8
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T8,T18,T21
TimeoutSt->Phase0St	172	Covered	T3,T8,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T8,T18,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T84,T86
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T51,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T86
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T31,T55
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	720796785	315	0	0
CheckAccumTrig0_A	720796785	867	0	0
CheckAccumTrig1_A	720796785	55	0	0
CheckClr_A	720796785	419	0	0
CheckEn_A	720608589	301789681	0	0
CheckPhase0_A	720796785	962	0	0
CheckPhase1_A	720796785	934	0	0
CheckPhase2_A	720796785	910	0	0
CheckPhase3_A	720796785	883	0	0
CheckTimeout0_A	720796785	1684	0	0
CheckTimeoutSt1_A	720796785	162279	0	0
CheckTimeoutSt2_A	720796785	1569	0	0
CheckTimeoutStTrig_A	720796785	59	0	0
ErrorStAllEscAsserted_A	720796785	1774	0	0
ErrorStIsTerminal_A	720796785	1474	0	0
EscStateOut_A	720607632	720537232	0	0
u_state_regs_A	720796785	720599345	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	315	0	0
T10	30672	60	0	0
T11	0	55	0	0
T12	0	73	0	0
T34	0	73	0	0
T35	0	54	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	867	0	0
T1	121414	12	0	0
T2	268155	1	0	0
T3	58316	1	0	0
T4	111622	1	0	0
T5	112419	0	0	0
T6	394516	2	0	0
T7	0	1	0	0
T8	631811	1	0	0
T13	0	1	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	55	0	0
T3	58316	1	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	1	0	0
T13	145493	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	251955	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T51	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	419	0	0
T1	121414	7	0	0
T2	268155	0	0	0
T3	58316	1	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	1	0	0
T8	631811	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T23	0	1	0	0
T28	0	8	0	0
T30	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720608589	301789681	0	0
T1	121414	705006	0	0
T2	268155	8111	0	0
T3	58316	2903	0	0
T4	111622	180985	0	0
T5	112419	12411	0	0
T6	394516	3109	0	0
T8	631811	303379	0	0
T16	12439	12386	0	0
T17	2920	2824	0	0
T18	7292	2962	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	962	0	0
T1	121414	12	0	0
T2	268155	1	0	0
T3	58316	2	0	0
T4	111622	1	0	0
T5	112419	0	0	0
T6	394516	2	0	0
T7	0	1	0	0
T8	631811	3	0	0
T13	0	1	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	934	0	0
T1	121414	12	0	0
T2	268155	1	0	0
T3	58316	2	0	0
T4	111622	1	0	0
T5	112419	0	0	0
T6	394516	2	0	0
T7	0	1	0	0
T8	631811	3	0	0
T13	0	1	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	910	0	0
T1	121414	12	0	0
T2	268155	1	0	0
T3	58316	2	0	0
T4	111622	1	0	0
T5	112419	0	0	0
T6	394516	2	0	0
T7	0	1	0	0
T8	631811	3	0	0
T13	0	1	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	883	0	0
T1	121414	12	0	0
T2	268155	1	0	0
T3	58316	2	0	0
T4	111622	1	0	0
T5	112419	0	0	0
T6	394516	2	0	0
T7	0	1	0	0
T8	631811	3	0	0
T13	0	1	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	4	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1684	0	0
T3	58316	1	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	348	0	0
T13	145493	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	1	0	0
T20	251955	0	0	0
T21	0	1	0	0
T23	0	28	0	0
T26	0	1	0	0
T69	0	1	0	0
T76	0	4	0	0
T77	0	2	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	162279	0	0
T3	58316	25	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	18814	0	0
T13	145493	0	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	248	0	0
T20	251955	0	0	0
T21	0	229	0	0
T23	0	4540	0	0
T26	0	52	0	0
T69	0	80	0	0
T76	0	832	0	0
T77	0	379	0	0
T79	0	181	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1569	0	0
T6	394516	0	0	0
T7	170795	0	0	0
T8	631811	346	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T18	7292	1	0	0
T20	251955	0	0	0
T21	74404	1	0	0
T23	0	27	0	0
T24	0	1	0	0
T26	16490	1	0	0
T45	8530	0	0	0
T69	0	1	0	0
T76	0	4	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	59	0	0
T6	394516	0	0	0
T7	170795	0	0	0
T8	631811	1	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T18	7292	0	0	0
T20	251955	0	0	0
T21	74404	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T26	16490	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T45	8530	0	0	0
T52	0	5	0	0
T77	0	1	0	0
T82	0	1	0	0
T84	0	6	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1774	0	0
T10	30672	356	0	0
T11	0	371	0	0
T12	0	351	0	0
T34	0	340	0	0
T35	0	356	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1474	0	0
T10	30672	296	0	0
T11	0	311	0	0
T12	0	291	0	0
T34	0	280	0	0
T35	0	296	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720607632	720537232	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	720599345	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T16,T17
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T8,T20
1	1	1	Covered	T16,T17,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T8
0	1	Covered	T8,T20,T21
1	0	Covered	T8,T55,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T17,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T55,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T8
1	0	Covered	T8
1	1	Covered	T8,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T20,T48,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T8,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T8,T20,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T8,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T8
Phase1St	198	Covered	T1,T2,T8
Phase2St	215	Covered	T1,T2,T8
Phase3St	233	Covered	T1,T2,T8
TerminalSt	249	Covered	T1,T2,T8
TimeoutSt	159	Covered	T16,T17,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T8
IdleSt->TimeoutSt	159	Covered	T16,T17,T8
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T111,T120
Phase0St->Phase1St	198	Covered	T1,T2,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T121,T122
Phase1St->Phase2St	215	Covered	T1,T2,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T75,T32
Phase2St->Phase3St	233	Covered	T1,T2,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T123,T90,T124
Phase3St->TerminalSt	249	Covered	T1,T2,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T8,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T17,T8
TimeoutSt->Phase0St	172	Covered	T8,T20,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T120
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T121,T122
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T75,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T123,T90,T124
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T6,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	720796785	352	0	0
CheckAccumTrig0_A	720796785	512	0	0
CheckAccumTrig1_A	720796785	19	0	0
CheckClr_A	720796785	230	0	0
CheckEn_A	720608589	314370368	0	0
CheckPhase0_A	720796785	604	0	0
CheckPhase1_A	720796785	591	0	0
CheckPhase2_A	720796785	575	0	0
CheckPhase3_A	720796785	566	0	0
CheckTimeout0_A	720796785	834	0	0
CheckTimeoutSt1_A	720796785	100145	0	0
CheckTimeoutSt2_A	720796785	738	0	0
CheckTimeoutStTrig_A	720796785	77	0	0
ErrorStAllEscAsserted_A	720796785	1839	0	0
ErrorStIsTerminal_A	720796785	1539	0	0
EscStateOut_A	720607632	720537232	0	0
u_state_regs_A	720796785	720599345	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	352	0	0
T10	30672	85	0	0
T11	0	74	0	0
T12	0	89	0	0
T34	0	55	0	0
T35	0	49	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	512	0	0
T1	121414	1	0	0
T2	268155	1	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	3	0	0
T8	631811	2	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	5	0	0
T27	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	19	0	0
T6	394516	0	0	0
T7	170795	0	0	0
T8	631811	1	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T18	7292	0	0	0
T20	251955	0	0	0
T21	74404	0	0	0
T26	16490	0	0	0
T45	8530	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	230	0	0
T6	394516	2	0	0
T7	170795	0	0	0
T8	631811	1	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T18	7292	0	0	0
T20	251955	5	0	0
T21	74404	0	0	0
T23	0	7	0	0
T26	16490	0	0	0
T45	8530	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T72	0	8	0	0
T74	0	2	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720608589	314370368	0	0
T1	121414	946658	0	0
T2	268155	8145	0	0
T3	58316	53558	0	0
T4	111622	2098	0	0
T5	112419	144564	0	0
T6	394516	3125	0	0
T8	631811	287192	0	0
T16	12439	632	0	0
T17	2920	603	0	0
T18	7292	7239	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	604	0	0
T1	121414	1	0	0
T2	268155	1	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	3	0	0
T8	631811	6	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	591	0	0
T1	121414	1	0	0
T2	268155	1	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	3	0	0
T8	631811	6	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	575	0	0
T1	121414	1	0	0
T2	268155	1	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	3	0	0
T8	631811	6	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	566	0	0
T1	121414	1	0	0
T2	268155	1	0	0
T3	58316	0	0	0
T4	111622	0	0	0
T5	112419	0	0	0
T6	394516	3	0	0
T8	631811	6	0	0
T16	12439	0	0	0
T17	2920	0	0	0
T18	7292	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	834	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	21	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T16	12439	6	0	0
T17	2920	1	0	0
T18	7292	0	0	0
T20	251955	3	0	0
T21	74404	2	0	0
T26	0	1	0	0
T45	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	100145	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	1654	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T16	12439	466	0	0
T17	2920	70	0	0
T18	7292	0	0	0
T20	251955	559	0	0
T21	74404	371	0	0
T26	0	170	0	0
T45	0	505	0	0
T76	0	659	0	0
T77	0	169	0	0
T79	0	180	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	738	0	0
T5	112419	0	0	0
T6	394516	0	0	0
T8	631811	17	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T16	12439	6	0	0
T17	2920	1	0	0
T18	7292	0	0	0
T20	251955	1	0	0
T21	74404	1	0	0
T23	0	8	0	0
T26	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	77	0	0
T6	394516	0	0	0
T7	170795	0	0	0
T8	631811	3	0	0
T9	915990	0	0	0
T13	145493	0	0	0
T18	7292	0	0	0
T20	251955	2	0	0
T21	74404	1	0	0
T23	0	6	0	0
T26	16490	0	0	0
T33	0	1	0	0
T41	0	1	0	0
T45	8530	1	0	0
T52	0	1	0	0
T72	0	7	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1839	0	0
T10	30672	372	0	0
T11	0	388	0	0
T12	0	362	0	0
T34	0	368	0	0
T35	0	349	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	1539	0	0
T10	30672	312	0	0
T11	0	328	0	0
T12	0	302	0	0
T34	0	308	0	0
T35	0	289	0	0
T36	374465	0	0	0
T37	312691	0	0	0
T38	246590	0	0	0
T39	4274	0	0	0
T40	119767	0	0	0
T41	524279	0	0	0
T42	414094	0	0	0
T43	335210	0	0	0
T44	77325	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720607632	720537232	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720796785	720599345	0	0
T1	121414	121358	0	0
T2	268155	268149	0	0
T3	58316	58216	0	0
T4	111622	111616	0	0
T5	112419	112414	0	0
T6	394516	394507	0	0
T8	631811	631798	0	0
T16	12439	12387	0	0
T17	2920	2825	0	0
T18	7292	7240	0	0