Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65795583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31999412

1

T1

2001

T2

112896

T3

1006

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14943577	1			T1	2539		T2	44371		T3	533
values[0x0]	40288430	1			T1	1261		T2	157968		T3	1289
values[0x1]	42562988	1			T1	1279		T2	158112		T3	1275

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56031075	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41763920

1

T1

2460

T2

143153

T3

1274

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	323919	1			T1	19		T2	1387		T3	11
valid_sources[0x01]	708664	1			T1	22		T2	1400		T3	12
valid_sources[0x02]	327819	1			T1	26		T2	1353		T3	7
valid_sources[0x03]	312778	1			T1	40		T2	1326		T3	12
valid_sources[0x04]	318083	1			T1	23		T2	1489		T3	17
valid_sources[0x05]	314407	1			T1	20		T2	1306		T3	17
valid_sources[0x06]	318836	1			T1	22		T2	1399		T3	18
valid_sources[0x07]	314614	1			T1	33		T2	1357		T3	13
valid_sources[0x08]	549952	1			T1	20		T2	1424		T3	23
valid_sources[0x09]	321960	1			T1	20		T2	1387		T3	9
valid_sources[0x0a]	1278021	1			T1	19		T2	1360		T3	13
valid_sources[0x0b]	314510	1			T1	21		T2	1452		T3	13
valid_sources[0x0c]	316639	1			T1	17		T2	1412		T3	16
valid_sources[0x0d]	637635	1			T1	15		T2	1394		T3	9
valid_sources[0x0e]	315932	1			T1	9		T2	1453		T3	8
valid_sources[0x0f]	309240	1			T1	17		T2	1343		T3	11
valid_sources[0x10]	320389	1			T1	19		T2	1351		T3	16
valid_sources[0x11]	318856	1			T1	31		T2	1358		T3	15
valid_sources[0x12]	312076	1			T1	30		T2	1358		T3	16
valid_sources[0x13]	316098	1			T1	23		T2	1482		T3	12
valid_sources[0x14]	713680	1			T1	20		T2	1450		T3	12
valid_sources[0x15]	316658	1			T1	36		T2	1497		T3	10
valid_sources[0x16]	332143	1			T1	14		T2	1415		T3	9
valid_sources[0x17]	315005	1			T1	28		T2	1402		T3	14
valid_sources[0x18]	316930	1			T1	17		T2	1300		T3	16
valid_sources[0x19]	319962	1			T1	30		T2	1422		T3	11
valid_sources[0x1a]	312049	1			T1	17		T2	1400		T3	4
valid_sources[0x1b]	591045	1			T1	23		T2	1461		T3	21
valid_sources[0x1c]	314303	1			T1	24		T2	1367		T3	10
valid_sources[0x1d]	320792	1			T1	19		T2	1443		T3	21
valid_sources[0x1e]	532949	1			T1	18		T2	1511		T3	12
valid_sources[0x1f]	313777	1			T1	22		T2	1383		T3	16
valid_sources[0x20]	315279	1			T1	22		T2	1435		T3	11
valid_sources[0x21]	623328	1			T1	18		T2	1417		T3	16
valid_sources[0x22]	317747	1			T1	19		T2	1345		T3	12
valid_sources[0x23]	1142158	1			T1	15		T2	1512		T3	6
valid_sources[0x24]	334197	1			T1	17		T2	1382		T3	11
valid_sources[0x25]	322989	1			T1	16		T2	1379		T3	10
valid_sources[0x26]	320687	1			T1	16		T2	1462		T3	9
valid_sources[0x27]	1141182	1			T1	23		T2	1454		T3	11
valid_sources[0x28]	315344	1			T1	10		T2	1401		T3	19
valid_sources[0x29]	322590	1			T1	20		T2	1439		T3	8
valid_sources[0x2a]	316381	1			T1	25		T2	1329		T3	15
valid_sources[0x2b]	327714	1			T1	23		T2	1476		T3	14
valid_sources[0x2c]	328362	1			T1	18		T2	1291		T3	8
valid_sources[0x2d]	944034	1			T1	21		T2	1409		T3	14
valid_sources[0x2e]	352761	1			T1	31		T2	1412		T3	9
valid_sources[0x2f]	1121358	1			T1	17		T2	1415		T3	10
valid_sources[0x30]	923729	1			T1	25		T2	1459		T3	8
valid_sources[0x31]	377758	1			T1	23		T2	1314		T3	16
valid_sources[0x32]	316282	1			T1	14		T2	1395		T3	4
valid_sources[0x33]	319638	1			T1	19		T2	1381		T3	8
valid_sources[0x34]	319017	1			T1	23		T2	1493		T3	14
valid_sources[0x35]	692025	1			T1	9		T2	1433		T3	10
valid_sources[0x36]	320228	1			T1	13		T2	1441		T3	24
valid_sources[0x37]	763150	1			T1	14		T2	1358		T3	8
valid_sources[0x38]	313798	1			T1	39		T2	1408		T3	14
valid_sources[0x39]	313443	1			T1	27		T2	1385		T3	13
valid_sources[0x3a]	325040	1			T1	17		T2	1505		T3	10
valid_sources[0x3b]	725580	1			T1	18		T2	1342		T3	12
valid_sources[0x3c]	322308	1			T1	22		T2	1394		T3	11
valid_sources[0x3d]	315883	1			T1	24		T2	1359		T3	11
valid_sources[0x3e]	346258	1			T1	8		T2	1371		T3	9
valid_sources[0x3f]	319306	1			T1	20		T2	1373		T3	19
valid_sources[0x40]	655487	1			T1	19		T2	1332		T3	11
valid_sources[0x41]	311411	1			T1	24		T2	1372		T3	8
valid_sources[0x42]	334423	1			T1	27		T2	1385		T3	15
valid_sources[0x43]	318228	1			T1	21		T2	1443		T3	23
valid_sources[0x44]	319645	1			T1	26		T2	1400		T3	16
valid_sources[0x45]	318590	1			T1	18		T2	1370		T3	16
valid_sources[0x46]	322344	1			T1	16		T2	1296		T3	15
valid_sources[0x47]	315536	1			T1	18		T2	1386		T3	12
valid_sources[0x48]	314528	1			T1	22		T2	1399		T3	14
valid_sources[0x49]	324169	1			T1	26		T2	1433		T3	3
valid_sources[0x4a]	324860	1			T1	27		T2	1455		T3	15
valid_sources[0x4b]	316937	1			T1	11		T2	1366		T3	12
valid_sources[0x4c]	330070	1			T1	15		T2	1425		T3	19
valid_sources[0x4d]	321892	1			T1	23		T2	1421		T3	13
valid_sources[0x4e]	312809	1			T1	20		T2	1380		T3	10
valid_sources[0x4f]	632154	1			T1	18		T2	1431		T3	10
valid_sources[0x50]	321741	1			T1	21		T2	1482		T3	16
valid_sources[0x51]	319167	1			T1	19		T2	1462		T3	8
valid_sources[0x52]	318096	1			T1	19		T2	1463		T3	10
valid_sources[0x53]	319741	1			T1	23		T2	1460		T3	12
valid_sources[0x54]	320059	1			T1	21		T2	1333		T3	18
valid_sources[0x55]	317419	1			T1	18		T2	1461		T3	10
valid_sources[0x56]	319308	1			T1	17		T2	1440		T3	13
valid_sources[0x57]	315057	1			T1	17		T2	1399		T3	21
valid_sources[0x58]	328299	1			T1	20		T2	1348		T3	14
valid_sources[0x59]	354061	1			T1	13		T2	1496		T3	14
valid_sources[0x5a]	550696	1			T1	21		T2	1359		T3	11
valid_sources[0x5b]	311784	1			T1	23		T2	1472		T3	16
valid_sources[0x5c]	312481	1			T1	23		T2	1338		T3	10
valid_sources[0x5d]	318896	1			T1	19		T2	1398		T3	13
valid_sources[0x5e]	316959	1			T1	15		T2	1375		T3	11
valid_sources[0x5f]	317576	1			T1	17		T2	1363		T3	10
valid_sources[0x60]	318466	1			T1	16		T2	1395		T3	12
valid_sources[0x61]	320145	1			T1	8		T2	1422		T3	14
valid_sources[0x62]	316191	1			T1	22		T2	1402		T3	17
valid_sources[0x63]	321985	1			T1	20		T2	1417		T3	9
valid_sources[0x64]	734446	1			T1	9		T2	1396		T3	8
valid_sources[0x65]	317750	1			T1	14		T2	1403		T3	14
valid_sources[0x66]	849752	1			T1	20		T2	1413		T3	11
valid_sources[0x67]	328157	1			T1	13		T2	1382		T3	13
valid_sources[0x68]	315044	1			T1	18		T2	1434		T3	13
valid_sources[0x69]	315689	1			T1	29		T2	1506		T3	6
valid_sources[0x6a]	338196	1			T1	20		T2	1339		T3	7
valid_sources[0x6b]	323300	1			T1	13		T2	1416		T3	25
valid_sources[0x6c]	314598	1			T1	15		T2	1348		T3	12
valid_sources[0x6d]	551569	1			T1	19		T2	1418		T3	18
valid_sources[0x6e]	313929	1			T1	22		T2	1378		T3	11
valid_sources[0x6f]	321456	1			T1	18		T2	1442		T3	20
valid_sources[0x70]	681298	1			T1	21		T2	1382		T3	10
valid_sources[0x71]	325279	1			T1	17		T2	1348		T3	15
valid_sources[0x72]	318698	1			T1	19		T2	1438		T3	9
valid_sources[0x73]	312136	1			T1	24		T2	1440		T3	13
valid_sources[0x74]	318680	1			T1	21		T2	1428		T3	11
valid_sources[0x75]	323781	1			T1	22		T2	1418		T3	13
valid_sources[0x76]	312477	1			T1	17		T2	1422		T3	11
valid_sources[0x77]	338807	1			T1	12		T2	1464		T3	9
valid_sources[0x78]	315828	1			T1	11		T2	1392		T3	16
valid_sources[0x79]	323637	1			T1	22		T2	1346		T3	6
valid_sources[0x7a]	557894	1			T1	21		T2	1395		T3	15
valid_sources[0x7b]	319742	1			T1	16		T2	1390		T3	14
valid_sources[0x7c]	703442	1			T1	20		T2	1443		T3	6
valid_sources[0x7d]	804275	1			T1	15		T2	1421		T3	9
valid_sources[0x7e]	313364	1			T1	19		T2	1458		T3	18
valid_sources[0x7f]	400754	1			T1	21		T2	1422		T3	6
valid_sources[0x80]	913842	1			T1	20		T2	1422		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7431271

1

T1

1294

T2

22051

T3

259

values[0x0]

all_enables

biggest_size

15484465

1

T1

465

T2

58180

T3

471

values[0x1]

all_enables

biggest_size

9083676

1

T1

242

T2

32665

T3

276