Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T104,T192,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12414	0	0
DisabledNoTrigBkwd_A	2147483647	830780	0	0
DisabledNoTrigFwd_A	2147483647	1532360989	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12414	0	0
T39	595434	0	0	0
T40	517823	0	0	0
T62	729530	0	0	0
T63	217900	0	0	0
T68	202939	0	0	0
T99	618179	0	0	0
T104	1300	525	0	0
T178	1081	392	0	0
T179	259387	0	0	0
T180	156045	0	0	0
T181	414347	0	0	0
T182	573351	0	0	0
T183	65631	0	0	0
T184	104838	0	0	0
T192	1820	199	0	0
T193	0	457	0	0
T194	0	1387	0	0
T195	0	1156	0	0
T196	0	178	0	0
T197	0	541	0	0
T198	0	542	0	0
T199	0	1123	0	0
T200	0	811	0	0
T201	0	405	0	0
T202	0	739	0	0
T203	0	522	0	0
T204	0	489	0	0
T205	0	600	0	0
T206	0	568	0	0
T207	0	542	0	0
T208	0	625	0	0
T209	0	613	0	0
T210	201368	0	0	0
T211	694104	0	0	0
T212	307150	0	0	0
T213	429865	0	0	0
T214	48829	0	0	0
T215	22812	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	830780	0	0
T1	45768	28	0	0
T2	574948	2134	0	0
T3	99604	22	0	0
T4	543764	1811	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	2408	0	0
T8	0	2990	0	0
T9	0	2	0	0
T17	0	4404	0	0
T18	0	11748	0	0
T21	174092	11	0	0
T22	128508	0	0	0
T23	21912	5	0	0
T24	108836	93	0	0
T25	0	521	0	0
T31	0	100	0	0
T34	0	101	0	0
T35	0	321	0	0
T36	0	77	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1532360989	0	0
T1	45768	20854	0	0
T2	574948	434213	0	0
T3	99604	58770	0	0
T4	543764	414988	0	0
T5	124308	22132	0	0
T6	25448	25060	0	0
T21	174092	98395	0	0
T22	128508	122578	0	0
T23	21912	17544	0	0
T24	108836	40639	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T178,T203,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701318401	1482	0	0
DisabledNoTrigBkwd_A	701318401	254631	0	0
DisabledNoTrigFwd_A	701318401	312893430	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1482	0	0
T99	618179	0	0	0
T178	1081	392	0	0
T179	259387	0	0	0
T180	156045	0	0	0
T181	414347	0	0	0
T182	573351	0	0	0
T183	65631	0	0	0
T184	104838	0	0	0
T203	0	522	0	0
T206	0	568	0	0
T214	48829	0	0	0
T215	22812	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	254631	0	0
T1	11442	7	0	0
T2	143737	2134	0	0
T3	24901	12	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2125	0	0
T18	0	1811	0	0
T21	43523	7	0	0
T22	32127	0	0	0
T23	5478	5	0	0
T24	27209	51	0	0
T34	0	101	0	0
T36	0	77	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	312893430	0	0
T1	11442	5589	0	0
T2	143737	3023	0	0
T3	24901	6770	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	9371	0	0
T22	32127	30272	0	0
T23	5478	3173	0	0
T24	27209	10416	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T24

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T194,T199
1	1	Covered	T1,T3,T24

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T24

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701318401	4352	0	0
DisabledNoTrigBkwd_A	701318401	187288	0	0
DisabledNoTrigFwd_A	701318401	390966442	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	4352	0	0
T39	297717	0	0	0
T40	517823	0	0	0
T62	364765	0	0	0
T63	108950	0	0	0
T68	202939	0	0	0
T192	910	199	0	0
T194	0	1387	0	0
T199	0	1123	0	0
T201	0	405	0	0
T208	0	625	0	0
T209	0	613	0	0
T210	100684	0	0	0
T211	694104	0	0	0
T212	307150	0	0	0
T213	429865	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	187288	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	3	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	5	0	0
T8	0	1790	0	0
T9	0	1	0	0
T17	0	1396	0	0
T18	0	6316	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	20	0	0
T25	0	192	0	0
T31	0	84	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	390966442	0	0
T1	11442	7393	0	0
T2	143737	143730	0	0
T3	24901	20089	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	5294	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T22

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T104,T193,T198
1	1	Covered	T1,T4,T22

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T24

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701318401	2263	0	0
DisabledNoTrigBkwd_A	701318401	172991	0	0
DisabledNoTrigFwd_A	701318401	407424165	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	2263	0	0
T39	297717	0	0	0
T59	630565	0	0	0
T60	31466	0	0	0
T61	524876	0	0	0
T62	364765	0	0	0
T63	108950	0	0	0
T104	1300	525	0	0
T192	910	0	0	0
T193	0	457	0	0
T198	0	542	0	0
T202	0	739	0	0
T210	100684	0	0	0
T216	10627	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	172991	0	0
T1	11442	12	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1811	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1200	0	0
T9	0	1	0	0
T17	0	3007	0	0
T18	0	17	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	3	0	0
T25	0	183	0	0
T31	0	10	0	0
T35	0	200	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	407424165	0	0
T1	11442	2839	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	7186	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	30272	0	0
T23	5478	4473	0	0
T24	27209	13967	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T21

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T196,T197
1	1	Covered	T1,T3,T21

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701318401	4317	0	0
DisabledNoTrigBkwd_A	701318401	215870	0	0
DisabledNoTrigFwd_A	701318401	421076952	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	4317	0	0
T49	112375	0	0	0
T85	13287	0	0	0
T100	9724	0	0	0
T195	3359	1156	0	0
T196	887	178	0	0
T197	0	541	0	0
T200	0	811	0	0
T204	0	489	0	0
T205	0	600	0	0
T207	0	542	0	0
T217	196971	0	0	0
T218	73336	0	0	0
T219	319498	0	0	0
T220	30557	0	0	0
T221	406145	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	215870	0	0
T1	11442	8	0	0
T2	143737	0	0	0
T3	24901	7	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	278	0	0
T17	0	1	0	0
T18	0	3604	0	0
T21	43523	4	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	19	0	0
T25	0	146	0	0
T31	0	6	0	0
T35	0	121	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	421076952	0	0
T1	11442	5033	0	0
T2	143737	143730	0	0
T3	24901	7104	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	2082	0	0
T22	32127	29976	0	0
T23	5478	4473	0	0
T24	27209	10962	0	0