Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T21
1	0	1	Covered	T1,T2,T21
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T3,T21,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T22
0	1	Covered	T21,T22,T24
1	0	Covered	T3,T18,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T21,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T18,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T27
1	1	Covered	T21,T22,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T2,T24,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T22,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T5,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T21,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T15,T16
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T21,T22
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T17,T18,T9
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T2,T26,T12
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T18,T9,T28
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T18,T29,T30
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T21,T7,T31
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T22,T7,T17
TimeoutSt->Phase0St	172	Covered	T3,T21,T22

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T7,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T18,T9
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T26,T12
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T9,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T7,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1490	0	0
CheckAccumTrig0_A	2147483647	2341	0	0
CheckAccumTrig1_A	2147483647	146	0	0
CheckClr_A	2147483647	1098	0	0
CheckEn_A	2147483647	1208569305	0	0
CheckPhase0_A	2147483647	2734	0	0
CheckPhase1_A	2147483647	2668	0	0
CheckPhase2_A	2147483647	2627	0	0
CheckPhase3_A	2147483647	2584	0	0
CheckTimeout0_A	2147483647	5562	0	0
CheckTimeoutSt1_A	2147483647	540612	0	0
CheckTimeoutSt2_A	2147483647	5117	0	0
CheckTimeoutStTrig_A	2147483647	292	0	0
ErrorStAllEscAsserted_A	2147483647	7261	0	0
ErrorStIsTerminal_A	2147483647	6061	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490	0	0
T5	124308	329	0	0
T7	881824	0	0	0
T15	0	273	0	0
T16	0	297	0	0
T17	3404640	0	0	0
T22	128508	0	0	0
T23	21912	0	0	0
T24	108836	0	0	0
T25	2026796	0	0	0
T31	136928	0	0	0
T32	0	284	0	0
T33	0	307	0	0
T34	416948	0	0	0
T35	606260	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T1	45768	4	0	0
T2	574948	2	0	0
T3	99604	2	0	0
T4	543764	1	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	8	0	0
T8	0	3	0	0
T9	0	2	0	0
T17	0	8	0	0
T18	0	18	0	0
T20	0	1	0	0
T21	174092	2	0	0
T22	128508	0	0	0
T23	21912	1	0	0
T24	108836	3	0	0
T25	0	3	0	0
T31	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	146	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	220456	0	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T10	515744	0	0	0
T18	204067	1	0	0
T19	114151	0	0	0
T20	126739	0	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	550909	3	0	0
T28	0	3	0	0
T30	0	1	0	0
T36	73290	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	6311	0	0	0
T54	66473	0	0	0
T55	420857	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1098	0	0
T2	143737	1	0	0
T3	24901	0	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	220456	2	0	0
T8	210678	0	0	0
T9	912746	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	1702320	5	0	0
T18	408134	10	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	15	0	0
T28	0	2	0	0
T31	68464	4	0	0
T34	104237	0	0	0
T35	303130	0	0	0
T36	146580	0	0	0
T37	0	12	0	0
T40	0	1	0	0
T53	12622	0	0	0
T54	66473	0	0	0
T56	0	3	0	0
T57	0	4	0	0
T58	0	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208569305	0	0
T1	45768	11968	0	0
T2	574948	434210	0	0
T3	99604	39362	0	0
T4	543764	408392	0	0
T5	600	384	0	0
T6	25448	25056	0	0
T21	174092	98393	0	0
T22	128508	93103	0	0
T23	21912	17006	0	0
T24	108836	12443	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2734	0	0
T1	45768	4	0	0
T2	574948	2	0	0
T3	99604	3	0	0
T4	543764	1	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T17	0	6	0	0
T18	0	18	0	0
T21	174092	3	0	0
T22	128508	1	0	0
T23	21912	1	0	0
T24	108836	4	0	0
T25	0	3	0	0
T31	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2668	0	0
T1	45768	4	0	0
T2	574948	1	0	0
T3	99604	3	0	0
T4	543764	1	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T17	0	6	0	0
T18	0	17	0	0
T21	174092	3	0	0
T22	128508	1	0	0
T23	21912	1	0	0
T24	108836	4	0	0
T25	0	3	0	0
T31	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2627	0	0
T1	45768	4	0	0
T2	574948	1	0	0
T3	99604	3	0	0
T4	543764	1	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T17	0	6	0	0
T18	0	16	0	0
T21	174092	3	0	0
T22	128508	1	0	0
T23	21912	1	0	0
T24	108836	4	0	0
T25	0	3	0	0
T31	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T1	45768	4	0	0
T2	574948	1	0	0
T3	99604	3	0	0
T4	543764	1	0	0
T5	124308	0	0	0
T6	25448	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T17	0	6	0	0
T18	0	15	0	0
T21	174092	3	0	0
T22	128508	1	0	0
T23	21912	1	0	0
T24	108836	4	0	0
T25	0	3	0	0
T31	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5562	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	881824	9	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	2553480	1	0	0
T18	612201	29	0	0
T21	43523	1	0	0
T22	96381	3	0	0
T23	16434	0	0	0
T24	81627	1	0	0
T25	1520097	0	0	0
T26	0	24	0	0
T28	0	4	0	0
T31	102696	0	0	0
T34	312711	0	0	0
T35	454695	0	0	0
T36	73290	0	0	0
T37	0	24	0	0
T38	0	1	0	0
T40	0	37	0	0
T53	6311	0	0	0
T59	0	10	0	0
T60	0	3	0	0
T63	0	6	0	0
T64	0	24	0	0
T65	0	3	0	0
T66	0	3	0	0
T67	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	540612	0	0
T3	24901	6	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	881824	1549	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	2553480	45	0	0
T18	612201	2756	0	0
T21	43523	87	0	0
T22	96381	236	0	0
T23	16434	0	0	0
T24	81627	365	0	0
T25	1520097	0	0	0
T26	0	3385	0	0
T28	0	71	0	0
T31	102696	0	0	0
T34	312711	0	0	0
T35	454695	0	0	0
T36	73290	0	0	0
T37	0	2740	0	0
T40	0	3240	0	0
T53	6311	0	0	0
T59	0	2055	0	0
T60	0	1651	0	0
T63	0	1102	0	0
T64	0	1018	0	0
T65	0	926	0	0
T66	0	143	0	0
T67	0	157	0	0
T68	0	138	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5117	0	0
T7	661368	8	0	0
T8	210678	0	0	0
T9	912746	0	0	0
T17	2553480	1	0	0
T18	612201	25	0	0
T22	32127	2	0	0
T26	550909	21	0	0
T28	12367	1	0	0
T29	0	1	0	0
T30	0	32	0	0
T31	102696	0	0	0
T34	312711	0	0	0
T35	454695	0	0	0
T36	146580	0	0	0
T37	364016	17	0	0
T39	0	2	0	0
T40	0	38	0	0
T44	0	1	0	0
T53	12622	0	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T59	0	11	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	0	6	0	0
T64	27230	24	0	0
T65	28303	0	0	0
T66	42582	3	0	0
T67	4097	2	0	0
T68	0	2	0	0
T69	841816	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T7	440912	1	0	0
T12	773393	0	0	0
T21	43523	1	0	0
T22	64254	1	0	0
T23	10956	0	0	0
T24	54418	1	0	0
T25	1013398	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	68464	0	0	0
T34	208474	0	0	0
T35	151565	0	0	0
T37	364016	0	0	0
T38	369788	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T60	0	1	0	0
T65	28303	3	0	0
T66	42582	0	0	0
T67	4097	0	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	21530	0	0	0
T80	64855	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7261	0	0
T5	124308	1517	0	0
T7	881824	0	0	0
T15	0	1422	0	0
T16	0	1408	0	0
T17	3404640	0	0	0
T22	128508	0	0	0
T23	21912	0	0	0
T24	108836	0	0	0
T25	2026796	0	0	0
T31	136928	0	0	0
T32	0	1468	0	0
T33	0	1446	0	0
T34	416948	0	0	0
T35	606260	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6061	0	0
T5	124308	1277	0	0
T7	881824	0	0	0
T15	0	1182	0	0
T16	0	1168	0	0
T17	3404640	0	0	0
T22	128508	0	0	0
T23	21912	0	0	0
T24	108836	0	0	0
T25	2026796	0	0	0
T31	136928	0	0	0
T32	0	1228	0	0
T33	0	1206	0	0
T34	416948	0	0	0
T35	606260	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45768	45416	0	0
T2	574948	574920	0	0
T3	99604	99228	0	0
T4	543764	543736	0	0
T5	212	0	0	0
T6	25448	25060	0	0
T21	174092	173884	0	0
T22	128508	128232	0	0
T23	21912	21700	0	0
T24	108836	108436	0	0
T25	0	2026584	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45768	45416	0	0
T2	574948	574920	0	0
T3	99604	99228	0	0
T4	543764	543736	0	0
T5	124308	22132	0	0
T6	25448	25060	0	0
T21	174092	173884	0	0
T22	128508	128232	0	0
T23	21912	21700	0	0
T24	108836	108436	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T21
1	0	1	Covered	T2,T24,T7
1	1	0	Covered	T1,T22,T7
1	1	1	Covered	T3,T21,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T7
0	1	Covered	T21,T7,T65
1	0	Covered	T3,T26,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T21,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T26,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T7
1	0	Not Covered
1	1	Covered	T21,T7,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T34
1	Covered	T1,T3,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T69

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T2,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T34,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T5,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T7,T34,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T3,T23,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T21,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T15,T16
IdleSt->Phase0St	152	Covered	T1,T2,T21
IdleSt->TimeoutSt	159	Covered	T3,T21,T7
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T37,T81,T82
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T26,T12
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T29,T42
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T30,T45
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T21,T7,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T18,T26
TimeoutSt->Phase0St	172	Covered	T3,T21,T7

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T81,T82
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T26,T12
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T42
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T45
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T7,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701318401	361	0	0
CheckAccumTrig0_A	701318401	893	0	0
CheckAccumTrig1_A	701318401	65	0	0
CheckClr_A	701318401	446	0	0
CheckEn_A	701122566	229556080	0	0
CheckPhase0_A	701318401	1019	0	0
CheckPhase1_A	701318401	986	0	0
CheckPhase2_A	701318401	968	0	0
CheckPhase3_A	701318401	945	0	0
CheckTimeout0_A	701318401	1435	0	0
CheckTimeoutSt1_A	701318401	122725	0	0
CheckTimeoutSt2_A	701318401	1289	0	0
CheckTimeoutStTrig_A	701318401	77	0	0
ErrorStAllEscAsserted_A	701318401	1819	0	0
ErrorStIsTerminal_A	701318401	1519	0	0
EscStateOut_A	701120725	701048020	0	0
u_state_regs_A	701318401	701118036	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	361	0	0
T5	31077	55	0	0
T7	220456	0	0	0
T15	0	74	0	0
T16	0	65	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	69	0	0
T33	0	98	0	0
T34	104237	0	0	0
T35	151565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	893	0	0
T1	11442	1	0	0
T2	143737	2	0	0
T3	24901	0	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T8	0	1	0	0
T18	0	5	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	1	0	0
T24	27209	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	65	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	220456	0	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	2	0	0
T28	0	3	0	0
T30	0	1	0	0
T37	0	2	0	0
T39	0	5	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	446	0	0
T2	143737	1	0	0
T3	24901	0	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T18	0	3	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	6	0	0
T28	0	2	0	0
T37	0	4	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701122566	229556080	0	0
T1	11442	5589	0	0
T2	143737	3023	0	0
T3	24901	2047	0	0
T4	135941	135934	0	0
T5	150	96	0	0
T6	6362	6264	0	0
T21	43523	9371	0	0
T22	32127	30271	0	0
T23	5478	2638	0	0
T24	27209	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1019	0	0
T1	11442	1	0	0
T2	143737	2	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	4	0	0
T18	0	5	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	1	0	0
T24	27209	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	986	0	0
T1	11442	1	0	0
T2	143737	1	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	4	0	0
T18	0	5	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	1	0	0
T24	27209	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	968	0	0
T1	11442	1	0	0
T2	143737	1	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	4	0	0
T18	0	5	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	1	0	0
T24	27209	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	945	0	0
T1	11442	1	0	0
T2	143737	1	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	4	0	0
T18	0	5	0	0
T21	43523	2	0	0
T22	32127	0	0	0
T23	5478	1	0	0
T24	27209	1	0	0
T34	0	1	0	0
T36	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1435	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	220456	4	0	0
T18	0	23	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	8	0	0
T28	0	4	0	0
T37	0	10	0	0
T64	0	10	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	122725	0	0
T3	24901	6	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	220456	458	0	0
T18	0	2290	0	0
T21	43523	87	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	955	0	0
T28	0	71	0	0
T37	0	1239	0	0
T64	0	424	0	0
T65	0	628	0	0
T66	0	44	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1289	0	0
T7	220456	3	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	851160	0	0	0
T18	204067	22	0	0
T26	0	6	0	0
T28	0	1	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	8	0	0
T39	0	2	0	0
T53	6311	0	0	0
T59	0	2	0	0
T64	0	10	0	0
T66	0	1	0	0
T67	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	77	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T7	220456	1	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T60	0	1	0	0
T65	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1819	0	0
T5	31077	378	0	0
T7	220456	0	0	0
T15	0	369	0	0
T16	0	344	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	358	0	0
T33	0	370	0	0
T34	104237	0	0	0
T35	151565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1519	0	0
T5	31077	318	0	0
T7	220456	0	0	0
T15	0	309	0	0
T16	0	284	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	298	0	0
T33	0	310	0	0
T34	104237	0	0	0
T35	151565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701120725	701048020	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	53	0	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0
T25	0	506646	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	701118036	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T22

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T25

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T23,T24
1	0	1	Covered	T4,T7,T31
1	1	0	Covered	T3,T24,T7
1	1	1	Covered	T22,T24,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T18
0	1	Covered	T22,T24,T65
1	0	Covered	T26,T40,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T24,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T40,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T24,T18
1	0	Not Covered
1	1	Covered	T22,T24,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T24
1	Covered	T4,T31,T35

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T18,T9,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T24,T8,T56

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T24,T31
1	Covered	T1,T22,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T5,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T4,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T4,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T35,T17,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T4,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T22
Phase1St	198	Covered	T1,T4,T22
Phase2St	215	Covered	T1,T4,T22
Phase3St	233	Covered	T1,T4,T22
TerminalSt	249	Covered	T1,T4,T22
TimeoutSt	159	Covered	T22,T24,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T15,T16
IdleSt->Phase0St	152	Covered	T1,T4,T25
IdleSt->TimeoutSt	159	Covered	T22,T24,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T83,T84
Phase0St->Phase1St	198	Covered	T1,T4,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T42,T85,T86
Phase1St->Phase2St	215	Covered	T1,T4,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T85,T87,T88
Phase2St->Phase3St	233	Covered	T1,T4,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T89,T90,T91
Phase3St->TerminalSt	249	Covered	T1,T4,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T31,T18,T9
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T26,T64
TimeoutSt->Phase0St	172	Covered	T22,T24,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T26,T64,T66
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T83,T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T42,T85,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T85,T87,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T89,T90,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T22,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T31,T9,T56
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701318401	379	0	0
CheckAccumTrig0_A	701318401	460	0	0
CheckAccumTrig1_A	701318401	20	0	0
CheckClr_A	701318401	199	0	0
CheckEn_A	701122566	313650953	0	0
CheckPhase0_A	701318401	540	0	0
CheckPhase1_A	701318401	529	0	0
CheckPhase2_A	701318401	523	0	0
CheckPhase3_A	701318401	516	0	0
CheckTimeout0_A	701318401	1283	0	0
CheckTimeoutSt1_A	701318401	144987	0	0
CheckTimeoutSt2_A	701318401	1195	0	0
CheckTimeoutStTrig_A	701318401	67	0	0
ErrorStAllEscAsserted_A	701318401	1791	0	0
ErrorStIsTerminal_A	701318401	1491	0	0
EscStateOut_A	701120725	701048020	0	0
u_state_regs_A	701318401	701118036	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	379	0	0
T5	31077	107	0	0
T7	220456	0	0	0
T15	0	64	0	0
T16	0	72	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	54	0	0
T33	0	82	0	0
T34	104237	0	0	0
T35	151565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	460	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T17	0	2	0	0
T18	0	2	0	0
T20	0	1	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	20	0	0
T26	550909	1	0	0
T28	12367	0	0	0
T37	364016	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T64	27230	0	0	0
T65	28303	0	0	0
T66	42582	0	0	0
T67	4097	0	0	0
T69	841816	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	199	0	0
T8	105339	0	0	0
T9	456373	1	0	0
T17	851160	1	0	0
T18	204067	0	0	0
T19	114151	0	0	0
T26	0	2	0	0
T31	34232	2	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	6	0	0
T53	6311	0	0	0
T54	66473	0	0	0
T56	0	2	0	0
T57	0	3	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701122566	313650953	0	0
T1	11442	590	0	0
T2	143737	143729	0	0
T3	24901	24806	0	0
T4	135941	590	0	0
T5	150	96	0	0
T6	6362	6264	0	0
T21	43523	43470	0	0
T22	32127	800	0	0
T23	5478	4472	0	0
T24	27209	8005	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	540	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	43523	0	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	529	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	43523	0	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	523	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	43523	0	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	516	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	0	0	0
T4	135941	1	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T8	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	43523	0	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1283	0	0
T7	220456	0	0	0
T17	851160	0	0	0
T18	204067	1	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	506699	0	0	0
T26	0	7	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T59	0	4	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	144987	0	0
T7	220456	0	0	0
T17	851160	0	0	0
T18	204067	75	0	0
T22	32127	101	0	0
T23	5478	0	0	0
T24	27209	365	0	0
T25	506699	0	0	0
T26	0	1160	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T59	0	699	0	0
T63	0	122	0	0
T64	0	86	0	0
T65	0	160	0	0
T66	0	55	0	0
T67	0	157	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1195	0	0
T26	550909	6	0	0
T28	12367	0	0	0
T30	0	32	0	0
T37	364016	0	0	0
T40	0	2	0	0
T44	0	1	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T59	0	4	0	0
T63	0	1	0	0
T64	27230	2	0	0
T65	28303	0	0	0
T66	42582	1	0	0
T67	4097	1	0	0
T68	0	1	0	0
T69	841816	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	67	0	0
T7	220456	0	0	0
T17	851160	0	0	0
T18	204067	0	0	0
T22	32127	1	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T42	0	1	0	0
T65	0	1	0	0
T71	0	1	0	0
T82	0	1	0	0
T85	0	3	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1791	0	0
T5	31077	376	0	0
T7	220456	0	0	0
T15	0	339	0	0
T16	0	353	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	358	0	0
T33	0	365	0	0
T34	104237	0	0	0
T35	151565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1491	0	0
T5	31077	316	0	0
T7	220456	0	0	0
T15	0	279	0	0
T16	0	293	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	298	0	0
T33	0	305	0	0
T34	104237	0	0	0
T35	151565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701120725	701048020	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	53	0	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0
T25	0	506646	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	701118036	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T3,T21
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T21

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T22
1	0	1	Covered	T1,T21,T25
1	1	0	Covered	T6,T22,T7
1	1	1	Covered	T22,T7,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T7,T17
0	1	Covered	T37,T59,T60
1	0	Covered	T37,T40,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T7,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T37,T40,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T7,T17
1	0	Not Covered
1	1	Covered	T37,T59,T60

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T25
1	Covered	T1,T24,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T7,T18,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T24,T25
1	Covered	T3,T21,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T25,T7,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T5,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T24,T7,T35

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T21,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T21,T25,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T21
Phase1St	198	Covered	T1,T3,T21
Phase2St	215	Covered	T1,T3,T21
Phase3St	233	Covered	T1,T3,T21
TerminalSt	249	Covered	T1,T3,T21
TimeoutSt	159	Covered	T22,T7,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T15,T16
IdleSt->Phase0St	152	Covered	T1,T3,T21
IdleSt->TimeoutSt	159	Covered	T22,T7,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T83,T82
Phase0St->Phase1St	198	Covered	T1,T3,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T40,T97
Phase1St->Phase2St	215	Covered	T1,T3,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T9,T26
Phase2St->Phase3St	233	Covered	T1,T3,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T18,T29,T98
Phase3St->TerminalSt	249	Covered	T1,T3,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T18,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T22,T7,T17
TimeoutSt->Phase0St	172	Covered	T37,T59,T60

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T7,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T37,T59,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T7,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T7,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T83,T52,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T40,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T9,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T29,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T26,T61
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701318401	396	0	0
CheckAccumTrig0_A	701318401	494	0	0
CheckAccumTrig1_A	701318401	30	0	0
CheckClr_A	701318401	227	0	0
CheckEn_A	701122566	358874727	0	0
CheckPhase0_A	701318401	596	0	0
CheckPhase1_A	701318401	583	0	0
CheckPhase2_A	701318401	570	0	0
CheckPhase3_A	701318401	561	0	0
CheckTimeout0_A	701318401	1219	0	0
CheckTimeoutSt1_A	701318401	114290	0	0
CheckTimeoutSt2_A	701318401	1106	0	0
CheckTimeoutStTrig_A	701318401	81	0	0
ErrorStAllEscAsserted_A	701318401	1812	0	0
ErrorStIsTerminal_A	701318401	1512	0	0
EscStateOut_A	701120725	701048020	0	0
u_state_regs_A	701318401	701118036	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	396	0	0
T5	31077	84	0	0
T7	220456	0	0	0
T15	0	61	0	0
T16	0	82	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	88	0	0
T33	0	81	0	0
T34	104237	0	0	0
T35	151565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	494	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T17	0	1	0	0
T18	0	7	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	30	0	0
T12	773393	0	0	0
T37	364016	2	0	0
T38	369788	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T66	42582	0	0	0
T67	4097	0	0	0
T79	21530	0	0	0
T80	64855	0	0	0
T83	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	1300	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	227	0	0
T8	105339	0	0	0
T9	456373	1	0	0
T10	515744	0	0	0
T18	204067	5	0	0
T19	114151	0	0	0
T20	126739	0	0	0
T26	0	7	0	0
T29	0	1	0	0
T36	73290	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T53	6311	0	0	0
T54	66473	0	0	0
T55	420857	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T105	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701122566	358874727	0	0
T1	11442	594	0	0
T2	143737	143729	0	0
T3	24901	2100	0	0
T4	135941	135934	0	0
T5	150	96	0	0
T6	6362	6264	0	0
T21	43523	2082	0	0
T22	32127	29975	0	0
T23	5478	4472	0	0
T24	27209	1932	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	596	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T17	0	1	0	0
T18	0	7	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	583	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T17	0	1	0	0
T18	0	6	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	570	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T17	0	1	0	0
T18	0	5	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	561	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T21	43523	1	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1219	0	0
T7	220456	1	0	0
T17	851160	1	0	0
T18	204067	2	0	0
T22	32127	2	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	9	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T37	0	10	0	0
T59	0	2	0	0
T60	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	114290	0	0
T7	220456	91	0	0
T17	851160	45	0	0
T18	204067	256	0	0
T22	32127	135	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	1270	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T37	0	1326	0	0
T59	0	821	0	0
T60	0	702	0	0
T64	0	83	0	0
T66	0	44	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1106	0	0
T7	220456	1	0	0
T17	851160	1	0	0
T18	204067	1	0	0
T22	32127	2	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T26	0	9	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T37	0	7	0	0
T59	0	1	0	0
T62	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	81	0	0
T12	773393	0	0	0
T30	0	1	0	0
T37	364016	1	0	0
T38	369788	0	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	42582	0	0	0
T67	4097	0	0	0
T71	0	2	0	0
T72	0	1	0	0
T79	21530	0	0	0
T80	64855	0	0	0
T104	1300	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1812	0	0
T5	31077	381	0	0
T7	220456	0	0	0
T15	0	368	0	0
T16	0	351	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	358	0	0
T33	0	354	0	0
T34	104237	0	0	0
T35	151565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1512	0	0
T5	31077	321	0	0
T7	220456	0	0	0
T15	0	308	0	0
T16	0	291	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	298	0	0
T33	0	294	0	0
T34	104237	0	0	0
T35	151565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701120725	701048020	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	53	0	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0
T25	0	506646	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	701118036	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T3,T24
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T24

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T24

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T24
1	0	1	Covered	T24,T25,T7
1	1	0	Covered	T3,T6,T22
1	1	1	Covered	T7,T18,T64

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T18,T64
0	1	Covered	T65,T42,T70
1	0	Covered	T18,T37,T38

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T18,T64
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T37,T38

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T64
1	0	Covered	T27
1	1	Covered	T65,T42,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T24
1	Covered	T25,T31,T56

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T24,T25
1	Covered	T3,T18,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T25
1	Covered	T24,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T7,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T5,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T3,T24,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T1,T24,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T3,T24,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T16
1	0	Covered	T24,T25,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T24
Phase1St	198	Covered	T1,T3,T24
Phase2St	215	Covered	T1,T3,T24
Phase3St	233	Covered	T1,T3,T24
TerminalSt	249	Covered	T1,T3,T24
TimeoutSt	159	Covered	T7,T18,T64

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T15,T16
IdleSt->Phase0St	152	Covered	T1,T3,T24
IdleSt->TimeoutSt	159	Covered	T7,T18,T64
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T18,T9
Phase0St->Phase1St	198	Covered	T1,T3,T24
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T109,T110
Phase1St->Phase2St	215	Covered	T1,T3,T24
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T59,T78,T111
Phase2St->Phase3St	233	Covered	T1,T3,T24
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T112,T91
Phase3St->TerminalSt	249	Covered	T1,T3,T24
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T31,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T18,T64
TimeoutSt->Phase0St	172	Covered	T18,T65,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T24
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T64
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T65,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T64
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T64
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T18,T9
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T24
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T24
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T109,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T24
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T59,T78,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T24
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T112,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T31,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T24
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701318401	354	0	0
CheckAccumTrig0_A	701318401	494	0	0
CheckAccumTrig1_A	701318401	31	0	0
CheckClr_A	701318401	226	0	0
CheckEn_A	701122566	306487545	0	0
CheckPhase0_A	701318401	579	0	0
CheckPhase1_A	701318401	570	0	0
CheckPhase2_A	701318401	566	0	0
CheckPhase3_A	701318401	562	0	0
CheckTimeout0_A	701318401	1625	0	0
CheckTimeoutSt1_A	701318401	158610	0	0
CheckTimeoutSt2_A	701318401	1527	0	0
CheckTimeoutStTrig_A	701318401	67	0	0
ErrorStAllEscAsserted_A	701318401	1839	0	0
ErrorStIsTerminal_A	701318401	1539	0	0
EscStateOut_A	701120725	701048020	0	0
u_state_regs_A	701318401	701118036	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	354	0	0
T5	31077	83	0	0
T7	220456	0	0	0
T15	0	74	0	0
T16	0	78	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	73	0	0
T33	0	46	0	0
T34	104237	0	0	0
T35	151565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	494	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T17	0	5	0	0
T18	0	4	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	31	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T10	515744	0	0	0
T18	204067	1	0	0
T19	114151	0	0	0
T20	126739	0	0	0
T36	73290	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	6311	0	0	0
T54	66473	0	0	0
T55	420857	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	226	0	0
T7	220456	1	0	0
T8	105339	0	0	0
T9	456373	1	0	0
T17	851160	4	0	0
T18	204067	2	0	0
T31	34232	2	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	2	0	0
T53	6311	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	4	0	0
T60	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701122566	306487545	0	0
T1	11442	5195	0	0
T2	143737	143729	0	0
T3	24901	10409	0	0
T4	135941	135934	0	0
T5	150	96	0	0
T6	6362	6264	0	0
T21	43523	43470	0	0
T22	32127	32057	0	0
T23	5478	5424	0	0
T24	27209	1924	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	579	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T17	0	4	0	0
T18	0	4	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	570	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T17	0	4	0	0
T18	0	4	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	566	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T17	0	4	0	0
T18	0	4	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	562	0	0
T1	11442	1	0	0
T2	143737	0	0	0
T3	24901	1	0	0
T4	135941	0	0	0
T5	31077	0	0	0
T6	6362	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T17	0	4	0	0
T18	0	4	0	0
T21	43523	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1625	0	0
T7	220456	4	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	851160	0	0	0
T18	204067	3	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T40	0	37	0	0
T53	6311	0	0	0
T59	0	4	0	0
T60	0	2	0	0
T63	0	5	0	0
T64	0	10	0	0
T65	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	158610	0	0
T7	220456	1000	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	851160	0	0	0
T18	204067	135	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	175	0	0
T40	0	3240	0	0
T53	6311	0	0	0
T59	0	535	0	0
T60	0	949	0	0
T63	0	980	0	0
T64	0	425	0	0
T65	0	138	0	0
T68	0	138	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1527	0	0
T7	220456	4	0	0
T8	105339	0	0	0
T9	456373	0	0	0
T17	851160	0	0	0
T18	204067	2	0	0
T29	0	1	0	0
T31	34232	0	0	0
T34	104237	0	0	0
T35	151565	0	0	0
T36	73290	0	0	0
T37	0	2	0	0
T40	0	36	0	0
T53	6311	0	0	0
T59	0	4	0	0
T60	0	2	0	0
T63	0	5	0	0
T64	0	10	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	67	0	0
T12	773393	0	0	0
T37	364016	0	0	0
T38	369788	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T57	682822	0	0	0
T58	43527	0	0	0
T65	28303	1	0	0
T66	42582	0	0	0
T67	4097	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	21530	0	0	0
T80	64855	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1839	0	0
T5	31077	382	0	0
T7	220456	0	0	0
T15	0	346	0	0
T16	0	360	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	394	0	0
T33	0	357	0	0
T34	104237	0	0	0
T35	151565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	1539	0	0
T5	31077	322	0	0
T7	220456	0	0	0
T15	0	286	0	0
T16	0	300	0	0
T17	851160	0	0	0
T22	32127	0	0	0
T23	5478	0	0	0
T24	27209	0	0	0
T25	506699	0	0	0
T31	34232	0	0	0
T32	0	334	0	0
T33	0	297	0	0
T34	104237	0	0	0
T35	151565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701120725	701048020	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	53	0	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0
T25	0	506646	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701318401	701118036	0	0
T1	11442	11354	0	0
T2	143737	143730	0	0
T3	24901	24807	0	0
T4	135941	135934	0	0
T5	31077	5533	0	0
T6	6362	6265	0	0
T21	43523	43471	0	0
T22	32127	32058	0	0
T23	5478	5425	0	0
T24	27209	27109	0	0