Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T30,T25
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14035	0	0
DisabledNoTrigBkwd_A	2147483647	753312	0	0
DisabledNoTrigFwd_A	2147483647	1372513319	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14035	0	0
T1	0	667	0	0
T17	350353	0	0	0
T18	976323	0	0	0
T19	164078	0	0	0
T20	111017	0	0	0
T25	0	1102	0	0
T26	815353	0	0	0
T30	4600	1063	0	0
T38	650273	0	0	0
T41	0	568	0	0
T44	0	359	0	0
T68	2730	495	0	0
T71	0	667	0	0
T77	21671	0	0	0
T85	31228	0	0	0
T86	6371	0	0	0
T191	0	2035	0	0
T223	4178	696	0	0
T224	3506	361	0	0
T225	0	444	0	0
T226	0	418	0	0
T227	0	732	0	0
T228	0	922	0	0
T229	0	267	0	0
T230	0	791	0	0
T231	0	1157	0	0
T232	0	574	0	0
T233	0	447	0	0
T234	0	270	0	0
T235	145415	0	0	0
T236	178778	0	0	0
T237	199594	0	0	0
T238	39646	0	0	0
T239	19238	0	0	0
T240	60303	0	0	0
T241	311945	0	0	0
T242	123297	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	753312	0	0
T1	3889	4	0	0
T2	777708	9808	0	0
T3	149880	98	0	0
T4	733652	90	0	0
T6	151508	12	0	0
T7	0	1342	0	0
T8	0	3138	0	0
T9	0	9591	0	0
T10	0	1416	0	0
T16	0	1109	0	0
T17	0	2044	0	0
T21	0	40	0	0
T23	0	219	0	0
T24	0	18	0	0
T25	0	40	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	251	0	0
T30	18400	16	0	0
T31	103252	0	0	0
T35	0	9	0	0
T38	0	1625	0	0
T50	11757	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372513319	0	0
T1	15556	12513	0	0
T2	777708	669603	0	0
T3	149880	115869	0	0
T4	733652	522779	0	0
T6	151508	75671	0	0
T27	22340	19303	0	0
T28	15500	8725	0	0
T29	1457316	746767	0	0
T30	18400	12865	0	0
T31	103252	79937	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T224,T226
1	1	Covered	T2,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	623977616	5989	0	0
DisabledNoTrigBkwd_A	623977616	250880	0	0
DisabledNoTrigFwd_A	623977616	304577230	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	5989	0	0
T17	350353	0	0	0
T18	976323	0	0	0
T19	164078	0	0	0
T20	111017	0	0	0
T26	815353	0	0	0
T38	650273	0	0	0
T68	2730	495	0	0
T77	21671	0	0	0
T85	31228	0	0	0
T86	6371	0	0	0
T191	0	2035	0	0
T224	0	361	0	0
T226	0	418	0	0
T227	0	732	0	0
T230	0	791	0	0
T231	0	1157	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	250880	0	0
T2	194427	8889	0	0
T3	37470	98	0	0
T4	183413	21	0	0
T6	37877	12	0	0
T8	0	909	0	0
T9	0	116	0	0
T16	0	1109	0	0
T21	0	25	0	0
T24	0	5	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	9	0	0
T50	3919	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	304577230	0	0
T1	3889	3097	0	0
T2	194427	187107	0	0
T3	37470	3687	0	0
T4	183413	82437	0	0
T6	37877	636	0	0
T27	5585	2767	0	0
T28	3875	2613	0	0
T29	364329	364236	0	0
T30	4600	3180	0	0
T31	25813	20263	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T28,T29

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T223,T225,T232
1	1	Covered	T2,T28,T29

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T28,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T29,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	623977616	1714	0	0
DisabledNoTrigBkwd_A	623977616	141181	0	0
DisabledNoTrigFwd_A	623977616	362790349	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1714	0	0
T223	4178	696	0	0
T224	3506	0	0	0
T225	0	444	0	0
T232	0	574	0	0
T235	145415	0	0	0
T236	178778	0	0	0
T237	199594	0	0	0
T238	39646	0	0	0
T239	19238	0	0	0
T240	60303	0	0	0
T241	311945	0	0	0
T242	123297	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	141181	0	0
T2	194427	419	0	0
T3	37470	0	0	0
T4	183413	5	0	0
T6	37877	0	0	0
T8	0	1100	0	0
T9	0	2146	0	0
T10	0	707	0	0
T17	0	1047	0	0
T21	0	4	0	0
T24	0	5	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	78	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	1625	0	0
T50	3919	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	362790349	0	0
T1	3889	3122	0	0
T2	194427	145908	0	0
T3	37470	37394	0	0
T4	183413	165344	0	0
T6	37877	640	0	0
T27	5585	5512	0	0
T28	3875	2759	0	0
T29	364329	7106	0	0
T30	4600	3200	0	0
T31	25813	25736	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T28,T29

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T25,T229
1	1	Covered	T2,T28,T29

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T28,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T29,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	623977616	3000	0	0
DisabledNoTrigBkwd_A	623977616	188323	0	0
DisabledNoTrigFwd_A	623977616	347015308	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	3000	0	0
T5	182982	0	0	0
T7	274193	0	0	0
T21	131244	0	0	0
T22	41045	0	0	0
T23	563487	0	0	0
T24	34564	0	0	0
T25	0	1102	0	0
T30	4600	1063	0	0
T31	25813	0	0	0
T35	36004	0	0	0
T41	0	568	0	0
T50	3919	0	0	0
T229	0	267	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	188323	0	0
T2	194427	205	0	0
T3	37470	0	0	0
T4	183413	4	0	0
T6	37877	0	0	0
T8	0	1129	0	0
T9	0	2392	0	0
T21	0	1	0	0
T24	0	3	0	0
T25	0	40	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	173	0	0
T30	4600	16	0	0
T31	25813	0	0	0
T50	3919	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	347015308	0	0
T1	3889	3137	0	0
T2	194427	168251	0	0
T3	37470	37394	0	0
T4	183413	172024	0	0
T6	37877	36606	0	0
T27	5585	5512	0	0
T28	3875	2759	0	0
T29	364329	11189	0	0
T30	4600	3226	0	0
T31	25813	8202	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T28
1	0	Covered	T2,T27,T29
1	1	Covered	T1,T2,T28

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T71,T228
1	1	Covered	T1,T2,T28

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	623977616	3332	0	0
DisabledNoTrigBkwd_A	623977616	172928	0	0
DisabledNoTrigFwd_A	623977616	358130432	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	3332	0	0
T1	3889	667	0	0
T2	194427	0	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T44	0	359	0	0
T71	0	667	0	0
T228	0	922	0	0
T233	0	447	0	0
T234	0	270	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	172928	0	0
T1	3889	4	0	0
T2	194427	295	0	0
T3	37470	0	0	0
T4	183413	60	0	0
T6	37877	0	0	0
T7	0	1342	0	0
T9	0	4937	0	0
T10	0	709	0	0
T17	0	997	0	0
T21	0	10	0	0
T23	0	219	0	0
T24	0	5	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	358130432	0	0
T1	3889	3157	0	0
T2	194427	168337	0	0
T3	37470	37394	0	0
T4	183413	102974	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	594	0	0
T29	364329	364236	0	0
T30	4600	3259	0	0
T31	25813	25736	0	0